JP2000077385A - Via forming method with high reliability for semiconductor device - Google Patents

Abstract

(57) Abstract: A method for forming a via of a semiconductor device having high reliability. SOLUTION: In a method of manufacturing a semiconductor device in which an upper metal wiring and a lower conductive layer are connected to a via, after the upper metal wiring is patterned, electric charges are accumulated on a surface of a metal plug filling the via. Plasma-less ozone ashing is carried out to prevent the occurrence of ozone ashing. Non-plasma ozone ashing oxidizes the surface of the metal plug that fills the misaligned and exposed via with respect to the upper metal wiring and absorbs positive charges, so that the exposed metal plug is not corroded by an electrochemical reaction. Therefore, the reliability of the via can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device. The present invention relates to a method of manufacturing a semiconductor device capable of preventing accumulated and electrochemical corrosion.

[0002]

2. Description of the Related Art As semiconductor devices become smaller and lighter,
The design rules were reduced, and the RC delay due to wiring became an important factor in determining the operation speed. As a result, a multilayer wiring structure has been put into practical use,
In the case of a highly integrated circuit device such as a microprocessor, the required number of metal wiring layers is reduced from existing 2-3 layers to 4-6 layers.
In the case of a higher integrated circuit device, it is expected that a higher wiring layer will be used in the future. In a semiconductor device having such a multilayer wiring structure, characteristics of vias connecting metal wirings are more important. Further, the size of the via is also reduced due to the reduction of the minimum line width (design rule) of the metal wiring.
As a result, it has become an important problem to suppress the occurrence of defects and to ensure a low contact resistance.

[0003] Excellent electron transfer resistance (Electromigration r)
Tungsten (W) having an esistance (EM) characteristic and a low non-resistance value is widely used as a material for filling a via.

FIG. 1 is a cross-sectional view for explaining a conventional method of forming a via of a semiconductor device.

Referring to FIG. 1, an aluminum (Al) film and a titanium nitride (Titanium nitride) are formed on a semiconductor substrate (not shown) on which a predetermined circuit pattern is formed.
niumNitride; hereinafter, referred to as 'TiN'. A) The lower metal wiring 12 and the first capping layer 14 are formed by sequentially sputtering the film and patterning the film in a photolithography process. Next, an oxide film is deposited on the resultant structure by a chemical vapor deposition (CVD) method to form an intermetal dielectric film (IM).
D) After the formation of 16, the interlayer insulating film 16 is etched by a photolithography process to form a via 18 exposing the lower metal wiring 12. Titanium (hereinafter referred to as “Ti”) or Ti / T is formed on the resultant product.
After a barrier metal layer (not shown) is formed by depositing iN by a chemical vapor deposition (CVD) method, a tungsten film is formed thereon by chemical vapor deposition (CV).
By the method D), vapor deposition is performed to a thickness enough to bury the via 18 sufficiently. Next, a tungsten plug 20 for filling the via is formed by etching the tungsten film until the surface of the interlayer insulating film 16 is exposed by a chemical physical polishing (CMP) method. After sequentially sputtering a Ti film, an aluminum (Al) film and a TiN film on the resultant product, the film is patterned by a photolithography process.
The ohmic layer 22, the upper metal wiring 24, and the second capping layer 26 are formed.

[0006] As the design rule of the semiconductor device is reduced, the line width of the metal wiring is reduced, whereby the size of the via connecting the metal wiring is also reduced. However, there is a limit in reducing the size of the via due to various restrictions such as an embedding limit of deposition conditions and an increase in contact resistance. Therefore, in a semiconductor device having a design rule of 0.35 μm or less, the size of the metal wiring is slightly larger or almost the same as the size of the via, so that the overlap margin between the via and the metal wiring is reduced. Is almost gone. Therefore, when the upper metal wiring is patterned using a photoresist film, if a misalignment (refer to 'a' in FIG. 1) occurs with respect to the via due to a margin limit of a photographic process, one of the surfaces of the via plug embedding the via is removed. The part is exposed. In particular, when the via plug is formed of tungsten, if the photoresist film is ashed with oxygen (O ₂ ) plasma after patterning the upper metal wiring, electric charges are accumulated in the tungsten plug by the plasma. The tungsten plugs with the accumulated charges are connected to a subsequent wet strip.
In the process, when exposed to an organic stripper, there is a problem that the tungsten plug causes an electrochemical reaction and is corroded.

FIG. 2 shows the pH index of a chemical solution (hereinafter, referred to as “pH index”).
Called 'pH'. ), The electrochemical potential of tungsten (hereinafter referred to as 'E (V)')
Called. 4) is a graph showing the values of FIG.

Referring to FIG. 2, in a region where the value of E (V) is equal to or greater than 0 (that is, E (V) ≧ 0), the tungsten film is treated with a chemical solution having a pH of approximately 4 or less. W on the surface
It has been shown that an O ₃ film is formed and has resistance to corrosion. However, a corrosion reaction of the tungsten film occurs for a chemical solution having a pH of 4 or more. Generally, the widely used organic stripper has a pH of 4 or more, so that when the upper metal line is misaligned with the via, the exposed tungsten plug is corroded during the subsequent stripping process.

Generally, in order for a tungsten film to corrode, a strong electrochemical reaction must be performed, and a sufficient charge must be supplied for this purpose. Therefore, the corrosion of the tungsten film may not be so fast unless sufficient charge is supplied, so that pitting may occur on the surface. However, after a process using plasma, for example, a dry etching process or an ashing process, positive charges are accumulated in the metal wiring. In particular, during the ashing process using oxygen plasma, the accumulation of positive charges is increased, and the positive charges are also stored in the via plugs connected to the metal wiring. In some cases, the accumulation of positive charges is further deepened. Anodized metal wiring including the via plug in this way (polarized metal line)
After a subsequent chemical solution treatment step, for example, a stripping step, a strong electrochemical reaction occurs on the surface of the exposed via plug, that is, the anodized tungsten plug,
If the corrosion of the tungsten plug is enhanced and severe,
At the bottom of the via, the tungsten plug is completely melted and a contact failure occurs.

[0010]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the conventional method by patterning an upper metal wiring in a multilayer wiring structure, and then forming a via plug by plasma in a subsequent stage. It is an object of the present invention to provide a method of manufacturing a semiconductor device, which can prevent electric charges from accumulating in a semiconductor device and electrochemically corroding.

[0011]

In order to achieve the above object, the present invention provides an upper metal wiring layer and a lower conductive layer.
In a method of manufacturing a semiconductor device in which a layer is connected to a metal plug embedded in a via, a first upper portion of the metal plug is exposed and an upper metal wiring layer covering a second upper portion of the metal plug is provided. Oxidizing the first upper portion of the metal plug by a plasmaless ozone ashing process to prevent electrochemical corrosion.

Preferably, the non-plasma ozone ashing is performed at a temperature of 300 to 400 ° C.

According to another aspect of the present invention, a lower conductive layer is formed on a semiconductor substrate, an interlayer insulating film is formed on the lower conductive layer, and the interlayer film is etched. Forming a via in the interlayer film where the lower conductive layer is exposed, filling the via with a metal plug, forming a metal wiring layer on the interlayer insulating film and the metal plug, A semiconductor device comprising a step of patterning the upper metal wiring layer after forming a photoresist film pattern on the metal wiring layer; and a step of performing plasma-free ozone ashing on the photoresist film pattern. And a method for producing the same.

[0014] Preferably, the metal plug is made of tungsten.

Preferably, the photoresist film pattern is further stripped with a chemical solution.

Preferably, the non-plasma ozone ashing process is performed at a temperature of 300 to 400.degree.

Preferably, the exposed surface of the metal plug is oxidized by plasma-free ozone ashing, and the oxidized layer prevents the accumulation of electric charges on the exposed surface of the metal plug.

[0018]

Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a flowchart showing a preferred embodiment of the present invention.

Referring to FIG. 3, after the upper metal wiring is patterned, the photoresist film pattern used as the etching mask is ashed with no plasma ozone during the patterning process, thereby misaligning the upper metal wiring. The surface of a via plug, for example, a tungsten plug, which buries the exposed via, is oxidized. next,
Perform strip and wash steps with chemical solution.

In general, ozone (O ₃ ) has a strong oxidizing ability and is itself an unstable molecule, so it decomposes immediately and depletes the charge existing on the surface of the wafer. Cause Therefore, the chemical solution used in the stripping process has a pH of 4 or more, but has resistance to corrosion since the surface of the tungsten plug exposed by ozone ashing is oxidized.
In addition, since the ozone ashing is performed without using plasma, positive charges are not accumulated inside the metal wiring and the exposed tungsten plug. Therefore, during the subsequent stripping process, the exposed tungsten plug of the via is not corroded by the electrochemical reaction.

FIGS. 4 to 6 are cross-sectional views illustrating a method of forming a via of a semiconductor device according to a preferred embodiment of the present invention.

FIG. 4 shows the step of forming the via 108.
After forming an insulating layer (not shown) on a semiconductor substrate (not shown) on which a predetermined circuit pattern is formed,
On top of this, a metal, for example, aluminum (Al)
A lower metal wiring (also referred to as a lower conductive layer) 102 is formed by sputtering with a thickness of 000 mm. Next, a first capping layer 104 is formed on the lower metal wiring 102 by sputtering TiN to a thickness of about 250 °. At this time, the first capping layer 104 is formed by sputtering Ti to a thickness of about 100 °
N can be formed by sputtering at a thickness of about 400 °.

Next, after the first capping layer 104 and the lower metal wiring 102 are patterned by a photolithography process, an insulating material, for example, an oxide is deposited on the resultant product by a chemical vapor deposition (CVD) method for about 10,000.
The interlayer insulating film 106 is formed by vapor deposition with a thickness of about 15000 °. In the photolithography process, the interlayer insulating film 1 is formed.
06 and the first capping layer 104 are etched (etched) to form a via 108 exposing a portion of the surface of the lower metal wiring 102, and then Ti or Ti is formed on the resultant structure.
/ TiN of about 800 by chemical vapor deposition (CVD)
A barrier metal layer (not shown) is formed by vapor deposition to a thickness of Å. Generally, when tungsten is deposited by a chemical vapor deposition (CVD) method to form a via plug, the reactive gas WF ₆ has a very good reactivity.
In some cases, aluminum (Al) or silicon (S
It may easily react with the underlayer material as in i) to form an undesired reaction product, thereby increasing the contact resistance or causing a failure. Therefore, in order to prevent this, a method of forming a barrier metal layer and then depositing tungsten to prevent the underlying layer from being directly exposed to WF ₆ gas is widely used. In addition, the barrier metal layer plays a role of increasing the adhesive strength between the tungsten plug and the aluminum (Al) wiring. When such a barrier metal layer is deposited by a sputtering method, the film itself has a slightly transparent structure.
The F ₆ gas can diffuse and react with silicon or aluminum (Al) of the underlayer to form an undesirable reaction product. Accordingly, the barrier metal layer is preferably deposited by a chemical vapor deposition (CVD) method.

After the formation of the barrier metal layer, a metal, for example, tungsten is deposited on the resultant structure by a chemical vapor deposition (CVD) method to a thickness enough to bury the via 108. I do. Next, a via plug 110 is formed inside the via 108 by etching the tungsten film until the surface of the interlayer insulating film 106 is exposed by a chemical physical polishing (CMP) method.

Alternatively, the via plug 110 may be formed up to the upper metal wiring layer in contact with an impurity-doped layer (not shown) formed on the semiconductor substrate.

FIG. 5 shows the step of forming the upper metal wiring 114. After forming the via plug 110 as described above,
An ohmic layer 112 is formed on the resultant structure by sputtering Ti to a thickness of about 150 °. Next, a metal such as aluminum (Al) is formed on the ohmic layer 112.
Is sputtered to a thickness of about 6000 ° to form the upper metal wiring 114. Next, a second capping layer 116 is formed on the upper metal interconnection 114 by sputtering TiN to a thickness of about 250 °. At this time, the second capping layer 116 may be formed by sputtering Ti with a thickness of about 100 ° and forming TiN thereon with a thickness of about 400 °.

Next, a photoresist layer is coated on the second capping layer 116 through a photographic process, and is exposed and developed to form a photoresist layer pattern 118 defining an upper metal wiring region.

FIG. 6 shows the stage of performing plasma-free ozone ashing. The photoresist film pattern 118
Is used as an etching mask to dry-etch the second capping layer 116, the upper metal wiring 114, and the ohmic layer 112 thereunder. Next, the photoresist film pattern 11
In order to remove 8, non-plasma ozone ashing is performed to oxidize the surface of the tungsten plug 110 buried in the via 108 exposed by misalignment with the upper metal wiring 114.

Reference numeral 120 denotes a surface oxide film of the plug, which is made of tungsten plug (1) by plasma-free ozone ashing.
10) represents an oxide film formed on the surface.

Preferably, in the plasma-free ozone ashing, the flow rate of ozone (O ₃ ) gas is 10,000 ± 500.
0sccm (standard cubic centimeter per minute)
And the gas flow rate of nitrogen (N ₂ ) is 500 ± 200 sc
cm and a temperature of 350 ± 50 ° C.

Next, the ashed photoresist film is stripped using a predetermined chemical solution, and then a cleaning process is performed.

Although the present invention has been described with reference to preferred embodiments, it is to be understood that the invention is not limited to these embodiments, and that various modifications can be made by those having ordinary skill in the art.

[0034]

As described above, according to the method for forming a highly reliable via of a semiconductor device according to the present invention, plasma-free ozone ashing is performed after patterning an upper metal wiring using a photoresist film pattern. Accordingly, the surface of the via plug embedding the via which is misaligned and exposed to the upper metal wiring is oxidized and the positive charge is absorbed. Therefore, the exposed via plug is not corroded by the electrochemical reaction, so that the reliability of the via can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a via forming method of a semiconductor device according to a conventional method.

FIG. 2 is a diagram showing electrochemical potential values of tungsten with respect to the pH index (pH) of a chemical solution.

FIG. 3 is a flowchart showing an embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a via forming method of the semiconductor device according to the embodiment.

FIG. 5 is a cross-sectional view for explaining a via forming method of the semiconductor device according to the embodiment.

FIG. 6 is a cross-sectional view for explaining a via forming method of the semiconductor device according to the embodiment.

[Explanation of symbols]

 12, 102: Lower metal wiring 14, 104: First capping layer 16, 106: Interlayer insulating film 18, 108: Via 20, 110: Tungsten plug 22, 112: Omic layer 24, 114 ... Upper metal wiring 26, 116 ... Second capping layer 118: photoresist film pattern

Continuing on the front page (72) Inventor Zheng Zhou Hak South Korea, Gyeonggi-do, Suwon-si, Cheonan-gu, Dongdae-dong Dongshin Apartment 209 Building 1214 No. Wing 804

Claims (7)

[Claims] 1. A method of manufacturing a semiconductor device in which an upper metal wiring layer and a lower conductive layer are connected by a metal plug embedded in a via, wherein a first upper portion of the metal plug is exposed and a second upper portion of the metal plug is exposed. Providing the upper metal wiring layer formed by covering the metal plug, and further oxidizing the first upper portion of the metal plug by plasma-free ozone ashing to prevent electrochemical corrosion. Device manufacturing method. 2. The method according to claim 1, wherein the plasma-free ozone ashing is performed at a temperature of 300 to 400 ° C. Forming a lower conductive layer on the semiconductor substrate; forming an interlayer insulating film on the lower conductive layer; and etching the interlayer film to expose the lower conductive layer. Forming a via in a via; filling the via with a metal plug; forming a metal wiring layer on the interlayer insulating film and the metal plug; forming a photoresist film pattern on the upper metal wiring layer After that, patterning the upper metal wiring layer,
Performing a non-plasma ozone ashing process on the photoresist film pattern. 4. The method according to claim 3, wherein the metal plug is made of tungsten. 5. The method according to claim 3, further comprising stripping the photoresist film pattern with a chemical solution.
A method for manufacturing a semiconductor device according to claim 4. 6. The method of manufacturing a semiconductor device according to claim 3, wherein the plasma-free ozone ashing is performed at a temperature of 300 to 400 ° C. 7. The non-plasma ozone ashing process oxidizes an exposed surface of the metal plug, and the oxidized layer prevents charges from being accumulated on the exposed surface of the metal plug. 7. The method for manufacturing a semiconductor device according to any one of items 1 to 6.