JP2000077672A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2000077672A
JP2000077672A JP10250133A JP25013398A JP2000077672A JP 2000077672 A JP2000077672 A JP 2000077672A JP 10250133 A JP10250133 A JP 10250133A JP 25013398 A JP25013398 A JP 25013398A JP 2000077672 A JP2000077672 A JP 2000077672A
Authority
JP
Japan
Prior art keywords
film
oxide film
heat treatment
substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10250133A
Other languages
Japanese (ja)
Other versions
JP3603611B2 (en
Inventor
Mitsutoshi Miyasaka
光敏 宮坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
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Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP25013398A priority Critical patent/JP3603611B2/en
Publication of JP2000077672A publication Critical patent/JP2000077672A/en
Application granted granted Critical
Publication of JP3603611B2 publication Critical patent/JP3603611B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PROBLEM TO BE SOLVED: To minimize the damage to a substrate carrying a semiconductor film and an oxide film caused by a plasma and, in addition, to repair the damage by performing a nitriding treatment on the substrate and performing a first heat treatment on the substrate in an oxidizing atmosphere, and then, a second heat treatment on the substrate. SOLUTION: After a silicon oxide film is formed, the film is subjected to a nitrogen plasma treatment. Then the substrate 101 on which the oxide film is formed is introduced to a parallel plate capacitively coupled plasma chemical vapor deposition(PECVD) device and irradiated with the light emitted from ammonia plasma. Thereafter, a first heat treatment is performed on the substrate 101 in an oxidizing atmosphere. After the first heat treatment, the oxide film is dried through a second heat treatment. Then a gate electrode 105 is formed of a metallic thin film, and source and drain areas 107 and a channel forming area 108 are formed in a self-aligning way against the gate electrode 105 by implanting impurity ions which become a donor or an acceptor. Thereafter, the manufacturing of a semiconductor device is completed by depositing an interlayer insulating film 109 and forming wiring 110.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は薄膜トランジスタ
(TFT)等に代表される半導体装置の製造方法に関す
る。更に詳しくは、本願発明は高性能で信頼性に富む半
導体装置を、600℃程度以下の比較的低温にて製造す
る方法に関する。
The present invention relates to a method for manufacturing a semiconductor device typified by a thin film transistor (TFT) and the like. More specifically, the present invention relates to a method for manufacturing a semiconductor device having high performance and high reliability at a relatively low temperature of about 600 ° C. or lower.

【0002】[0002]

【従来の技術】多結晶硅素薄膜トランジスタ(p−Si
TFT)に代表される半導体装置を汎用ガラス基板を
使用し得る600℃程度以下の低温にて製造する場合、
従来以下の如き製造方法が取られて居た。まずエキシマ
レーザー照射法などで多結晶硅素膜(p−Si膜)形成
した後、ゲート絶縁膜と成る酸化硅素膜を化学気相堆積
法(CVD法)や物理気相堆積法(PVD法)にて形成
する。次にタンタル等でゲート電極を作成して、金属
(ゲート電極)−酸化膜(ゲート絶縁膜)−半導体(多
結晶硅素膜)から成る電界効果トランジスタ(MOS−
FET)を構成する。次に層間絶縁膜を堆積し、コンタ
クトホールを開孔した後に金属薄膜にて配線を施す。必
要に応じて電気特性を改善する為に、最後に水素プラズ
マ処理を2時間程行い、半導体装置が完成する。
2. Description of the Related Art Polycrystalline silicon thin film transistors (p-Si
When manufacturing a semiconductor device typified by TFT) at a low temperature of about 600 ° C. or less, which can use a general-purpose glass substrate,
Conventionally, the following manufacturing method has been adopted. First, a polycrystalline silicon film (p-Si film) is formed by an excimer laser irradiation method or the like, and then a silicon oxide film serving as a gate insulating film is formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Formed. Next, a gate electrode is formed of tantalum or the like, and a field effect transistor (MOS) composed of a metal (gate electrode) -oxide film (gate insulating film) -semiconductor (polycrystalline silicon film) is formed.
FET). Next, an interlayer insulating film is deposited, a contact hole is opened, and wiring is formed using a metal thin film. In order to improve the electric characteristics as needed, a hydrogen plasma treatment is finally performed for about 2 hours to complete the semiconductor device.

【0003】[0003]

【発明が解決しようとする課題】しかしながら此等従来
の半導体装置の製造方法では半導体特性を改善する為に
水素プラズマ照射を施すと、その処理時間が余りにも長
い為に半導体膜や酸化硅素膜、更にはプラズマ処理装置
自身にもプラズマに依る損傷が入ったり、高価格なプラ
ズマ処理装置を何台も購入せねばならぬ等の多くの問題
を抱えて居た。斯くした事実に則し、従来の製造方法に
てp−Si TFT等の半導体装置を製造すると、製造
価格は高騰し、完成した半導体装置もその電気特性に優
れぬにのみならず、使用途上に経時劣化が生ずる等の信
頼性にも課題を有して居た。
However, in the conventional method of manufacturing a semiconductor device, if hydrogen plasma irradiation is performed to improve the semiconductor characteristics, the processing time is too long, so that the semiconductor film, silicon oxide film, Further, the plasma processing apparatus itself suffers from many problems such as damage due to plasma, and the necessity of purchasing many expensive plasma processing apparatuses. In accordance with such a fact, if a semiconductor device such as a p-Si TFT is manufactured by a conventional manufacturing method, the manufacturing cost rises, and the completed semiconductor device not only has poor electrical characteristics but also has a problem in use. There was also a problem in reliability such as deterioration over time.

【0004】そこで本発明は上述の諸事情を鑑み、その
目的とする所は600℃程度以下との低温工程で優良な
半導体装置を製造する方法を提供する事に有る。
The present invention has been made in view of the above circumstances, and has as its object to provide a method of manufacturing an excellent semiconductor device in a low-temperature process at about 600 ° C. or less.

【0005】[0005]

【課題を解決するための手段】本発明は基板上に設けら
れた絶縁性物質の上に形成された半導体膜と、この半導
体膜上に形成された酸化硅素に代表される絶縁膜の二者
を主たる構成要件として居る半導体装置の製造方法に関
し、少なくとも以下の五工程を以てその特徴と為す。即
ち基板上に設けられた絶縁性物質の上に半導体膜を形成
する第一工程と、気相堆積法にて酸化膜を此の半導体膜
上に堆積する第二工程と、此等半導体膜と酸化膜とを有
する基板に窒化処理を施す第三工程と、此の基板に酸化
性雰囲気下にて第一熱処理を施す第四工程と、更に此の
基板に対して第二熱処理を施す第五工程とで有る。
According to the present invention, there is provided a semiconductor film formed on an insulating material provided on a substrate and an insulating film typified by silicon oxide formed on the semiconductor film. The method for manufacturing a semiconductor device whose main component is described above is characterized by at least the following five steps. That is, a first step of forming a semiconductor film on an insulating material provided on a substrate, a second step of depositing an oxide film on the semiconductor film by a vapor deposition method, A third step of subjecting the substrate having an oxide film to a nitriding treatment, a fourth step of subjecting the substrate to a first heat treatment under an oxidizing atmosphere, and a fifth step of further subjecting the substrate to a second heat treatment. Process.

【0006】まず本発明は第一工程としてガラス基板や
半導体基板上に形成された三次元半導体装置の層間絶縁
膜等の縁性物質上に多結晶硅素(p−Si)に代表され
る半導体膜を形成する。この半導体膜は結晶状態に有っ
ても非晶質状態に有っても構わないが、多結晶状態に有
る時に本願発明は殊の外その効果を示す。此は本願発明
が半導体膜と絶縁膜との界面に存在する捕獲準位(界面
準位)を低減せしめると共に、結晶粒と結晶粒との間に
位置する捕獲準位(粒界準位)をも低減せしめるが故で
有る。言う迄もなく界面準位は結晶状態に拘わらず半導
体膜と絶縁膜との接合界面には必ず存在する。この界面
準位を低減させるから、本願発明は半導体膜の状態の如
何に拘わらず有効なので有る。一方、多結晶膜に対して
は此の効果に加え、粒界準位を減らすとの効果も認めら
れる。半導体膜は硅素(Si)や硅素ゲルマニウム(S
Ge1−x:0<x<1)等如何なる半導体物質で
有っても構わないが、簡便に良好なMOS界面を構成す
るとの視点からは、硅素単体や硅素をその主構成元素
(硅素原子構成比が80%程度以上)として居る半導体
物質が優れて居る。半導体膜は物理気相堆積法(PVD
法)や化学気相堆積法(CVD法)等の気相堆積法等で
形成される。PVD法にはスパッター法や蒸着法等が考
えられる。又CVD法には常圧化学気相堆積法(APC
VD法)や低圧化学気相堆積法(LPCVD法)、プラ
ズマ化学気相堆積法(PECVD法)等が使用され得
る。気相堆積法で形成された半導体膜は、堆積直後には
通常多結晶状態か非晶質状態に、又はこれらの混合状態
に有る。多結晶状態に有る薄膜は多結晶膜と称され、非
晶質状態や混合状態に有る薄膜は非晶質膜や混晶質膜と
其々称される。半導体装置の能動部(電界効果型トラン
ジスタのソース・ドレイン領域やチャンネル形成領域、
及びバイポーラ型トランジスタのエミッター・ベース・
コレクター領域)としては堆積直後に得られた多結晶膜
をその侭使用する事も可能で有る。此とは対照的に非晶
質膜や混晶質膜を結晶化したり、或いは多結晶膜を再結
晶化するなどして、新たな多結晶膜を得た後に、此等を
能動部として使用する事も可能で有る。結晶化や再結晶
化を行うにはレーザー照射や急速熱処理が用いられる。
First, in the present invention, as a first step, a semiconductor film typified by polycrystalline silicon (p-Si) is formed on an edge material such as an interlayer insulating film of a three-dimensional semiconductor device formed on a glass substrate or a semiconductor substrate. To form The semiconductor film may be in a crystalline state or an amorphous state, but when it is in a polycrystalline state, the present invention exhibits its effects. This is because the present invention reduces the trap level (interface level) existing at the interface between the semiconductor film and the insulating film, and reduces the trap level (grain boundary level) located between crystal grains. Is also reduced. Needless to say, the interface state always exists at the bonding interface between the semiconductor film and the insulating film regardless of the crystal state. Since this interface state is reduced, the present invention is effective regardless of the state of the semiconductor film. On the other hand, for a polycrystalline film, in addition to this effect, an effect of reducing the grain boundary level is also recognized. The semiconductor film is made of silicon (Si) or silicon germanium (S
i x Ge 1-x: 0 <x <1) or the like but may be there in any semiconductor material, conveniently good from the perspective of configuring the MOS interface, the main constituent element of silicon simple substance and silicon ( Semiconductor materials having a silicon atom composition ratio of about 80% or more) are excellent. Semiconductor films are deposited by physical vapor deposition (PVD).
) Or a vapor phase deposition method such as a chemical vapor deposition method (CVD method). As the PVD method, a sputtering method, an evaporation method, or the like can be considered. Atmospheric pressure chemical vapor deposition (APC)
VD), low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), and the like. A semiconductor film formed by a vapor deposition method is usually in a polycrystalline state, an amorphous state, or a mixed state thereof immediately after deposition. A thin film in a polycrystalline state is called a polycrystalline film, and a thin film in an amorphous state or a mixed state is called an amorphous film or a mixed crystalline film, respectively. Active part of semiconductor device (source / drain region and channel formation region of field effect transistor,
Emitter and base of bipolar transistors
As the collector region, the polycrystalline film obtained immediately after the deposition can be used as it is. In contrast to this, a new polycrystalline film is obtained by crystallizing an amorphous film or mixed crystal film or recrystallizing a polycrystalline film, and then using this as an active part. It is also possible to do. Laser irradiation or rapid heat treatment is used for crystallization or recrystallization.

【0007】次に第二工程として気相堆積法にて酸化膜
を半導体膜上に堆積する。酸化膜の堆積は高くとも60
0℃程度以下の温度で、通常は400℃程度以下の温度
で行われる。此は本願が対象として居る半導体装置を汎
用ガラス基板やプラスチック基板等、耐熱性の乏しい基
板上に製造する事を前提として居るからで有る。此の酸
化膜をMOS−FETのゲート絶縁膜として利用する。
半導体膜と絶縁膜との良好な界面を簡便に得るには、酸
化膜の主構成物質は酸化硅素(SiO:0<x≦2)
で有る事が望ましい。酸化膜は物理気相堆積法(PVD
法)や化学気相堆積法(CVD法)等の気相堆積法等で
形成される。PVD法にはスパッター法や蒸着法等が考
えられる。CVD法には常圧化学気相堆積法(APCV
D法)や低圧化学気相堆積法(LPCVD法)、プラズ
マ化学気相堆積法(PECVD法)等が使用され得る。
斯様にして得られた酸化膜は、1100℃程度以上の温
度で形成される熱酸化膜に比べて酸化膜中に酸化膜捕獲
準位や固定電荷を多量に含み、更に界面準位も遥かに高
いのが普通で有る。それ故、本願発明では以下の三工程
(第三、第四、第五工程)を以て、酸化膜と界面及び結
晶粒界の改質を図る訳で有る。
Next, as a second step, an oxide film is deposited on the semiconductor film by a vapor deposition method. Oxide deposition at most 60
It is performed at a temperature of about 0 ° C. or less, usually at a temperature of about 400 ° C. or less. This is because it is assumed that the semiconductor device to which the present invention is applied is manufactured on a substrate having poor heat resistance, such as a general-purpose glass substrate or a plastic substrate. This oxide film is used as a gate insulating film of a MOS-FET.
In order to easily obtain a good interface between the semiconductor film and the insulating film, the main constituent material of the oxide film is silicon oxide (SiO x : 0 <x ≦ 2).
It is desirable that it is. Oxide film is deposited by physical vapor deposition (PVD).
) Or a vapor phase deposition method such as a chemical vapor deposition method (CVD method). As the PVD method, a sputtering method, an evaporation method, or the like can be considered. Atmospheric pressure chemical vapor deposition (APCV)
D), low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), and the like.
The oxide film thus obtained contains a larger amount of oxide film trapping levels and fixed charges in the oxide film than the thermal oxide film formed at a temperature of about 1100 ° C. or higher, and further has a much higher interface state. It is usually high. Therefore, in the present invention, the following three steps (third, fourth, and fifth steps) are performed to reform the oxide film, the interface, and the crystal grain boundaries.

【0008】第二工程が終了した後に、第三工程として
半導体膜や酸化硅素膜が形成された基板に水素化を含む
窒化処理を施す。此は半導体膜や半導体膜と酸化硅素膜
との界面が有する不対結合対に水素(−H)やアミノ基
(−NH)、イミノ基(=NH)、窒素(≡N)等を
結合させ、禁制帯中の中心部付近(真性フェルミレベル
近傍)に於ける捕獲準位(ディープ・ステイツ)を減少
させるので有る。同時に酸化膜中に存在する不対結合対
も此等の官能基で終端し、酸化膜固定電荷を減少させ
る。ディープ・ステイツの主因は半導体膜の界面や粒界
に存在する不対結合対で有る。此等は窒化処理に依り容
易に不活性とされ、不活性化されれば捕獲準位は減少す
る。又、酸化膜中の固定電荷はフラットバンド電位に変
動をもたらしたり、酸化膜への電荷の注入を容易として
半導体装置の動作信頼性を低下させる。従って第三工程
の窒化処理を行う事で半導体装置のフラットバンド電位
を理想値に近づけ、ディープ・ステイツを減少させ、更
に半導体装置の信頼性を増すので有る。最も簡単に窒化
処理を行うには基板にアンモニア(NH)プラズマや
窒素(N)プラズマを照射する事で有る。アンモニア
プラズマ照射では先の水素(−H)やアミノ基(−NH
)、イミノ基(=NH)等を結合させる化学反応が容
易に進み、不対電子対の終端は効率的に行われる。しか
もアンモニアプラズマならば大面積化が容易なrf波
(13.56MHzや此等の高調波)を利用できる。一
方、マイクロ波(2.45GHz等)を用いれば窒素プ
ラズマによる窒化が窮めて容易となり、プラズマ処理装
置の安全性や耐久性が増す事と成る。窒化処理は基板温
度が低過ぎる(100℃程度未満)と反応が進行せず、
基板温度が高過ぎる(450℃程度以上)と水素離脱等
の逆反応の進行が速く成るので、100℃程度から45
0℃程度の間の基板温度で行う。理想的には250℃程
度から400℃程度の間の温度で有る。此の窒化処理に
依り界面には0.3nm程度から5nm程度の極薄い硅
素の窒化酸化膜(SiON)が形成される事になる。此はゲー
ト絶縁膜中への半導体膜からの電荷注入が起こりにくく
なり、半導体装置の動作信頼性が増す事を意味する。
After the second step is completed, as a third step, the substrate on which the semiconductor film and the silicon oxide film are formed is subjected to a nitriding treatment including hydrogenation. In this method, hydrogen (—H), amino group (—NH 2 ), imino group (= NH), nitrogen (≡N), etc. are bonded to an unpaired bond pair at the interface between the semiconductor film and the semiconductor film and the silicon oxide film. This reduces the trap states (deep states) near the center of the forbidden zone (near the intrinsic Fermi level). At the same time, unpaired bonding pairs existing in the oxide film are also terminated with these functional groups, thereby reducing the oxide film fixed charge. The main cause of deep states is an unpaired pair existing at the interface or grain boundary of the semiconductor film. These are easily made inert by the nitriding treatment, and if they are inactivated, the trap level decreases. In addition, the fixed charge in the oxide film causes a change in the flat band potential and facilitates injection of the charge into the oxide film, thereby lowering the operation reliability of the semiconductor device. Therefore, by performing the nitriding treatment in the third step, the flat band potential of the semiconductor device is made closer to the ideal value, the deep states are reduced, and the reliability of the semiconductor device is further increased. The easiest way to perform the nitriding treatment is to irradiate the substrate with ammonia (NH 3 ) plasma or nitrogen (N 2 ) plasma. In ammonia plasma irradiation, hydrogen (-H) or amino group (-NH)
2 ) A chemical reaction for bonding an imino group (= NH) or the like proceeds easily, and the unpaired electron pair is efficiently terminated. In addition, in the case of ammonia plasma, rf waves (13.56 MHz or higher harmonics thereof) that can be easily enlarged can be used. On the other hand, if microwaves (2.45 GHz or the like) are used, nitriding by nitrogen plasma becomes extremely difficult and the safety and durability of the plasma processing apparatus are increased. In the nitriding treatment, if the substrate temperature is too low (less than about 100 ° C.), the reaction does not proceed,
If the substrate temperature is too high (about 450 ° C. or more), the progress of the reverse reaction such as hydrogen elimination is accelerated.
This is performed at a substrate temperature of about 0 ° C. Ideally, the temperature is between about 250 ° C. and about 400 ° C. By this nitriding treatment, an extremely thin silicon nitride oxide film (SiON) of about 0.3 nm to about 5 nm is formed at the interface. This means that charge injection from the semiconductor film into the gate insulating film is less likely to occur and the operation reliability of the semiconductor device is increased.

【0009】従来の水素化処理は2時間から6時間も行
われていた。此に対して本願発明の第三工程に於ける水
素化を含む窒化処理時間は10秒間程度から10分間程
度で有る。此は従来の方法ではゲート電極(厚さ500
nm程度以上)や層間絶縁膜(厚さ500nm程度以
上)、金属配線(厚さ500nm程度以上)等が出来上
がった後に水素化処理を行って居た為で有る。水素化を
効率的に行うにはプラズマ等で水素ラジカルを生成する
必要が有るが、此等は化学的に活性で反応が速い為、そ
の寿命が短く、ゲート電極や層間絶縁膜、金属配線等が
存在すると、ゲート絶縁膜や能動層半導体膜迄はなかな
か達しない。それが故、従来は水素プラズマ処理時間を
長くせざるを得ず、斯くして水素化処理と同時に半導体
装置には多くのプラズマ損傷が入り、プラズマ処理装置
も自身が発生するプラズマにその寿命を短くして居たの
で有った。此に対して本願発明ではゲート絶縁膜が形成
された直後に前述の官能基群を結合させる処理を施す。
ゲート絶縁膜も層間絶縁膜も金属配線も存在せぬ状況下
にて直に此等の水素化やアミノ化、イミノ化、或いは窒
化処理を行うので有る。然も本願発明の半導体装置では
ゲート絶縁膜が5nm程度から120nm程度と薄い
為、水素や窒素、アンモニア、アミノ基、イミノ基等の
ラジカルは容易に半導体膜迄達する。これが本願発明で
は窒化処理時間を従来の水素化処理に比べて10分の1
から100分の1へと大幅に短縮し得た理由で有る。窒
化処理にアンモニアプラズマ照射を利用すると、プラズ
マ照射時間の短縮に伴い、プラズマ損傷も10分の1か
ら100分の1へと低減され、プラズマ処理装置の寿命
内での処理枚数も10倍から100倍へと増加するので
有る。第三工程の処理時間が10秒程度未満だと水素化
や窒化の効果は現れず、10分程度以上だと酸化膜や半
導体膜にプラズマ損傷が第四工程以降で修繕出来ぬ程入
る恐れが有る。理想的には30秒程度から120秒程度
で有る。
[0009] Conventional hydrogenation treatment has been performed for 2 to 6 hours. On the other hand, the nitriding time including hydrogenation in the third step of the present invention is about 10 seconds to about 10 minutes. This is a conventional method using a gate electrode (thickness 500).
This is because the hydrogenation treatment was performed after the formation of the interlayer insulating film (about 500 nm or more), the metal wiring (about 500 nm or more), and the like. In order to perform hydrogenation efficiently, it is necessary to generate hydrogen radicals by plasma or the like, but these are chemically active and react quickly, so their life is short, and gate electrodes, interlayer insulating films, metal wiring, etc. Does not readily reach the gate insulating film or the active layer semiconductor film. Therefore, conventionally, the hydrogen plasma processing time has to be extended, and thus, a large amount of plasma damage is caused to the semiconductor device at the same time as the hydrogenation processing, and the plasma processing apparatus also extends its life to the plasma generated by itself. It was so short. On the other hand, in the present invention, immediately after the gate insulating film is formed, the above-described treatment for bonding the functional groups is performed.
The hydrogenation, amination, iminoization, or nitridation treatment is performed directly in a state where no gate insulating film, interlayer insulating film, and metal wiring exist. Of course, in the semiconductor device of the present invention, since the gate insulating film is as thin as about 5 nm to about 120 nm, radicals such as hydrogen, nitrogen, ammonia, amino groups, and imino groups easily reach the semiconductor film. This is because the nitriding time of the present invention is one tenth of that of the conventional hydrogenation.
This is the reason why it could be greatly reduced from 1 to 100 times. When the ammonia plasma irradiation is used for the nitriding treatment, the plasma damage is reduced from 1/10 to 1/100 as the plasma irradiation time is shortened, and the number of processed wafers within the life of the plasma processing apparatus is increased from 10 times to 100 times. Yes, because it doubles. If the processing time of the third step is less than about 10 seconds, the effect of hydrogenation or nitridation does not appear, and if the processing time is about 10 minutes or more, plasma damage to the oxide film or semiconductor film may not be repaired after the fourth step. Yes. Ideally, it is about 30 seconds to about 120 seconds.

【0010】プラズマ損傷とはプラズマから発生する高
エネルギー光子(紫外線)やイオンが酸化膜や半導体膜
に照射され、酸化膜や半導体膜と言った物質の化学結合
を切断する事に由来する。此の結果、半導体膜や酸化膜
の内部に不対結合対や固定電荷が生ずるので有る。此の
プラズマ損傷は特に酸化硅素膜に対して顕著と成る。と
言うのは、酸化硅素膜がゲート絶縁膜としてプラズマに
露出して居る為、イオン照射を直接被り、更に酸化膜が
非晶質でSi−O−Siの結合角や原子間距離に大きな
分布を有して居るからで有る。本願発明では第三工程に
於けるプラズマ照射時間が長くとも10分程度未満と短
いものの、それでも僅かなプラズマ損傷が酸化膜や界面
に入って居る。又、酸化膜が600℃程度以下との低温
で形成されて居る為、低温形成酸化膜に固有な固定電荷
や捕獲準位を良質な熱酸化膜に比べて多量に有して居
る。更には前述の窒化処理に伴い、窒素原子に由来する
不対結合対も絶縁膜中や界面、多結晶性半導体膜の粒界
に現れる。そこで第四工程では低品質な低温形成酸化膜
やプラズマ損傷、窒化処理に由来する欠陥等を第一熱処
理に依り改質するので有る。
[0010] Plasma damage is caused by irradiating high-energy photons (ultraviolet rays) or ions generated from plasma to an oxide film or a semiconductor film to cut a chemical bond of a substance such as an oxide film or a semiconductor film. As a result, an unpaired pair or a fixed charge is generated inside the semiconductor film or the oxide film. This plasma damage is particularly remarkable for a silicon oxide film. This is because the silicon oxide film is exposed to the plasma as a gate insulating film, so that it is directly exposed to ion irradiation, and the oxide film is amorphous and has a large distribution in the bond angle and interatomic distance of Si-O-Si. It is because it has. In the present invention, although the plasma irradiation time in the third step is as short as less than about 10 minutes at the longest, slight plasma damage still enters the oxide film and the interface. Also, since the oxide film is formed at a low temperature of about 600 ° C. or less, the fixed oxide and the trapping level inherent in the low-temperature formed oxide film are more abundant than a high-quality thermal oxide film. Further, with the above-described nitriding treatment, unpaired bond pairs derived from nitrogen atoms also appear in the insulating film, at the interface, and at the grain boundaries of the polycrystalline semiconductor film. Therefore, in the fourth step, low-quality low-temperature-formed oxide films, plasma damage, defects derived from nitriding, and the like are modified by the first heat treatment.

【0011】第四工程では酸化膜に酸化性雰囲気下に
て、200℃程度から450℃程度の温度で第一熱処理
を施す。酸化性雰囲気は塩酸(HCl)や硝酸(HNO
)、弗酸(HF)等の酸や水(HO)と云った酸化
膜の結合を化学的に切断し得る物質と、酸素(O)や
亜酸化窒素(N0)、二酸化炭素(CO)と云った
酸素含有気体とを少なくとも含んだ気体から構成され
る。酸化膜の結合を化学的に切断し得る物質は同時に半
導体膜や窒化膜の酸化促進物質でも有る。此の雰囲気は
酸化膜の結合を化学的に切断し得る物質と酸素含有気体
と不活性気体から成って居ても無論良い。最も簡単な一
例は水蒸気を含有した空気で有る。此の場合、水蒸気が
酸化膜の結合を切断し得る物質で有り、空気中の酸素が
酸素含有気体で有る。前者の酸化膜の結合を切断し得る
物質は、酸化硅素膜等の酸化膜を構成する元素(硅素や
酸素)間の歪んだ結合や弱い結合を優先的に切断する性
質を有して居る。此に対して後者は酸素欠損を生じて居
る酸化膜や界面に酸素を供給し、不完全な酸化膜(例え
ばSiO:0<x<2)や酸素欠損の多い界面を完全
な酸化膜(例えばSiO)や酸素欠損の少ない界面へ
と改善する。又、不対結合対を有する窒素原子を酸化さ
せ、窒化酸化膜を形成する。此の第一熱処理に依り酸化
膜を構成する歪んだ結合や弱い結合は切断と再結合を繰
り返され、最終的に酸化膜は正常で強い結合から成るS
i−O−Si結合の編み目構想を取るに到る。又、単純
な窒化処理を施しただけの絶縁膜では固定電化や酸化膜
捕獲準位が多くて実用的でない物を、此の第一熱処理に
依り此等の電荷や準位を大幅に低減して窒化酸化膜の膜
質を著しく改善するので有る。斯様にして酸化膜と窒化
酸化膜とから成る絶縁膜中の捕獲準位や固定電荷、界面
準位が大幅に低減されるので有る。此の事は半導体装置
の立場からすると、フラットバンド電位を理想値(ゲー
ト電極を構成する金属の仕事関数と半導体の仕事関数の
差)に近づけ、閾値電圧を小さくし、更に半導体装置の
信頼性を増して居るを意味して居る。第四工程の処理温
度はそれが高い程、その処理時間は短くて済む。常識的
な処理時間(長くとも24時間程度)で処理を完了させ
るには最低でも200℃程度の温度が必要と成る。一
方、本願発明では第三工程で半導体膜や酸化膜が有する
欠陥を水素や窒素等にて補修して居る。第四工程の熱処
理温度が高過ぎると結晶性半導体膜や酸化膜の欠陥を終
端して居る水素やアミノ基が離脱し、欠陥が増す恐れが
有る。水素やアミノ基の離脱を防ぎ多結晶性半導体膜や
酸化膜の欠陥を最少に止める為には、第四工程の処理温
度は400℃程度以下が好ましい。
In a fourth step, the oxide film is subjected to a first heat treatment at a temperature of about 200 ° C. to 450 ° C. in an oxidizing atmosphere. The oxidizing atmosphere is hydrochloric acid (HCl) or nitric acid (HNO
3 ) an acid such as hydrofluoric acid (HF) or water (H 2 O) that can chemically break the bond of the oxide film, oxygen (O 2 ), nitrous oxide (N 20 ), It is composed of a gas containing at least an oxygen-containing gas such as carbon dioxide (CO 2 ). The substance capable of chemically breaking the bond of the oxide film is also an oxidation promoting substance of the semiconductor film and the nitride film. Of course, this atmosphere may be made of a substance capable of chemically breaking the bond of the oxide film, an oxygen-containing gas, and an inert gas. One of the simplest examples is air with water vapor. In this case, water vapor is a substance capable of breaking the bond of the oxide film, and oxygen in the air is an oxygen-containing gas. The former substance capable of breaking a bond of an oxide film has a property of preferentially breaking a distorted bond or a weak bond between elements (silicon and oxygen) constituting an oxide film such as a silicon oxide film. On the other hand, the latter supplies oxygen to an oxide film or an interface having an oxygen deficiency, and forms an incomplete oxide film (for example, SiO x : 0 <x <2) or an interface having many oxygen deficiencies to a complete oxide film ( For example, it is improved to an interface having few SiO 2 ) or oxygen vacancies. Further, a nitrogen atom having an unpaired bond pair is oxidized to form a nitrided oxide film. Due to this first heat treatment, the distorted bonds and weak bonds constituting the oxide film are repeatedly cut and recombined, and finally the oxide film has a normal and strong bond composed of S
The idea of the stitch of the i-O-Si bond is taken. In addition, in the case of an insulating film simply subjected to a simple nitridation treatment, those which are impractical due to a large number of fixed electrification and oxide film trapping levels are greatly reduced by the first heat treatment. This significantly improves the quality of the nitrided oxide film. Thus, trap levels, fixed charges, and interface levels in the insulating film composed of the oxide film and the nitrided oxide film are significantly reduced. From the standpoint of a semiconductor device, this implies that the flat band potential approaches the ideal value (the difference between the work function of the metal forming the gate electrode and the work function of the semiconductor), reduces the threshold voltage, and further improves the reliability of the semiconductor device. It means that we are increasing. The higher the processing temperature of the fourth step, the shorter the processing time. A temperature of at least about 200 ° C. is required to complete the processing in a common sense processing time (at most about 24 hours). On the other hand, in the present invention, in the third step, defects in the semiconductor film and the oxide film are repaired with hydrogen, nitrogen or the like. If the temperature of the heat treatment in the fourth step is too high, hydrogen and amino groups terminating the defects in the crystalline semiconductor film and the oxide film may be released, and the number of defects may increase. In order to prevent elimination of hydrogen and amino groups and to minimize defects in the polycrystalline semiconductor film and the oxide film, the processing temperature in the fourth step is preferably about 400 ° C. or less.

【0012】第四工程終了後、第五工程として第二熱処
理を非酸化性雰囲気下にて行う。非酸化性雰囲気として
は窒素(N)やアルゴン(Ar)等の不活性雰囲気下
や、此等不活性雰囲気中に水素を含有した雰囲気、或い
は水素単体から成る雰囲気下にて行われる。第五工程の
第二熱処理では第一熱処理の最中に酸化膜中に拡散した
酸や水等の物質を取り除く。此等の物質が酸化膜中に残
存すると潜在的な酸化膜準位や界面準位と化し、半導体
装置の信頼性を低下させる事と成る。従って第五工程の
第二熱処理を行う事で半導体装置の信頼性は著しく増大
する事に成る。酸化膜中に拡散した酸や水を除去するに
は、酸や水を含まぬ雰囲気下で熱処理を行えば、其の効
果は認められる。但し酸素を含む等の酸化性雰囲気下に
てこの第二熱処理を行うと、酸化の進行に伴い新たに不
完全な界面が形成されて仕舞い、界面準位の低減効果は
弱まる事に成る。それ故、第二熱処理は不活性雰囲気下
乃至は弱還元性雰囲気下にて行われる。圧力は1Torr程
度未満の低圧が好ましい。斯うすると界面準位が低い侭
に保たれ、優良な半導体装置が得られるので有る。界面
準位を更に低減するには第二熱処理を水素含有雰囲気下
にて行う事が好ましい。この場合、水素単体の雰囲気下
で行っても良いが、安全性を考慮すると水素を窒素やア
ルゴンと云った不活性気体で、濃度が爆発下限界以下と
成る4%程度未満に希釈して熱処理を行う事が望まし
い。第五工程の熱処理温度は第四工程の熱処理温度と略
同じで有るか、或いは第三工程の熱処理温度よりも高く
設定する。此は酸化膜中から不要な物質を早急且つ効果
的に除去し、更に酸化膜の編み目構造をより改善するに
は、第二熱処理の温度は高い方が好ましいからで有る。
そうした意味では此の第五工程の熱処理温度が第二工程
以降、半導体装置が完成する迄の全工程中の最高温度で
有る事が最も好ましい。第四工程や第五工程の温度はそ
れが高い程、酸化膜や界面の改質効果やプラズマ損傷の
修繕効果は大きいのだが、高温処理は取りも直さず半導
体膜中の不対結合対を終端して居る水素等の官能基の離
脱を促し、結果として半導体のディープ・ステイツを増
大させる事に成る。先にも述べた様に本願発明では第五
工程の熱処理温度が第二工程以降で半導体装置が完成す
る迄の最高温度と成って居る。従って第五工程で此等の
基の離脱が生じなければ、以降半導体装置から水素やア
ミノ基等が熱的に脱離される事はない。第三工程で不対
結合対を終端した水素等が半導体装置完成迄に離脱させ
ない為には、第五工程の基板温度を水素離脱の生じない
400℃程度以下とする事が好ましい。第一熱処理の温
度と第二熱処理の温度の関係は概ね第二熱処理温度が第
一熱処理温度よりも25℃程度から75℃程度高い事が
望ましい。例えば第一熱処理を300℃程度から350
℃程度で行い、第二熱処理を350℃程度から400℃
程度で行うのが理想と言えよう。此の温度関係ならば熱
処理炉の温度変動を考慮しても、第一熱処理の酸化膜編
み目構造補修効果も第二熱処理の不要物質除去効果も確
実に達成出来、且つ半導体膜からの水素離脱も最小限に
押さえる事が可能だからで有る。
After the fourth step, a second heat treatment is performed in a non-oxidizing atmosphere as a fifth step. The non-oxidizing atmosphere is performed under an inert atmosphere such as nitrogen (N 2 ) or argon (Ar), an atmosphere containing hydrogen in the inert atmosphere, or an atmosphere consisting of hydrogen alone. In the second heat treatment of the fifth step, substances such as acid and water diffused into the oxide film during the first heat treatment are removed. When these substances remain in the oxide film, they become potential oxide film levels or interface states, which lowers the reliability of the semiconductor device. Therefore, performing the second heat treatment in the fifth step significantly increases the reliability of the semiconductor device. In order to remove the acid and water diffused in the oxide film, the effect can be recognized by performing a heat treatment in an atmosphere containing no acid or water. However, if this second heat treatment is performed in an oxidizing atmosphere containing oxygen or the like, a new imperfect interface is formed with the progress of oxidation, and the second heat treatment is performed, and the effect of reducing the interface state is weakened. Therefore, the second heat treatment is performed in an inert atmosphere or a weak reducing atmosphere. The pressure is preferably as low as less than about 1 Torr. In this case, the interface state is kept low, and an excellent semiconductor device can be obtained. In order to further reduce the interface state, the second heat treatment is preferably performed in a hydrogen-containing atmosphere. In this case, the heat treatment may be performed in an atmosphere of hydrogen alone, but in consideration of safety, hydrogen is diluted with an inert gas such as nitrogen or argon to a concentration less than about 4%, which is lower than the lower explosion limit, and heat treated. It is desirable to do. The heat treatment temperature in the fifth step is substantially the same as the heat treatment temperature in the fourth step, or is set higher than the heat treatment temperature in the third step. This is because the temperature of the second heat treatment is preferably higher in order to quickly and effectively remove unnecessary substances from the oxide film and to further improve the stitch structure of the oxide film.
In this sense, it is most preferable that the heat treatment temperature in the fifth step be the highest temperature in all the steps after the second step until the semiconductor device is completed. The higher the temperature in the fourth and fifth steps, the greater the effect of reforming the oxide film and interface and the effect of repairing plasma damage.However, high-temperature processing does not repair the unpaired pair in the semiconductor film. It promotes the elimination of the terminating functional group such as hydrogen, and as a result, increases the deep state of the semiconductor. As described above, in the present invention, the heat treatment temperature in the fifth step is the maximum temperature until the semiconductor device is completed after the second step. Therefore, unless these groups are eliminated in the fifth step, hydrogen, amino groups, and the like are not thermally eliminated from the semiconductor device thereafter. In order to prevent hydrogen or the like terminating the dangling bond pair from being released in the third step by the time the semiconductor device is completed, it is preferable to set the substrate temperature in the fifth step to about 400 ° C. or lower where hydrogen desorption does not occur. The relationship between the temperature of the first heat treatment and the temperature of the second heat treatment is preferably that the second heat treatment temperature is higher than the first heat treatment temperature by about 25 ° C. to about 75 ° C. For example, the first heat treatment is performed from about 300 ° C. to 350
℃, the second heat treatment from about 350 ℃ to 400 ℃
It would be ideal to do it on the order. With this temperature relationship, the effect of repairing the knitted structure of the oxide film in the first heat treatment and the effect of removing unnecessary substances in the second heat treatment can be reliably achieved even if the temperature fluctuation of the heat treatment furnace is taken into consideration, and the desorption of hydrogen from the semiconductor film is also reduced. This is because it can be kept to a minimum.

【0013】結局、半導体特性の視点より第三乃至第五
工程の効果を論ずると、第三工程でフラットバンド電位
を理想値に近づけ、酸化膜固定電荷を減少させると共に
半導体膜や界面に於けるディープ・ステイツを減少さ
せ、第四工程でプラズマ損傷や絶縁膜中の欠陥を修繕す
る事で絶縁膜中の捕獲準位や固定電荷、界面捕獲準位を
低減し、第五工程でゲート絶縁膜の漏れ電流や絶縁膜内
捕獲準位の低減と云った半導体装置の信頼性を増して居
る事に成る。捕獲準位(テール・ステイツやディープ・
ステイツ)が低減されると、電気伝導に寄与する荷電担
体数が増加するにのみならず、捕獲電荷に依る荷電担体
の散乱も減るので移動度も大きく成る。又、サブスレー
シュホールド・スイングや閾値電圧が小さくなり、急峻
なスイッチ性能を示す良好な半導体装置が得られる事と
成る。
After all, the effects of the third to fifth steps are discussed from the viewpoint of the semiconductor characteristics. In the third step, the flat band potential is brought close to an ideal value, the oxide film fixed charge is reduced, and the semiconductor film and the interface are reduced. In the fourth step, trap levels, fixed charges, and interface trap levels in the insulating film are reduced by reducing deep states and repairing plasma damage and defects in the insulating film in the fourth step. This leads to an increase in the reliability of the semiconductor device, such as a reduction in leakage current and trap levels in the insulating film. Capture levels (tail states and deep
When the number of states is reduced, not only the number of charge carriers contributing to electric conduction increases, but also the scattering of the charge carriers due to trapped charges is reduced, so that the mobility is increased. In addition, the sub-threshold swing and the threshold voltage are reduced, and a good semiconductor device showing a steep switching performance can be obtained.

【0014】尚、第二工程の酸化膜形成と第三工程の窒
化処理は、窒化や水素化を効率的に短時間で行う為に、
連続して行われなければ成らないが、第三工程と第四工
程の間乃至第四工程と第五工程の間は必ずしも連続で有
る必要は無い。例えば第四工程と第五工程の間にゲート
電極を形成すると言った他工程が入っても良い。但し、
第四工程で酸化膜の結合を切断し得る物質や酸素含有気
体の酸化膜中への拡散を速くしたり、第五工程で此等の
物質をゲート絶縁膜中から迅速に除去するとの立場から
は、矢張り此等の工程も連続で有る事が望ましい。
The formation of the oxide film in the second step and the nitridation in the third step are performed in order to efficiently perform nitriding and hydrogenation in a short time.
Although it must be performed continuously, it is not always necessary to be continuous between the third step and the fourth step or between the fourth step and the fifth step. For example, another step of forming a gate electrode between the fourth step and the fifth step may be included. However,
From the standpoint of speeding up the diffusion of the substance capable of breaking the bond of the oxide film or the oxygen-containing gas into the oxide film in the fourth step, or quickly removing these substances from the gate insulating film in the fifth step It is desirable that these steps be continuous.

【0015】[0015]

【発明の実施の形態】(実施例1)図1(a)〜(d)
はMOS型電界効果トランジスタを形成する薄膜半導体
装置の製造工程を断面で示した図で有る。本実施例1で
は基板101として歪点が650℃程度の汎用無アルカ
リガラスを用いた。まず基板101上にECR−PEC
VD法で酸化硅素膜を200nm程度堆積し、下地保護
膜102とした。酸化硅素膜のECR−PECVD法で
の堆積条件は以下の通りで有る。
(Embodiment 1) FIGS. 1 (a) to 1 (d)
FIG. 2 is a cross-sectional view showing a manufacturing process of a thin film semiconductor device for forming a MOS field effect transistor. In the first embodiment, a general-purpose non-alkali glass having a strain point of about 650 ° C. was used as the substrate 101. First, ECR-PEC is placed on the substrate 101.
A silicon oxide film was deposited to a thickness of about 200 nm by the VD method to form a base protective film 102. The conditions for depositing the silicon oxide film by the ECR-PECVD method are as follows.

【0016】 モノシラン(SiH)流量・・・60sccm 酸素(O)流量・・・100sccm 圧力・・・2.40mTorr マイクロ波(2.45GHz)出力・・・2250W 印可磁場・・・875Gauss 基板温度・・・100℃ 成膜時間・・・40秒 此の下地保護膜上に半導体膜として真性非晶質硅素膜を
LPCVD法にて50nm程度の膜厚に堆積した。LP
CVD装置はホット・ウォール型で容積が184.5l
で、基板挿入後の反応総面積は約44000cmで有
る。堆積温度は425℃で原料ガスとして純度99.9
9%以上のジシラン(Si)を用い、200sc
cm反応炉に供給した。堆積圧力は凡そ1.1Torr
で有り、此の条件下で硅素膜の堆積速度は0.77nm
/minで有った。斯様にして得られた非晶質半導体膜
にクリプトン弗素(KrF)エキシマレーザーを照射し
て半導体膜の結晶化を進めた。照射レーザーエネルギー
密度は245mJ・cm−2で、半導体膜が膜厚方向全
体に渡り完全溶融して微結晶化が生ずるエネルギー密度
よりも15mJ・cm−2低いエネルギー密度で有っ
た。こうして結晶性半導体膜(多結晶硅素膜)を形成し
た(第一工程)後、この結晶性半導体膜を島状に加工し
て、後に半導体装置の能動層と成る半導体膜の島103
を形成した。(図1−a) 次にパターニング加工された半導体膜の島103を被う
様に酸化硅素膜104をECR−PECVD法にて形成
(第二工程)した。此の酸化硅素膜は半導体装置のゲー
ト絶縁膜として機能する。ゲート絶縁膜と成る酸化硅素
膜堆積条件は堆積時間が24秒と短縮された事を除い
て、下地保護膜の酸化硅素膜の堆積条件と同一で有る。
但し、酸化硅素膜堆積の直前にはECR−PECVD装
置内で基板に酸素プラズマを照射して、半導体の表面に
低温プラズマ酸化膜を形成した。プラズマ酸化条件は次
の通りで有る。
Monosilane (SiH 4 ) flow rate: 60 sccm Oxygen (O 2 ) flow rate: 100 sccm Pressure: 2.40 mTorr Microwave (2.45 GHz) output: 2250 W Applied magnetic field: 875 Gauss Substrate temperature ... 100 ° C. Film formation time... 40 seconds An intrinsic amorphous silicon film was deposited as a semiconductor film to a thickness of about 50 nm on the underlying protective film by LPCVD. LP
The CVD equipment is a hot wall type with a volume of 184.5 l
The total reaction area after inserting the substrate is about 44000 cm 2 . The deposition temperature is 425 ° C. and the purity is 99.9 as a source gas.
200 sc using disilane (Si 2 H 6 ) of 9% or more
cm reactor. Deposition pressure is about 1.1 Torr
Under these conditions, the deposition rate of the silicon film is 0.77 nm.
/ Min. The amorphous semiconductor film thus obtained was irradiated with a krypton fluorine (KrF) excimer laser to promote crystallization of the semiconductor film. The irradiation laser energy density was 245 mJ · cm −2, which was 15 mJ · cm −2 lower than the energy density at which the semiconductor film was completely melted over the entire thickness direction and microcrystallization was caused. After the crystalline semiconductor film (polycrystalline silicon film) is thus formed (first step), the crystalline semiconductor film is processed into an island shape, and the island 103 of the semiconductor film which will later become the active layer of the semiconductor device
Was formed. (FIG. 1A) Next, a silicon oxide film 104 was formed by ECR-PECVD so as to cover the island 103 of the semiconductor film subjected to the patterning process (second step). This silicon oxide film functions as a gate insulating film of the semiconductor device. The conditions for depositing the silicon oxide film as the gate insulating film are the same as the conditions for depositing the silicon oxide film as the base protective film, except that the deposition time is reduced to 24 seconds.
However, immediately before the deposition of the silicon oxide film, the substrate was irradiated with oxygen plasma in an ECR-PECVD apparatus to form a low-temperature plasma oxide film on the surface of the semiconductor. The plasma oxidation conditions are as follows.

【0017】 酸素(O)流量・・・100sccm 圧力・・・1.85mTorr マイクロ波(2.45GHz)出力・・・2000W 印可磁場・・・875Gauss 基板温度・・・100℃ 処理時間・・・24秒 プラズマ酸化に依り凡そ3.5nmの酸化膜が半導体表
面に形成されて居る。酸素プラズマ照射が終了した後、
真空を維持した侭連続で酸化膜を堆積した。従ってゲー
ト絶縁膜と成る酸化硅素膜はプラズマ酸化膜と気相堆積
膜の二者から成り、その膜厚は115nmで有った。
Oxygen (O 2 ) flow rate: 100 sccm Pressure: 1.85 mTorr Microwave (2.45 GHz) output: 2000 W Applicable magnetic field: 875 Gauss Substrate temperature: 100 ° C. Processing time: An oxide film of about 3.5 nm is formed on the semiconductor surface by plasma oxidation for 24 seconds. After the oxygen plasma irradiation ends,
An oxide film was deposited continuously while maintaining the vacuum. Therefore, the silicon oxide film serving as the gate insulating film was composed of a plasma oxide film and a vapor deposition film, and had a thickness of 115 nm.

【0018】第二工程で酸化硅素膜を形成した後、第三
工程として窒素プラズマ処理が施された。酸化膜が形成
された基板は平行平板容量結合型PECVD装置に導入
され、基板に対してアンモニアプラズマ照射(第三工
程)が施された。アンモニアプラズマ条件は以下の通り
で有る。
After forming the silicon oxide film in the second step, a nitrogen plasma treatment was performed as a third step. The substrate on which the oxide film was formed was introduced into a parallel plate capacitively coupled PECVD apparatus, and the substrate was irradiated with ammonia plasma (third step). Ammonia plasma conditions are as follows.

【0019】 アンモニア(NH)流量・・・1000sccm アルゴン(Ar)流量・・・1000sccm 圧力・・・1Torr rf波(13.56MHz)出力・・・200W 電極間距離・・・25mm 基板温度・・・370℃ 処理時間・・・90秒 次に第四工程として酸化性雰囲気下にて第一熱処理を行
った。濃度16%の塩化水素酸水溶液を空気中に露点で
96℃含む塩酸水蒸気空気下にて熱処理は施こされた。
処理温度は345℃で処理時間は2時間、処理室内圧力
は1気圧で有った。この塩酸に依る熱処理が終了した
後、引き続いて酸化膜中のハロゲン元素を抜く目的で1
時間の熱処理を継続した。この熱処理雰囲気は露点96
℃の水蒸気含有空気中で行われ、雰囲気に塩酸は含まれ
て居ない。熱処理温度は矢張り345℃で圧力は1気圧
で有る。この例が示す様に、第一熱処理に酸を用いた場
合、第一熱処理の後半で酸を抜いた水蒸気と酸素、或い
は水蒸気と酸素と不活性気体を主体とした雰囲気で熱処
理を行うのが好ましい。
Ammonia (NH 3 ) flow rate: 1000 sccm Argon (Ar) flow rate: 1000 sccm Pressure: 1 Torr rf wave (13.56 MHz) output: 200 W Distance between electrodes: 25 mm Substrate temperature 370 ° C. Processing time: 90 seconds Next, as a fourth step, a first heat treatment was performed in an oxidizing atmosphere. The heat treatment was performed in hydrochloric acid steam air containing a hydrochloric acid aqueous solution having a concentration of 16% in air at a dew point of 96 ° C.
The processing temperature was 345 ° C., the processing time was 2 hours, and the processing chamber pressure was 1 atm. After the completion of the heat treatment with hydrochloric acid, one step is to remove halogen elements in the oxide film.
The heat treatment was continued for hours. This heat treatment atmosphere has a dew point of 96.
The test is carried out in air containing water vapor at ℃, and the atmosphere does not contain hydrochloric acid. The heat treatment temperature is 345 ° C. and the pressure is 1 atm. As shown in this example, when an acid is used for the first heat treatment, the heat treatment is performed in an atmosphere mainly composed of steam and oxygen, or steam, oxygen, and an inert gas, in the latter half of the first heat treatment. preferable.

【0020】斯うして第四工程が終了した後に第五工程
の第二熱処理を行い、酸化膜を乾燥さた。第二熱処理は
アルゴン中に水素を3%含む非酸化性雰囲気下にて1気
圧、400℃で2時間施された。斯様にしてゲート絶縁
膜堆積と、酸化膜及び界面の改質が完了した。(図1−
b) 引き続いて金属薄膜に依りゲート電極105をスパッタ
ー法にて形成する。スパッター時の基板温度は150℃
で有った。本実施例1では750nmの膜厚を有するα
構造のタンタル(Ta)にてゲート電極を作成し、この
ゲート電極のシート抵抗は0.8Ω/□で有った。次に
ゲート電極をマスクとして、ドナー又はアクセプターと
なる不純物イオン106を打ち込み、ソース・ドレイン
領域107とチャンネル形成領域108をゲート電極に
対して自己整合的に作成する。本実施例1ではCMOS
半導体装置を作製した。NMOSトランジスタを作製す
る際にはPMOSトランジスタ部をアルミニウム(A
l)薄膜で覆った上で、不純物元素として水素中に5%
の濃度で希釈されたフォスヒィン(PH)を選び、加
速電圧80kVにて水素を含んだ総イオンを7×10
15cm−2の濃度でNMOSトランジスタのソース・
ドレイン領域に打ち込んだ。反対にPMOSトランジス
タを作製する際にはNMOSトランジスタ部をアルミニ
ウム(Al)薄膜で覆った上で、不純物元素として水素
中に5%の濃度で希釈されたジボラン(B)を選
び、加速電圧80kVにて水素を含んだ総イオンを5×
1015cmー2の濃度でPMOSトランジスタのソー
ス・ドレイン領域に打ち込んだ。(図1−c)イオン打
ち込み時の基板温度は300℃で有る。
After the completion of the fourth step, the second heat treatment of the fifth step was performed to dry the oxide film. The second heat treatment was performed in a non-oxidizing atmosphere containing 3% of hydrogen in argon at 1 atm and 400 ° C. for 2 hours. Thus, the deposition of the gate insulating film and the modification of the oxide film and the interface are completed. (Figure 1
b) Subsequently, a gate electrode 105 is formed by a sputtering method using a metal thin film. The substrate temperature during sputter is 150 ° C
It was. In the first embodiment, α having a thickness of 750 nm
A gate electrode was formed from tantalum (Ta) having a structure, and the sheet resistance of the gate electrode was 0.8Ω / □. Next, using the gate electrode as a mask, an impurity ion 106 serving as a donor or an acceptor is implanted, and a source / drain region 107 and a channel formation region 108 are formed in a self-aligned manner with respect to the gate electrode. In the first embodiment, the CMOS
A semiconductor device was manufactured. When fabricating an NMOS transistor, the PMOS transistor portion is made of aluminum (A
l) After covering with a thin film, 5%
Phosphine (PH 3 ) diluted at a concentration of 7 × 10 3
At a concentration of 15 cm -2 , the source of the NMOS transistor
Driven into the drain region. Conversely, when fabricating a PMOS transistor, after covering the NMOS transistor portion with an aluminum (Al) thin film, diborane (B 2 H 6 ) diluted in hydrogen at a concentration of 5% is selected as an impurity element and accelerated. 5x total ions containing hydrogen at a voltage of 80 kV
It was implanted into the source / drain region of the PMOS transistor at a concentration of 10 15 cm -2 . (FIG. 1-c) The substrate temperature at the time of ion implantation is 300 ° C.

【0021】次にPECVD法でTEOS(Si−(O
CHCH)と酸素を原料気体として、基板温度
300℃で層間絶縁膜109を堆積した。層間絶縁膜は
二酸化硅素膜から成り、その膜厚は凡そ500nmで有
った。層間絶縁膜堆積後、層間絶縁膜の焼き締めとソー
ス・ドレイン領域に添加された不純物元素の活性化を兼
ねて、窒素雰囲気下350℃にて2時間の熱処理を施し
た。最後にコンタクト・ホールを開穴し、スパッター法
で基板温度を180℃としてアルミニウムを堆積し、配
線110を作成して薄膜半導体装置が完成した。(図1
−d) この様にして作成した薄膜半導体装置の伝達特性を測定
した。測定した半導体装置のチャンネル形成領域の長さ
及び幅は其々10μmで、測定は室温にて行われた。N
MOSトランジスタのVds=8Vに於ける飽和領域よ
り求めた移動度は93.4cm・Vー1・s−1で有
り、閾値電圧は3.21V、サブスレーシュホールド・
スイングは0.477Vで有った。又、PMOSトラン
ジスタのVds=−8Vに於ける飽和領域より求めた移
動度は45.2cm・Vー1・s−1で有り、閾値電
圧は−3.71V、サブスレーシュホールド・スイング
は0.504Vで有った。此に対して本実施例1から第
三工程乃至第五工程を削除した比較例ではNMOSトラ
ンジスタの移動度が74.2cm・Vー1・s−1
閾値電圧が4.34V、サブスレーシュホールド・スイ
ングが0.651Vで、PMOSトランジスタの移動度
が32.6cm・Vー1・s−1、閾値電圧が−7.
00V、サブスレーシュホールド・スイングが0.63
3Vで有った。本願発明に依りN型とP型の両半導体装
置共に高移動度で低閾値電圧を有し、急峻なサブスレー
シュホールド特性を示す良好な薄膜半導体装置が安定的
に製造された。又、本願発明で作成したCMOS回路
(リングオスシレーター)は比較例よりも優れた動作安
定性を示した。此等の例が示す様に本発明に依ると優れ
た特性を有し、然も酸化膜の信頼性が高い薄膜半導体装
置を汎用ガラス基板を使用し得る低温工程にて、簡便且
つ容易に作成し出来るので有る。
Next, TEOS (Si- (O
Using CH 2 CH 3 ) 4 ) and oxygen as source gases, an interlayer insulating film 109 was deposited at a substrate temperature of 300 ° C. The interlayer insulating film was made of a silicon dioxide film, and its thickness was about 500 nm. After the deposition of the interlayer insulating film, a heat treatment was performed at 350 ° C. for 2 hours in a nitrogen atmosphere to bake the interlayer insulating film and activate the impurity element added to the source / drain regions. Finally, a contact hole was opened, aluminum was deposited at a substrate temperature of 180 ° C. by a sputtering method, and a wiring 110 was formed to complete a thin film semiconductor device. (Figure 1
-D) The transfer characteristics of the thin film semiconductor device thus prepared were measured. The length and width of the channel formation region of the semiconductor device measured were 10 μm each, and the measurement was performed at room temperature. N
The mobility of the MOS transistor obtained from the saturation region at Vds = 8 V is 93.4 cm 2 · V −1 · s −1 , the threshold voltage is 3.21 V, and the
The swing was 0.477V. The mobility of the PMOS transistor obtained from the saturation region at Vds = −8 V is 45.2 cm 2 · V −1 · s −1 , the threshold voltage is −3.71 V, and the sub slash hold swing is It was 0.504V. On the other hand, in the comparative example in which the third to fifth steps are deleted from the first embodiment, the mobility of the NMOS transistor is 74.2 cm 2 · V −1 · s −1 ,
The threshold voltage is 4.34 V, the subthreshold hold swing is 0.651 V, the mobility of the PMOS transistor is 32.6 cm 2 · V −1 · s −1 , and the threshold voltage is −7.
00V, sub-leash hold swing 0.63
It was 3V. According to the present invention, both N-type and P-type semiconductor devices have a high mobility, a low threshold voltage, and a good thin-film semiconductor device showing a steep sub-threshold hold characteristic has been stably manufactured. In addition, the CMOS circuit (ring oscillator) produced by the present invention exhibited better operation stability than the comparative example. As shown in these examples, according to the present invention, a thin film semiconductor device having excellent characteristics and a highly reliable oxide film can be easily and easily formed in a low-temperature process in which a general-purpose glass substrate can be used. I can do it.

【0022】[0022]

【発明の効果】以上詳述してきた様に、従来プラズマ損
傷が夥しく、且つ製造価格がかさんでいた薄膜半導体装
置を本願発明はプラズマ損傷を最少とし、更に修繕する
事を可能と化した。同時に半導体装置の電気特性を著し
く向上させると共にその動作安定性をも高め、更に低価
格化に結びつくとの効果が認められる。
As described in detail above, the present invention minimizes plasma damage and makes it possible to repair the thin-film semiconductor device, which has conventionally suffered enormous plasma damage and was expensive to manufacture. . At the same time, the effect of remarkably improving the electrical characteristics of the semiconductor device, improving the operation stability thereof, and further reducing the cost is recognized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本願発明の製造工程を説明した図。FIG. 1 is a diagram illustrating a manufacturing process of the present invention.

【符号の説明】[Explanation of symbols]

101・・・基板 102・・・下地保護膜 103・・・半導体膜の島 104・・・酸化硅素膜 105・・・ゲート電極 106・・・不純物イオン 107・・・ソース・ドレイン領域 108・・・チャネル形成領域 109・・・層間絶縁膜 110・・・配線 DESCRIPTION OF SYMBOLS 101 ... Substrate 102 ... Underlying protective film 103 ... Semiconductor film island 104 ... Silicon oxide film 105 ... Gate electrode 106 ... Impurity ions 107 ... Source / drain region 108 ...・ Channel forming region 109 ・ ・ ・ Interlayer insulating film 110 ・ ・ ・ Wiring

Claims (14)

【特許請求の範囲】[Claims] 【請求項1】 基板上に形成された半導体膜と、該半導
体膜上に形成された絶縁膜を少なくとも構成要件として
有する半導体装置の製造方法に於いて、 半導体膜を基板上に形成する第一工程と、気相堆積法に
て酸化膜を堆積する第二工程と、該基板に窒化処理を施
す第三工程と、該基板を酸化性雰囲気下にて第一熱処理
を施す第四工程と、該基板に第二熱処理を施す第五工程
とを含む事を特徴とする半導体装置の製造方法。
In a method of manufacturing a semiconductor device having at least a semiconductor film formed on a substrate and an insulating film formed on the semiconductor film as a constituent feature, a first method for forming a semiconductor film on a substrate is provided. Step, a second step of depositing an oxide film by a vapor deposition method, a third step of performing a nitriding treatment on the substrate, and a fourth step of performing a first heat treatment on the substrate in an oxidizing atmosphere, A fifth step of subjecting the substrate to a second heat treatment.
【請求項2】 前記半導体膜が多結晶膜で有る事を特徴
とする請求項1記載の半導体装置の製造方法。
2. The method according to claim 1, wherein the semiconductor film is a polycrystalline film.
【請求項3】 前記半導体膜が硅素(Si)を主体と成
して居る事を特徴とする請求項1または2記載の半導体
装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor film is mainly composed of silicon (Si).
【請求項4】 前記酸化膜が酸化硅素(SiO:0<
x≦2)を主体と成して居る事を特徴とする請求項1乃
至3のいずれかに記載の半導体装置の製造方法。
4. The method according to claim 1, wherein the oxide film is made of silicon oxide (SiO x : 0 <
4. The method for manufacturing a semiconductor device according to claim 1, wherein x ≦ 2 is mainly used.
【請求項5】 前記第三工程がアンモニア(NH)を
含有したプラズマ照射で有る事を特徴とする請求項1乃
至4のいずれかに記載の半導体装置の製造方法。
5. The method for manufacturing a semiconductor device according to claim 1, wherein said third step is irradiation with plasma containing ammonia (NH 3 ).
【請求項6】 前記第四工程が前記酸化膜の結合を切断
し得る物質を含む雰囲気下にて行われる事を特徴とする
請求項1乃至5のいずれかに記載の半導体装置の製造方
法。
6. The method for manufacturing a semiconductor device according to claim 1, wherein said fourth step is performed in an atmosphere containing a substance capable of breaking a bond of said oxide film.
【請求項7】 前記酸化膜の結合を切断し得る物質が水
で有る事を特徴とする請求項6記載の半導体装置の製造
方法。
7. The method according to claim 6, wherein the substance capable of breaking the bond of the oxide film is water.
【請求項8】 前記酸化膜の結合を切断し得る物質がハ
ロゲン原子を含有して居る事を特徴とする請求項6記載
の半導体装置の製造方法。
8. The method for manufacturing a semiconductor device according to claim 6, wherein the substance capable of breaking the bond of the oxide film contains a halogen atom.
【請求項9】 前記第五工程が非酸化性雰囲気下にて行
われる事を特徴とする請求項1乃至8のいずれかに記載
の半導体装置の製造方法。
9. The method according to claim 1, wherein the fifth step is performed in a non-oxidizing atmosphere.
【請求項10】 前記第五工程が不活性雰囲気下にて行
われる事を特徴とする請求項1乃至8のいずれかに記載
の半導体装置の製造方法。
10. The method according to claim 1, wherein the fifth step is performed in an inert atmosphere.
【請求項11】 前記第五工程が水素含有雰囲気下にて
行われる事を特徴とする請求項1乃至8のいずれかに記
載の半導体装置の製造方法。
11. The method according to claim 1, wherein the fifth step is performed in a hydrogen-containing atmosphere.
【請求項12】 前記第五工程の熱処理温度が前記第三
工程の熱処理温度と略同じで有る事を特徴とする請求項
1乃至11のいずれかに記載の半導体装置の製造方法。
12. The method according to claim 1, wherein the heat treatment temperature in the fifth step is substantially the same as the heat treatment temperature in the third step.
【請求項13】 前記第五工程の熱処理温度が前記第三
工程の熱処理温度よりも高い事を特徴とする請求項1乃
至11のいずれかに記載の半導体装置の製造方法。
13. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment temperature in the fifth step is higher than the heat treatment temperature in the third step.
【請求項14】 前記第五工程の熱処理温度が前記第二
工程以降該半導体装置が完成する迄の全工程中の最高温
度で有る事を特徴とする請求項12または13記載の半
導体装置の製造方法。
14. The manufacturing of a semiconductor device according to claim 12, wherein the heat treatment temperature in the fifth step is the highest temperature in all the steps from the second step to the completion of the semiconductor device. Method.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004107431A1 (en) * 2003-05-30 2004-12-09 Tokyo Electron Limited Method for modifying insulating film
JP2010028124A (en) * 2004-03-25 2010-02-04 Japan Science & Technology Agency Method of manufacturing substrate suitable for device containing organic material, and method of manufacturing device containing organic material
JP2022008633A (en) * 2017-11-15 2022-01-13 学校法人加計学園 Manufacturing method of rare earth hydride, hydrogen sensor, and thin film transistor

Cited By (7)

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Publication number Priority date Publication date Assignee Title
WO2004107431A1 (en) * 2003-05-30 2004-12-09 Tokyo Electron Limited Method for modifying insulating film
KR100887330B1 (en) * 2003-05-30 2009-03-06 도쿄엘렉트론가부시키가이샤 Method for modifying insulation film and method for manufacturing semiconductor device
US7655574B2 (en) 2003-05-30 2010-02-02 Tokyo Electron Limited Method of modifying insulating film
US8021987B2 (en) 2003-05-30 2011-09-20 Tokyo Electron Limited Method of modifying insulating film
JP2010028124A (en) * 2004-03-25 2010-02-04 Japan Science & Technology Agency Method of manufacturing substrate suitable for device containing organic material, and method of manufacturing device containing organic material
JP2022008633A (en) * 2017-11-15 2022-01-13 学校法人加計学園 Manufacturing method of rare earth hydride, hydrogen sensor, and thin film transistor
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