JP2000200903A - Method for manufacturing semiconductor device - Google Patents

Abstract

An object of the present invention is to provide a method for manufacturing a field effect transistor having an LDD structure using a sidewall spacer on a side wall of a gate electrode. An object is to provide a method for manufacturing a semiconductor device which can be manufactured. A concentration 2wt gate electrode 20 side wall through the SiO ₂ film 24. % P-doped P-DP
A sidewall spacer 26a made of the S26 film is formed. For this reason, after the high concentration impurity region 28 is formed by implanting high concentration impurity ions,
When removing the spacer 26a, the etching time can be shortened, and all the sidewall spacers 26a are almost uniformly removed under a predetermined etching condition, so that the etching residue of the specific sidewall spacer 26a is removed. Generation can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to an LDD (Lightly Doped) using a sidewall spacer on a side wall of a gate electrode.
The present invention relates to a method for manufacturing a field effect transistor having a ped drain structure.

[0002]

2. Description of the Related Art A conventional LDD structure MOS (Metal Oxid
e Semiconductor) A method of manufacturing a transistor is shown in FIG.
This will be described with reference to FIGS. In each of the cross-sectional views, a transistor portion for forming a MOS transistor is shown on the left side, and a field portion for insulating the transistor portion is shown on the right side.

[0003] For example, LOCOS (Lo) is applied to a field portion of an Si (silicon) substrate 50 as a semiconductor substrate.
A field oxide film 52 for device isolation is formed by using a cal oxidation of silicon (selective oxidation) method. And
On the Si substrate 50 of the transistor portion surrounded by the field oxide film 52, via the gate oxide film 54,
A gate electrode 60 in which a polysilicon layer 56 and a silicide layer 58 are sequentially stacked is formed. Subsequently, using the gate electrode 60 as a mask, low-concentration impurity ions are implanted into the Si substrate 50 to form a low-concentration impurity region 62 on the surface of the Si substrate 50. Thereafter, for example, CVD (Chemical Vap
An SiO ₂ film (silicon oxide film) 64 having a sufficient film thickness is deposited on the entire surface of the substrate by using a chemical vapor deposition (or chemical vapor deposition) method (see FIG. 10).

Next, the entire surface of the SiO ₂ film 64 is etched back to leave the SiO ₂ film 64 only on the side wall of the gate electrode 60. Thus, the SiO _{2 is formed on the} side wall of the gate electrode 60.
A sidewall spacer 64a made of the film 64 is formed (see FIG. 11).

Next, high concentration impurity ions are implanted into the Si substrate 50 by using the gate electrode 60 and the sidewall spacers 64a on both side walls as a mask, as shown by arrows in FIG. A high-concentration impurity region 66 having resistance is formed. The LDD is formed from the high concentration impurity region 66 and the low concentration impurity region 62 formed earlier.
A source / drain region 68 of the structure is formed.

The source / drain region 68 of the LDD structure formed opposite to the surface of the Si substrate 50 and the channel region sandwiched between the two opposite source / drain regions 68 with the gate oxide film 54 interposed therebetween. A MOS transistor composed of the gate electrode 60 formed as described above is formed (see FIG. 12).

Next, an SiN film (silicon nitride film) 70 as an etching stopper layer is deposited on the entire surface of the substrate by, for example, a CVD method, and then an interlayer insulating film 72 is further deposited on the SiN film 70. Then, the interlayer insulating film 72 and the SiN film 70 are selectively etched by using a lithography technique to form a contact window 74 exposing the high-concentration impurity region 66 of the source / drain region 68.

At this time, in order to supplement the processing accuracy of the contact window 74, Si is used as an etching stopper layer between the sidewall spacer 64a and the interlayer insulating film 72.
A method is adopted in which the selective etching of the interlayer insulating film 72 for opening the contact window 74 with the N film 70 interposed is once stopped by the SiN film 70, and then the exposed SiN film 70 is removed by etching. In this case, even if the opening position of the contact window 74 is slightly shifted to the gate electrode 60 side, when the SiN film 70 is etched away,
Sidewall spacer 64 made of SiO ₂ film 64
a remains as it is, the contact window 74
Are formed in a self-aligned manner. For this reason, the contact window 74 does not expose the gate electrode 60 to cause an electrical short (see FIG. 13).

However, in the above-mentioned conventional method of manufacturing a MOS transistor having an LDD structure, since the SiO ₂ film 64 is used as the material of the sidewall spacer 64a, as shown in FIG. When the entire surface of the formed SiO ₂ film 64 is etched back to form the sidewall spacers 64 a on the side walls of the gate electrode 60, the SiO ₂ film 64 on the field oxide film 52 for element isolation is removed.
Not only the _second film 64 but also the field oxide film 52 itself is over-etched, and its film thickness is, for example, t1 as a whole.
Only thinner.

For this reason, as shown in FIG.
When high-concentration impurity ions are implanted into the Si substrate 50 using the gate electrode 60 and the sidewall spacers 64a on both side walls as a mask, the thickness of the field oxide film 52, which is reduced as a whole, becomes particularly thin. A phenomenon occurs in which impurity ions penetrate the peripheral portion. Therefore, the high-concentration impurity regions 66 are formed up to the surface of the Si substrate 50 in contact with the lower surface of the field oxide film 52 in the peripheral portion. As a result, there is a problem that the element isolation capability of the field oxide film 52 is reduced.

After forming the MOS transistor,
When the interlayer insulating film 72 and the SiN film 70 are selectively etched in order to form a contact window 74 exposing the high-concentration impurity region 66 of the source / drain region 68,
As shown in FIG.
4a remains as it is, so that even if the opening position of the contact window 74 is slightly shifted to the gate electrode 60 side, occurrence of an electrical short between the gate electrode 60 and the source / drain region 68 is prevented, but on the other hand However, the presence of the sidewall spacers 64a reduces the bottom area of the contact window 74, which is opened, in a slit-like manner. As a result, there is a problem that the processing accuracy of the contact window 74 is reduced.

In order to solve the above-mentioned problems of the conventional method of manufacturing a MOS transistor having an LDD structure, another manufacturing method using a polysilicon film as a material of a sidewall spacer formed on a side wall of a gate electrode has been proposed. .

Next, another method of manufacturing the conventional MOS transistor having the LDD structure will be described with reference to the process sectional views of FIGS. In each of the cross-sectional views, a transistor portion for forming a MOS transistor is shown on the left side, and a field portion for insulating the transistor portion is shown on the right side. The same components as those of the MOS transistor shown in FIGS. 10 to 13 are denoted by the same reference numerals, and description thereof is omitted.

In the field portion of the Si substrate 50, for example, L
Field oxide film 5 for element isolation using OCOS method
After forming the gate electrode 60, a polysilicon layer 56 and a silicide layer 58 are sequentially stacked on the Si substrate 50 of the transistor portion surrounded by the field oxide film 52 via the gate oxide film 54. To form Then, low-concentration impurity regions 62 are formed on the surface of the Si substrate 50 by implanting low-concentration impurity ions using the gate electrode 60 as a mask. Subsequently, after that, using, for example, a CVD method, Si is used as an etching stopper layer over the entire surface of the substrate.
After depositing the O ₂ film 76, a polysilicon film 78 having a sufficient thickness is deposited on the SiO ₂ film 76 (see FIG. 14).

Next, the entire surface of the polysilicon film 78 is etched back, and the SiO ₂ film 7 is formed only on the side walls of the gate electrode 60.
The polysilicon film 78 is left through the film 6. Note that, when the entire surface of the polysilicon film 78 is etched back, Si
The O ₂ film 76 functions as an etching stopper layer. Thus, a sidewall spacer 78a made of the polysilicon film 78 is formed on the side wall of the gate electrode 60 via the SiO ₂ film 76 (see FIG. 15).

Next, the gate electrode 60, the SiO ₂ film 76 on both side walls thereof, and the side wall spacers 78a are formed.
Is used as a mask, as shown by arrows in FIG.
A high-concentration impurity ion is implanted into the Si substrate 50 to form a low-resistance high-concentration impurity region 66 on the surface of the Si substrate 50. And
The source / drain region 68 having the LDD structure is formed from the high concentration impurity region 66 and the low concentration impurity region 62 formed earlier.
(See FIG. 16).

Next, the sidewall spacer 78a on the side wall of the gate electrode 60 is removed by isotropic etching. Also at this time, the SiO ₂ film 76 functions as an etching stopper layer for isotropic etching of the sidewall spacer 78a made of the polysilicon film. Since the sidewall spacer 78a becomes a conductive film by being implanted with high-concentration impurity ions,
If left as it is, this may cause an electrical short between contacts in a later process, and therefore, the removal of the sidewall spacer 78a is an essential step. Thus, the source / drain regions 68 of the LDD structure formed facing the surface of the Si substrate 50
Then, a MOS transistor including a gate electrode 60 formed via a gate oxide film 54 on a channel region interposed between these two opposite source / drain regions 68 is formed (see FIG. 17).

Next, an SiN film 70 as an etching stopper layer is deposited on the entire surface of the substrate using, for example, a CVD method, and further an interlayer insulating film 72 is formed on the SiN film 70.
Is deposited. Subsequently, the interlayer insulating film 72, the SiN film 70, and the SiO ₂ film 76 are selectively etched by using a lithography technique to form a contact window 80 exposing the high-concentration impurity region 66 of the source / drain region 68. .

At this time, in order to supplement the processing accuracy of the contact window 80, an SiN film 70 as an etching stopper layer is interposed between the SiO ₂ film 76 and the interlayer insulating film 72 to open the contact window 80. Interlayer insulating film 72
Is selectively stopped by the SiN film 70, and then the exposed SiN film 70 is removed by etching.
Further, a method of etching and removing the exposed SiO ₂ film 76 is employed (see FIG. 18).

As described above, the MO of the conventional LDD structure is used.
In another method of manufacturing the S transistor, a polysilicon film 78 is used as a material of the sidewall spacer 78a.
Since the SiO ₂ film 76 is provided as an etching stopper layer under the polysilicon film 78,
As shown in FIG. 15, the polysilicon film 78 deposited on the entire surface of the base is etched back to form the gate electrode 60.
When the sidewall spacers 78a are formed on the side walls, since the SiO ₂ film 76 is also formed as an etching stopper layer on the field oxide film 52 for element isolation, the field oxide film 52 itself is etched to form a thin film. Will not be converted.

For this reason, as shown in FIG. 16, the Si substrate 5 is formed using the gate electrode 60, the SiO ₂ film 76 and the sidewall spacers 78a on both side walls thereof as a mask.
When impurity ions having a high concentration are implanted to zero, the phenomenon that the impurity ions penetrate through the peripheral field oxide film 52 is suppressed. Therefore, the high-concentration impurity region 66 is prevented from escaping to the lower surface of the field oxide film 52 in the peripheral portion, and a decrease in the element isolation capability of the field oxide film 52 can be prevented.

After forming the MOS transistor,
When forming a contact window 80 exposing the high concentration impurity region 66 of the source / drain region 68, as shown in FIG. 18, an interlayer insulating film 72, a SiN film 70 as an etching stopper layer, and a SiO ₂ film 76 are formed. Is selectively removed by etching, but at this time, since the sidewall spacer 78a does not remain on the side wall of the gate electrode 60, the bottom area of the opened contact window 80 does not decrease in a slit shape. As a result, the processing accuracy of the contact window 80 can be improved.

[0023]

When the polysilicon film and the SiO ₂ film are etched, impurity ions are implanted into the polysilicon film and the SiO ₂ film as shown in the graphs of FIGS. Presence, type of implanted impurity ions (As ion, BF ₂ ion, etc.),
The etching rate (Etch Rate) of the polysilicon film and the SiO ₂ film changes depending on the dose of the impurity ions (Dosage), the implantation energy of the impurity ions, and the like. For this reason, as shown in the graphs of FIGS. 19 and 20,
For example, when etching the polysilicon film and the SiO ₂ film using a fluorine-based etchant, the ratio between the etching speed of the polysilicon film and the etching speed of the SiO ₂ film, that is, the etching selectivity (Etch Selectivity) also changes. .

In the graphs of FIGS. 19 and 20, when the dose of impurity ions and the energy for implanting impurity ions increase, the etching rates of the polysilicon film and the SiO ₂ film tend to increase, respectively. The etching selectivity between the silicon film and the SiO ₂ film tends to decrease substantially. Regarding the latter, since many defects are generated in the SiO ₂ film by the high concentration and high energy impurity ion implantation, the degree of increase in the etching rate is relatively large compared to the polysilicon film. it is conceivable that.

In another method of manufacturing the conventional MOS transistor having the LDD structure, the SiO ₂ film 76 is etched by an etching stopper due to the change in the etching selectivity between the polysilicon film and the SiO ₂ film due to the impurity ion implantation conditions. When the sidewall spacers 78a on the side walls of the gate electrode 60 are removed by isotropic etching as a layer, there is a problem that it is difficult to stably remove the sidewall spacers 78a by etching.

That is, as shown in FIG.
When forming the high-concentration impurity regions 66 of the source / drain regions 68 having the D structure, high-concentration impurity ions have already been implanted into the sidewall spacers 78a on the side walls of the gate electrode 60 and the underlying SiO ₂ film 76. . For this reason, various types of MOSs constituting an LSI (Large Scale Integrated Circuit)
In the transistor, the sidewall spacer 7
In some cases, the impurity ion implantation states for the SiO ₂ film 8a and the underlying SiO ₂ film 76 are different.

For example, as shown in FIG.
In a MOS transistor constituting a memory cell transistor of a DRAM (Dynamic Random Access Memory), an n ⁻ -type low-concentration impurity region 62 a is formed on the surface of the Si substrate 50 sandwiching the gate electrode 60, while an n ⁺ -type high-concentration impurity region is Since the gate electrode 6 is not formed,
0 side wall spacer 78a and underlying S
No impurity ions have been implanted into the iO ₂ film 76. Further, as shown in FIG. 21 (b), in the N-channel MOS transistor constituting a logic transistor, n the Si substrate 50 surface which sandwich the gate electrode 60 ^- n ⁺ -type highly-doped with type low-concentration impurity regions 62a An impurity region 66a is formed, and a sidewall spacer 78a on the side wall of the gate electrode 60 and an underlying SiO ₂
N-type impurity ions are implanted into the film 76 at a high concentration. Further, as shown in FIG. 21 (c), in the P-channel MOS transistor constituting a logic transistor, p the Si substrate 50 surface which sandwich the gate electrode 60 ^- p ⁺ -type highly-doped with type low-concentration impurity regions 62b An impurity region 66b is formed, and a sidewall spacer 78a on the side wall of the gate electrode 60 and an underlying SiO ₂
A high concentration of p-type impurity ions is implanted into the film 76.

Therefore, when the side wall spacer 78a on the side wall of the gate electrode 60 of each of the MOS transistors shown in FIGS. 21A to 21C is removed by isotropic etching, FIG. The etching rate of the sidewall spacer 78a into which the impurity ions have not been implanted is the etching rate of the sidewall spacer 78a into which the n-type or p-type impurity ions are implanted at a high concentration as shown in FIGS. Be less than the speed. Also,
21B and 21C, sidewall spacers 78 into which n-type or p-type impurity ions are implanted at a high concentration.
The etching selectivity between a and the underlying SiO ₂ film 76 is smaller than the etching selectivity between the sidewall spacer 78a into which the impurity ions are not implanted and the underlying SiO ₂ film 76 in FIG.

For this reason, the isotropic etching conditions were changed as shown in FIG.
If the optimum conditions are set for the removal of the sidewall spacers 78a in (b) and (c), as shown in FIG. 21 (a), the sidewall spacers 78a into which impurity ions have not been implanted are completely removed. And remains on the side wall of the gate electrode 60.

Conversely, if the isotropic etching conditions are set so that the sidewall spacers 78a into which the impurity ions of FIG. 21A are not implanted are completely removed, FIGS. c) The sidewall spacer 78a is over-etched. At this time, even the underlying SiO ₂ film 76 whose etching selectivity with respect to the sidewall spacer 78a has become small is cut off more than necessary, as shown in FIGS. 21 (b) and 21 (c). The thickness of the SiO ₂ film 76 is reduced to t2 and t3, respectively. Therefore, locally the SiO ₂ film 7
6, the high concentration impurity region 66 of the source / drain region 68 is exposed. Then, the exposed surface of the Si substrate 50 is etched by isotropic etching of the sidewall spacer 78a made of the polysilicon film 78, and trenches 82a and 82b as shown in FIGS. May occur.

The side wall spacer 78
In order to prevent the underlying SiO ₂ film 76 from being shaved during the overetching of a, and locally exposing the n ⁺ -type high concentration impurity region 66a or the p ⁺ -type high concentration impurity region 66b on the surface of the Si substrate 50. Then, for example, an underlying SiO ₂ film 7
6 may be made sufficiently thick. However, in this case, the thicker the underlying SiO ₂ film 76 is, the more the impurity ion implantation for forming the n ⁺ -type high concentration impurity region 66a or the p ⁺ -type high concentration impurity region 66b is performed. In such a case, it is necessary to increase the dose amount and the implantation energy, which may cause a short-channel effect of the MOS transistor or deteriorate the element isolation characteristics, which may adversely affect the transistor characteristics.

Accordingly, the present invention has been made in view of the above problems, and is not needed in a method of manufacturing a semiconductor device for manufacturing a field effect transistor having an LDD structure by using a sidewall spacer on a side wall of a gate electrode. When removing the side wall spacers made of the polysilicon film, the remaining of the side wall spacers and the source due to the change of the etching rate due to the presence or absence of impurity ions and the etching selectivity with the underlying silicon oxide film are removed. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can manufacture a field-effect transistor having good transistor characteristics without causing formation of a groove in a drain / drain region.

[0033]

The above object is achieved by the following method of manufacturing a semiconductor device according to the present invention. That is, a method of manufacturing a semiconductor device according to claim 1 includes a first step of implanting a first impurity ion into a semiconductor substrate using a gate electrode formed on the semiconductor substrate via a first insulating film as a mask. A second insulating film is deposited on the entire surface of the substrate.
After depositing a polysilicon film doped with a predetermined impurity on the second insulating film, the polysilicon film is etched back, and the polysilicon film is formed on the side wall of the gate electrode via the second insulating film. Side wall made of silicon film
A third step of forming a spacer, a fourth step of implanting a second impurity ion into the semiconductor substrate using the gate electrode and the sidewall spacer as a mask,
A fifth step of selectively removing the sidewall spacers by etching using the insulating film as an etching stopper layer.

As described above, in the method of manufacturing a semiconductor device according to the first aspect, the sidewall spacer made of the polysilicon film doped with the predetermined impurity is formed on the side wall of the gate electrode via the second insulating film. Thus, when implanting high-concentration impurity ions for forming the high-concentration impurity regions of the source / drain regions of the LDD structure, even if the sidewall spacer is not implanted with any impurity ions, n Even if the sidewall spacers are heavily implanted with impurity ions of p-type or p-type, all of these sidewall spacers are pre-doped with a predetermined impurity. The speed is generally higher and the etch between these sidewall spacers is The difference between the grayed speed is reduced. For this reason, when the sidewall spacers are removed by etching, all the sidewall spacers are almost uniformly removed under predetermined isotropic etching conditions, and specific sidewall spacers, for example, any impurity ions are implanted. Even in the sidewall spacers which have not been etched, the etching residue of the sidewall spacers does not remain on the side walls of the gate electrode.

Further, the etching selectivity between the sidewall spacer and the underlying second insulating film is increased as a whole, and the difference in etching selectivity between the plurality of sidewall spacers is reduced. When the spacer is removed by etching, the underlying second insulating film will not be cut off more than necessary, and the second insulating film will be locally lost and the source / source of the LDD structure will be removed.
It is also possible to prevent a situation in which the high-concentration impurity region of the drain region is exposed, and the exposed portion is etched by isotropic etching of the sidewall spacer, thereby forming a trench.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device, a first impurity ion is implanted into a semiconductor substrate using a gate electrode formed on the semiconductor substrate via a first insulating film as a mask. And a second step of depositing a second insulating film over the entire surface of the substrate. After depositing an amorphous silicon film doped with a predetermined impurity on the second insulating film, the amorphous silicon film is etched. Backing and forming a side wall spacer made of an amorphous silicon film on the side wall of the gate electrode with a second insulating film interposed therebetween, and forming a third step on the semiconductor substrate using the gate electrode and the side wall spacer as a mask. A fourth step of implanting the second impurity ions, and selectively etching the sidewall spacers using the second insulating film as an etching stopper layer. And having a fifth step of grayed removed, the.

As described above, in the method of manufacturing a semiconductor device according to the second aspect, the sidewall spacer made of the amorphous silicon film doped with a predetermined impurity is formed on the gate electrode side wall via the second insulating film. That is, in the method of manufacturing a semiconductor device according to claim 1, an amorphous silicon film doped with a predetermined impurity is used instead of the polysilicon film doped with a predetermined impurity used as a material of the sidewall spacer. By using the material as a material for the sidewall spacer, the same operation as in the method of manufacturing a semiconductor device according to the first aspect is achieved.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the first or second aspect, after the fourth step, that is, by masking the gate electrode and the sidewall spacer. After the second impurity ions are implanted into the semiconductor substrate before the fifth step,
That is to say, before the sidewall spacers are removed by etching using the second insulating film as an etching stopper layer, a step of performing an annealing process is provided.
The defects generated in the second insulating film underlying the sidewall spacers by the implantation of the impurity ions are recovered,
Since the etching rate of the second insulating film is lower, the etching selectivity between the sidewall spacer and the underlying second insulating film is further increased as a whole. Therefore, when the sidewall spacers are removed by etching, the underlying second insulating film functioning as an etching stopper layer is cut off more than necessary, and the second insulating film is locally lost and the source / drain region having the LDD structure is formed. The margin for exposing the high-concentration impurity region of
The occurrence of such a situation that the exposed portion is etched by isotropic etching with respect to the sidewall spacer and a trench is dug is prevented more effectively.

[0039]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment of the present invention will be described. (First Embodiment) FIGS. 1 to 5 show a first embodiment of the present invention.
FIG. 10 is a process cross-sectional view for describing the method for manufacturing the MOS transistor having the LDD structure according to the embodiment. In each of the cross-sectional views, a transistor portion for forming a MOS transistor is shown on the left side, and a field portion for insulating the transistor portion is shown on the right side.

After a field oxide film 12 for element isolation is formed in a field portion of a Si substrate 10 as a semiconductor substrate by using, for example, the LOCOS method, the Si portion of a transistor portion surrounded by the field oxide film 12 is formed. Substrate 1
On the polysilicon layer 1 via the gate oxide film 14.
Gate electrode 2 in which silicon layer 6 and silicide layer 18 are sequentially stacked
0 is formed. Then, by implanting low-concentration impurity ions using the gate electrode 20 as a mask, the Si substrate 10 is implanted.
A low concentration impurity region 22 is formed on the surface.

Subsequently, a SiO ₂ film 24 as an etching stopper layer having a thickness of 20 to 50 nm is deposited on the entire surface of the substrate by using, for example, a CVD method. Thereafter, for example, P (Phosphor) is formed on this SiO ₂ film 24 by using, for example, a CVD method.
us: phosphorus (hereinafter referred to as “P-DPS (Phosphorus-D)”).
oped Polysilicon film) is deposited to a sufficient thickness. The P concentration in the P-DPS film 26 is, for example, 2 wt. % (See FIG. 1).

Next, the entire surface of the P-DPS film 26 is etched back to leave the P-DPS film 26 only on the side wall of the gate electrode 20 via the SiO ₂ film 24. Note that when the entire surface of the P-DPS film 26 is etched back, SiO
_{The two} films 24 function as an etching stopper layer. Thus, P via the SiO ₂ film 24 on the gate electrode 20 side wall
-Sidewall spacer 26 made of DPS26 film
a is formed (see FIG. 2).

Next, the gate electrode 20, the SiO ₂ film 24 on both side walls thereof, and the side wall spacers 26a are formed.
Is used as a mask, as shown by arrows in the figure,
A high-concentration impurity ion 28 is implanted into the substrate 10 to form a low-resistance high-concentration impurity region 28 on the surface of the Si substrate 10. Then, the high concentration impurity region 28 and the previously formed low concentration impurity region 22 constitute a source / drain region 30 having an LDD structure (see FIG. 3).

Next, the sidewall spacer 26a on the side wall of the gate electrode 20 is removed by isotropic etching. Also at this time, the underlying SiO ₂ film 24 is made of P-DPS.
It functions as an etching stopper layer for isotropic etching of the sidewall spacer 26a made of the 26 film. Thus, the source / drain region 30 having the LDD structure formed opposite to the surface of the Si substrate 10 and the channel region sandwiched between the two opposite source / drain regions 30 are formed via the gate oxide film 14. Then, a MOS transistor including the gate electrode 20 is formed (see FIG. 4).

Next, an SiN film 32 as an etching stopper layer is deposited on the entire surface of the substrate by using, for example, a CVD method, and further an interlayer insulating film 34 is formed on the SiN film 32.
Is deposited. Subsequently, using a lithography technique, an interlayer insulating film 34 and an SiN film 3 as an etching stopper layer are formed.
2 and the SiO ₂ film 24 are selectively etched to form a contact window 36 exposing the high-concentration impurity region 28 of the source / drain region 30. That is, after the selective etching of the interlayer insulating film 34 for opening the contact window 36 is once stopped by the SiN film 32, the exposed SiN film 32 is selectively removed by etching, and the exposed SiO ₂ film 24 is further removed. Is selectively removed by etching to form a contact window 36 (see FIG. 5).

As described above, according to the method of manufacturing the MOS transistor having the LDD structure according to the present embodiment, the gate electrode 2
0 through the SiO ₂ film 24 at a concentration of 2 wt. % Of P-DPS 26 film doped with P is formed on the Si substrate 10 using the gate electrode 20, the SiO ₂ film 24 and the sidewall spacer 26a on both side walls as masks. Is implanted to form the high-concentration impurity region 28 of the source / drain region 30 having the LDD structure, and then the side wall spacer 26a on the side wall of the gate electrode 20 is removed by isotropic etching. In the step of implanting high-concentration impurity ions for forming the high-concentration impurity region 28 of the drain region 30, for example, as in the sidewall spacer 26a on the side wall of the gate electrode 20 of the MOS transistor constituting the memory cell transistor of the DRAM. If no impurity ions are implanted Or a case where n-type or p-type impurity ions are implanted at a high concentration like a sidewall spacer 26a on the side wall of the gate electrode 20 of an N-channel MOS transistor or a P-channel MOS transistor forming a logic transistor. However, since P is highly doped in all of the sidewall spacers 26a in advance, whether or not impurity ions are implanted into the sidewall spacers 26a depending on the type of the MOS transistor, and whether the implanted impurity ions The etching rate of the sidewall spacer 26a is increased as a whole regardless of the type, dose of impurity ions, implantation energy of impurity ions, etc.
The difference in the etching rate between the sidewall spacer 26a of the transistor becomes small. Therefore, when the sidewall spacers 26a are removed by etching, the etching time can be shortened, and all the sidewall spacers 26a can be substantially uniformly removed under a predetermined isotropic etching condition, so that the specific Can be prevented from being left unetched on the sidewall spacer 26a. Therefore, it is possible to eliminate the risk that the etching residue of the sidewall spacer 26a on the side wall of the gate electrode 20 may cause an electrical short between contacts in a later process, thereby realizing good transistor characteristics.

Further, the respective sidewall spacers 26a of various MOS transistors and the underlying SiO ₂
The etching selectivity with the film 24 is also increased, and the sidewall spacers 26a of various MOS transistors are formed.
To become smaller difference in etching selectivity between the sidewall spacers 26a since the SiO ₂ film 24 underlying that is scraped more than necessary is suppressed in etching removal, locally SiO ₂ film 24 And the high concentration impurity region 28 of the source / drain region 30 of the LDD structure is exposed, and the exposed portion is prevented from being etched by isotropic etching of the sidewall spacer 26a to form a trench. be able to. Therefore, a MOS transistor having favorable transistor characteristics can be manufactured.

(Second Embodiment) FIGS. 6 to 9 are process cross-sectional views for explaining a method of manufacturing an MOS transistor having an LDD structure according to a second embodiment of the present invention. In each of the cross-sectional views, a transistor portion for forming a MOS transistor is shown on the left side, and a field portion for insulating the transistor portion is shown on the right side.
The same components as those of the MOS transistor shown in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof is omitted.

In the same manner as in the steps shown in FIGS. 1 to 3 in the first embodiment, the Si substrate 1
Field oxide film 12 for element isolation in the field portion of 0
To form a gate electrode 20 in which a polysilicon layer 16 and a silicide layer 18 are sequentially stacked on a Si substrate 10 of a transistor portion surrounded by the field oxide film 12 with a gate oxide film 14 interposed therebetween. This gate electrode 2
0 as a mask to implant S at a low concentration
A low-concentration impurity region 22 is formed on the surface of the i-substrate 10, an SiO ₂ film 24 is deposited as an etching stopper layer on the entire surface of the substrate, and a P ₂ film is formed on the side wall of the gate electrode 20 via the SiO ₂ film 24.
-Sidewall spacer 26 made of DPS26 film
is formed, and the gate electrode 20 and SiO on both side walls thereof are formed.
_{Using the two} films 24 and the sidewall spacers 26a as masks, high-concentration impurity ions are implanted into the Si substrate 10 as shown by arrows in the figure to form low-resistance high-concentration impurity regions 28 on the surface of the Si substrate 10. The high concentration impurity region 28 and the low concentration impurity region 22 previously formed
A source / drain region 30 having a DD structure is formed (FIG. 6).
reference).

Next, in an N ₂ (nitrogen) atmosphere,
Annealing is performed at a temperature of 800 ° C. for a time of 10 to 30 minutes. Thus, to recover the defects that occur during the SiO ₂ film 24 when the injected high-concentration impurity ions for forming a high-concentration impurity region 28 of the source / drain regions 30 in the preceding step, the SiO ₂ film 24 Decrease the etching rate (see FIG. 7).

Next, FIG. 4 in the first embodiment will be described.
The sidewall spacer 26a on the side wall of the gate electrode 20 is removed by isotropic etching in the same manner as shown in FIG. Also at this time, the SiO ₂ film 24 is made of P-DPS2.
Although the SiO ₂ film 24 functions as an etching stopper layer for isotropic etching of the side wall spacers 26a made of six films, the SiO ₂ film 24 recovers defects generated during high-concentration impurity ion implantation in the preceding annealing step, Since the etching rate is reduced, the etching selectivity between the sidewall spacer 26a and the SiO ₂ film 24 becomes larger than that in the first embodiment, and the etching selectivity of the sidewall spacer 26a with respect to the isotropic etching is reduced. The function as an etching stopper layer is exhibited more effectively than in the case of the first embodiment. Thus, the source / drain region 30 having the LDD structure formed opposite to the surface of the Si substrate 10 and the channel region sandwiched between the two opposite source / drain regions 30 are formed via the gate oxide film 14. Gate electrode 20
(FIG. 8)
reference).

Next, FIG. 5 in the first embodiment will be described.
A SiN film 32 as an etching stopper layer is deposited on the entire surface of the substrate in the same manner as shown in FIG.
After depositing an interlayer insulating film 34 thereon, the interlayer insulating film 34, S
The iN film 32 and the SiO ₂ film 24 are selectively etched to form the high-concentration impurity regions 2 in the source / drain regions 30.
A contact window 36 for exposing 8 is formed (see FIG. 9).

As described above, according to the method of manufacturing the MOS transistor having the LDD structure according to the present embodiment, the gate electrode 2
0 and implanting high-concentration impurity ions of the Si substrate 10 of the SiO ₂ film 24 and the side wall spacers 26a of the side walls as a mask to form high concentration impurity regions 28 of low resistance Si substrate 10 surface, Before the sidewall spacer 26a on the side wall of the gate electrode 20 is removed by isotropic etching, an annealing process is performed in an N ₂ atmosphere to form a base of the sidewall spacer 26a by implanting high-concentration impurity ions. The defect generated in the SiO ₂ film 24 is recovered and this S 2
Since the etching rate of the iO ₂ film 24 becomes lower, the etching selectivity between the sidewall spacers 26a of the various MOS transistors and the underlying SiO ₂ film 24 is further higher than in the case of the first embodiment. for larger, and more effectively prevent the SiO ₂ film 24 underlying abraded more than necessary when the sidewall spacer 26a is removed by etching, the SiO ₂ film 24
Is locally eliminated, and the margin for exposing the high-concentration impurity region 28 of the source / drain region 30 is further increased, and the exposed portion is etched by isotropic etching for the sidewall spacer 26a to form a groove. Such a situation can be more effectively prevented. Therefore, a MOS transistor having favorable transistor characteristics can be manufactured.

In the first and second embodiments, the sidewall spacers 26a made of the P-DPS 26 film doped with P at a high concentration are formed on the side walls of the gate electrode 20 via the SiO ₂ film 24, respectively. Although the P-DPS 26 film is formed, for example, an amorphous silicon film in which P is highly doped, that is, P-DAS
(Phosphorus-Doped Amorphous Silicon) may be formed as a sidewall spacer.

In place of P, the same n-type impurities such as As (Arsenic; arsenic) and p-type impurities such as B (Boron; boron) may be used as impurities for doping a polysilicon film or an amorphous silicon film at a high concentration. May be doped at a high concentration.

[0056]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the following effects can be obtained. That is, according to the semiconductor device of the first aspect, the sidewall spacer made of the polysilicon film doped with a predetermined impurity is formed on the side wall of the gate electrode with the second insulating film interposed therebetween.
Whether or not impurity ions are implanted in the step of implanting high-concentration impurity ions for forming the high-concentration impurity regions of the source / drain regions having the D structure; type of implanted impurity ions; dose amount of impurity ions; Irrespective of the implantation energy, etc., the etching rate of the sidewall spacer is increased as a whole, and the difference in etching rate between the plurality of sidewall spacers is reduced. The etching time can be shortened, and all the sidewall spacers are almost uniformly removed under predetermined isotropic etching conditions, thereby preventing the occurrence of etching residue of a specific sidewall spacer. Can be.

Further, the etching selectivity between the sidewall spacer and the underlying second insulating film is increased as a whole, and the difference in etching selectivity between the plurality of sidewall spacers is reduced. Since the underlying second insulating film is prevented from being unnecessarily shaved when the spacer is removed by etching, the second insulating film locally disappears and the high-concentration impurity region on the surface of the semiconductor substrate is exposed. Further, it is possible to prevent a situation in which the exposed portion is etched by isotropic etching with respect to the sidewall spacer and a groove is dug.

According to the method of manufacturing a semiconductor device of the present invention, the sidewall spacer made of the amorphous silicon film doped with a predetermined impurity is formed on the side wall of the gate electrode via the second insulating film. That is, in the method of manufacturing a semiconductor device according to claim 1, an amorphous silicon film doped with a predetermined impurity is used instead of the polysilicon film doped with a predetermined impurity used as a material of the sidewall spacer. By using it as a material of the sidewall spacer, the same effect as in the method of manufacturing a semiconductor device according to claim 1 can be obtained.

According to the method of manufacturing a semiconductor device of the third aspect, in the method of manufacturing a semiconductor device of the first or second aspect, the second step is performed by using the gate electrode and the sidewall spacer as a mask. After the impurity ions are implanted and before the sidewall spacers are removed by etching, a step of performing an annealing process is provided so that the second impurity ions are implanted into the second insulating film underlying the sidewall spacers. Since the generated defect is recovered and the etching rate of the second insulating film becomes lower, the etching selectivity between the side wall spacer and the underlying second insulating film is further increased as a whole. More effectively prevent the underlying second insulating film from being unnecessarily shaved when the spacer is removed by etching. In this case, the margin for exposing the source / drain region is further increased by locally removing the second insulating film, and the exposed portion is etched by isotropic etching with respect to the sidewall spacer to form a trench. Can be prevented more effectively.

As described above, the method for manufacturing a semiconductor device according to the present invention makes it possible to easily manufacture a field-effect transistor having good transistor characteristics and element isolation characteristics.

[Brief description of the drawings]

FIG. 1 shows an M of an LDD structure according to a first embodiment of the present invention.
FIG. 9 is a process sectional view (part 1) for describing the method for manufacturing the OS transistor.

FIG. 2 is a diagram showing an M of the LDD structure according to the first embodiment of the present invention;
FIG. 9 is a process sectional view (part 2) for describing the method for manufacturing the OS transistor.

FIG. 3 is a diagram showing an M of the LDD structure according to the first embodiment of the present invention;
FIG. 11 is a process sectional view (part 3) for describing the method for manufacturing the OS transistor.

FIG. 4 is a diagram showing an M of the LDD structure according to the first embodiment of the present invention;
FIG. 14 is a process sectional view (part 4) for describing the method for manufacturing the OS transistor.

FIG. 5 is a diagram showing an M of the LDD structure according to the first embodiment of the present invention;
FIG. 21 is a process sectional view (part 5) for describing the method for manufacturing the OS transistor.

FIG. 6 shows the M of the LDD structure according to the second embodiment of the present invention.
FIG. 9 is a process sectional view (part 1) for describing the method for manufacturing the OS transistor.

FIG. 7 shows an M of the LDD structure according to the second embodiment of the present invention.
FIG. 9 is a process sectional view (part 2) for describing the method for manufacturing the OS transistor.

FIG. 8 is a diagram showing an M of the LDD structure according to the second embodiment of the present invention;
FIG. 11 is a process sectional view (part 3) for describing the method for manufacturing the OS transistor.

FIG. 9 is a diagram showing an M of the LDD structure according to the second embodiment of the present invention;
FIG. 14 is a process sectional view (part 4) for describing the method for manufacturing the OS transistor.

FIG. 10 is a process cross-sectional view (part 1) for describing a method for manufacturing a conventional MOS transistor having an LDD structure.

FIG. 11 is a process sectional view (part 2) for explaining the method for manufacturing the conventional MOS transistor having the LDD structure.

FIG. 12 is a process sectional view (part 3) for describing a method for manufacturing a conventional MOS transistor having an LDD structure.

FIG. 13 is a process sectional view (part 4) for explaining the method for manufacturing the conventional MOS transistor having the LDD structure.

FIG. 14 is a process sectional view (part 1) for describing another method of manufacturing a conventional MOS transistor having an LDD structure.

FIG. 15 is a process sectional view (part 2) for describing another method of manufacturing a conventional MOS transistor having an LDD structure.

FIG. 16 is a process sectional view (part 3) for describing another method of manufacturing the conventional MOS transistor having the LDD structure.

FIG. 17 is a process sectional view (part 4) for explaining another method of manufacturing the conventional MOS transistor having the LDD structure.

FIG. 18 is a process sectional view (part 5) for describing another method of manufacturing the conventional MOS transistor having the LDD structure.

FIG. 19 shows the relationship between the dose of impurity ions implanted into the polysilicon film and the SiO ₂ film and the polysilicon film and S
4 is a graph showing a relationship between an etching rate of an iO ₂ film and a relationship between an etching selectivity between a polysilicon film and a SiO ₂ film.

20 shows a relationship between the etching selectivity of the polysilicon film and the SiO ₂ film relationship etch rate of the polysilicon film and the SiO ₂ film to the energy when implanting impurity ions into and polysilicon film and SiO ₂ film It is a graph.

21A is a process cross-sectional view showing a state of etching of a sidewall spacer into which impurity ions have not been implanted, and FIG. 21B is a sectional view of the sidewall spacer into which n-type impurity ions have been implanted at a high concentration; FIG. 4C is a process sectional view showing the state of etching, and FIG. 4C is a process sectional view showing the state of etching of the sidewall spacer into which p-type impurity ions are implanted at a high concentration.

[Explanation of symbols]

10 ... Si substrate, 12 ... Field oxide film, 14 ...
... gate oxide film, 16 ...... polysilicon layer, 18 ...... silicide layer, 20 ...... gate electrode, 22 ...... low concentration impurity regions, 24 ...... SiO ₂ film, 26 ...... P-DPS film,
26a ... sidewall spacer, 28 ... high concentration impurity region, 30 ... source / drain region, 32 ...
SiN, 34 ... interlayer insulating film, 36 ... contact window.

Claims (3)

[Claims] A first step of implanting a first impurity ion into the semiconductor substrate using a gate electrode formed on the semiconductor substrate via a first insulating film as a mask; A second step of depositing a film, and after depositing a polysilicon film doped with a predetermined impurity on the second insulating film, etching back the polysilicon layer to form a second layer on the side wall of the gate electrode. A third step of forming a sidewall spacer made of the polysilicon film via the second insulating film; and implanting second impurity ions into the semiconductor substrate using the gate electrode and the sidewall spacer as a mask. A fourth step of selectively etching away the sidewall spacers using the second insulating film as an etching stopper layer. The method of manufacturing a semiconductor device according to claim and. 2. A first step of implanting first impurity ions into the semiconductor substrate using a gate electrode formed on the semiconductor substrate via a first insulating film as a mask, and a second insulating step over the entire surface of the base. A second step of depositing a film, and after depositing an amorphous silicon film doped with a predetermined impurity on the second insulating film, etching back the amorphous silicon film to form a second layer on the side wall of the gate electrode. A third step of forming a sidewall spacer made of the amorphous silicon film via the second insulating film; and implanting second impurity ions into the semiconductor substrate using the gate electrode and the sidewall spacer as a mask. A fourth step of selectively etching and removing the sidewall spacers by using the second insulating film as an etching stopper layer. The method of manufacturing a semiconductor device, characterized in that it comprises a fifth step. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing an annealing process after the fourth step and before the fifth step. Device manufacturing method.