JP2000200904A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an MOS FET for sufficiently reducing the trigger of a parasitic transistor, and for reducing the impurity concentration of a channel region. SOLUTION: N-type impurity is injected to one part of the surface of a high concentration (p)-type region 15 so that a low concentration (p) type region 19 can be formed in the part, and an (n)-type source region is formed in the high concentration (p) type region 15 so as to be made adjacent to the low concentration (p)-type region 19. Thus, the concentration of the impurity in the low concentration (p)-type region being a channel can be reduced, and the breakdown voltage of the parasitic transistor formed of an epitaxial layer 13, high concentration (p)-type region 15, and (n) type source region 19. That is, the threshold voltage of an MOS FET 1 can be decreased, and the L load resistant quantity and breakdown voltage or the like can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which an impurity concentration in only a channel region is reduced to improve an L load resistance and a breakdown voltage.

[0002]

2. Description of the Related Art MOS FET which is a conventional semiconductor device
FIG. 6 shows a cross-sectional view of a main part of FIG. The MOSFET 100 includes a substrate 101, an epitaxial layer 103, a p-type region 105,
It has an n-type region 107, an oxide film 109, a gate electrode 111, a protective film 113, and an aluminum electrode layer 115. In addition,
The MOS FET 100 is an n-type.

A MOS FET 100 has an n-type region 10
7. The p-type region 105B and the epitaxial layer 103 form an npn-type parasitic transistor. The n-type region 107 corresponds to the emitter, the p-type region 105B corresponds to the base, and the epitaxial layer 103 corresponds to the collector.

The parasitic transistor is a MOS FET
1 lowers the L load tolerance and breakdown voltage. Therefore, in order to operate the MOS FET 1 correctly, it is necessary to prevent the parasitic transistor from being triggered.

A common way to avoid triggering a parasitic transistor is to short the emitter and base of the parasitic transistor. By short-circuiting the emitter and the base in this way, the breakdown voltage between the emitter and the collector becomes the breakdown voltage of the parasitic transistor.

However, when there is a large difference between the concentration of the emitter and the concentration of the base, that is, when there is a large difference between the concentration of the n-type region 107 and the concentration of the p-type region 105B,
The short circuit between the emitter and the base as described above makes it impossible to suppress the trigger of the parasitic transistor. Therefore, p
In order to increase the concentration of the mold region 105B,
It is necessary to form T100.

On the other hand, as the concentration of the channel region increases, the value of the threshold voltage increases. Therefore, the concentration of the channel region must not be increased.

In order to satisfy the condition that the concentration of the p-type region 105B is high and the concentration of the channel region is low, the MOS FET 100 is formed by the following method.

A method for manufacturing a MOS FET will be described with reference to FIGS. Epitaxial layer 1 on substrate 101
Grow 03. An oxide layer 161 of several thousand angstroms is formed on the epitaxial layer 103. Thereafter, after the oxide layer 161 is patterned, etching is performed to provide an opening in a predetermined portion.

A high concentration p-type impurity (acceptor) is ion-implanted to perform thermal diffusion. Thus, a high-concentration p-type region 125 is formed (see FIG. 7A). Then, the remaining oxide film 161 is removed.

Next, an oxide film 109 of several hundreds to several thousand angstroms is newly formed. On the oxide layer 109, a polysilicon layer is further formed. After patterning the polysilicon, etching is performed. Thus, a gate electrode 111 is formed (see FIG. 7B).

Then, using the formed gate electrode 111 as a mask, low-concentration p-type impurities (acceptors) are ion-implanted and thermally diffused. Thus, a low concentration p-type region 135 is formed (see FIG. 7B). The high-concentration p-type region 125 formed previously and the low-concentration p-type region 135 formed this time are integrated to form the p-type region 105.

Next, after a resist 153 is applied, patterning is performed by photolithography or the like to form an n-type region 10.
7 are formed (see FIG. 7C).
Then, high-concentration n-type impurities (donors) are ion-implanted and then thermally diffused to form n-type regions 107 at predetermined locations. Then, the resist 153 is peeled off (FIG. 8Α).
reference).

Next, a protective layer 113 is formed. Finally,
Aluminum is deposited to form an aluminum electrode layer 115 (see FIG. 8B).

[0015]

SUMMARY OF THE INVENTION Conventional MOS FET
100 has the following problems. p-type region 105B
In order to satisfy the condition that the concentration of the channel region is high and the concentration of the channel region is low, first, a high-concentration p-type region 125 having a high impurity concentration is formed (see FIG. 7A), and then a low-concentration p-type region 125 having a low impurity concentration is formed. 135 (see FIG. 7B).

When forming a low concentration p-type region, a thermal diffusion step is performed after ion implantation of a p-type impurity (acceptor). At this time, the previously formed high-concentration p-type region 1
25 are affected by the thermal diffusion, and the high-concentration p-type region 1
25 diffuses further. As a result of the diffusion, the high-concentration p-type region 1
When 25 reaches the channel region, the impurity concentration of the channel region increases.

That is, it is necessary to control the conditions such as the impurity concentration and the diffusion time of each region so that the diffusion of the high-concentration p-type region reaches just below the n-type region 107. However, it is very difficult to perform this control.

Accordingly, an object of the present invention is to provide a MOS FET capable of reducing the impurity concentration of a channel region while sufficiently suppressing a trigger of a parasitic transistor.

[0019]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a second conductive type high-concentration impurity-containing region in a first conductive type impurity-containing layer; A second conductivity type low-concentration impurity-containing region is formed in the portion by implanting a first conductivity-type impurity into a portion of the surface in the conductivity-type high-concentration impurity-containing region.
A first conductive type impurity-containing region is formed in the second conductive type high-concentration impurity-containing region so as to be adjacent to the conductive type low-concentration impurity-containing region. Thereby, the second-conductivity-type low-concentration impurity-containing region existing adjacent to the first-conductivity-type impurity-containing region can be formed in the second-conductivity-type high-concentration impurity-containing region.

Therefore, the impurity concentration of the low-concentration impurity-containing region of the second conductivity type can be reduced, and
The breakdown voltage of a parasitic transistor formed by the first conductive type impurity-containing layer, the second conductive type high-concentration impurity-containing region, and the first conductive type impurity-containing region can be increased. That is, the threshold voltage of the semiconductor device according to the present invention can be reduced, and the L load tolerance, breakdown voltage, and the like can be improved.

Here, the correspondence between the respective components according to claim 1 and the respective components of the MOS FET 1 according to the present embodiment will be described. The first conductivity type impurity-containing layer is in the epitaxial layer 13, the second conductivity type high-concentration impurity-containing region is in the high-concentration p-type region, and the second conductivity-type low-concentration impurity-containing region is in the low-concentration p-type region 19. , The impurity region of the first conductivity type is n
Each corresponds to the mold source region 17. Although the n-type is shown as the MOS FET 1 according to the present embodiment,
It may be a type.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a high-concentration impurity-containing region of a second conductivity type is formed in a first-conductivity-type impurity-containing layer, Forming a first conductivity type impurity-containing region, and implanting the first conductivity type impurity into the second conductivity type high-concentration impurity-containing region so as to be adjacent to the first conductivity type impurity-containing region. A low-concentration impurity-containing region of the second conductivity type is formed. Thereby, the second-conductivity-type low-concentration impurity-containing region existing adjacent to the first-conductivity-type impurity-containing region can be formed in the second-conductivity-type high-concentration impurity-containing region.

Therefore, the impurity concentration of the low-concentration impurity-containing region of the second conductivity type can be reduced, and
The breakdown voltage of a parasitic transistor formed by the first conductive type impurity-containing layer, the second conductive type high-concentration impurity-containing region, and the first conductive type impurity-containing region can be increased. That is, the threshold voltage of the semiconductor device according to the present invention can be reduced, and the L load tolerance, breakdown voltage, and the like can be improved.

This forms a second conductivity type low-concentration impurity-containing region.

Here, the correspondence between the respective components according to claim 2 and the respective components of the MOS FET 1 according to the present embodiment will be described. The first conductivity type impurity-containing layer is in the epitaxial layer 13, the second conductivity type high-concentration impurity-containing region is in the high-concentration p-type region, and the second conductivity-type low-concentration impurity-containing region is in the low-concentration p-type region 19. , The impurity region of the first conductivity type is n
Each corresponds to the mold source region 17. Although the n-type is shown as the MOS FET 1 according to the present embodiment,
It may be a type.

In the semiconductor device according to the third aspect and the MOS FET according to the fourth aspect, the impurity concentration in the channel region and the vicinity of the channel region is the second conductivity type impurity-containing region other than the vicinity of the channel region and the channel region. Lower than the impurity concentration. Thereby, the impurity concentration of only the channel region and the vicinity thereof can be made lower than the impurity concentration of the impurity-containing region of the second conductivity type.

Therefore, the impurity concentration of the channel region can be reduced, and a parasitic transistor formed of the first conductive type impurity-containing layer, the second conductive type impurity-containing region and the first conductive type impurity-containing region. Can have a high breakdown voltage. That is, the semiconductor device according to claim 1 and the MOSF according to claim 2
The threshold voltage of ET can be lowered,
It is possible to improve the L load resistance, breakdown voltage, and the like.

Here, the correspondence between the components according to claim 3 and the respective components of the MOS FET 1 according to the present embodiment will be described. The impurity-containing layer of the first conductivity type is in the epitaxial layer 13, the impurity-containing region of the second conductivity type is in the high-concentration p-type region 15, the impurity-containing region of the first conductivity type is in the n-type source region 17, and the channel region is Each corresponds to the low concentration p-type region 19. The MOS FET according to the present embodiment
Although n-type is shown as 1, it may be p-type.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described below using an n-type MOS FET as an example. FIG. 1 shows n
FIG. 3 is a cross-sectional view of a main part of a type MOS FET1. n-type MOS
The FET 1 includes a substrate 11, an epitaxial layer 13, a high-concentration p-type region 15, an n-type source region 17, and a low-concentration p-type region 1.
9, a high-concentration n-type region 21, a gate oxide film 23, a gate electrode 25, a protective film 27, and a source electrode 29.

In the MOS FET 1, the high-concentration p-type region 1
5 is formed on the epitaxial layer 13. The n-type source region 17 is formed in the high-concentration p-type region 15.

The low-concentration p-type region 19 is formed in the high-concentration p-type region, and depends on whether a voltage is applied to the gate electrode 25 or not.
7 is formed in a region through which a current flowing therethrough passes. The impurity concentration in the vicinity of the low-concentration p-type region 19 and the low-concentration p-type region 19 is lower than the impurity concentration of the high-concentration p-type region 15 other than the vicinity of the low-concentration p-type region 19 and the low-concentration p-type region 19. .

Thus, the MOS FET 1 can reduce the impurity concentration of the low-concentration p-type region 19 and reduce the parasitic transistor formed by the epitaxial bath 13, the high-concentration p-type region 15 and the n-type source region 17. The breakdown voltage can be increased. That is,
The threshold voltage of the MOS FET 1 can be lowered, and the L load tolerance, breakdown voltage, and the like can be improved.

Next, a method of manufacturing the MOS FET 1 will be described with reference to FIG.
This will be described with reference to FIG. First, the epitaxial layer 13 is formed on the substrate 11. After forming the oxide film 51 on the epitaxial layer 13, the oxide film 51 is patterned. Then, ions of a p-type impurity are implanted. Oxide film 51
After the removal, diffusion is performed. Thus, a central p-type region 151 is formed (see FIG. 2A).

A new resist film 53 is formed and predetermined patterning is performed. Using the resist film 55 as a mask, p
Ion implantation of type impurities is performed. After removing the resist film 53, diffusion is performed. Thus, a channel p-type region 152 including a channel region is formed.

At this time, the impurity concentration of the channel p-type region 152 is set higher than the concentration used in the conventional MOS FET. The high-concentration p-type region 15 is formed by the central p-type region 151 and the channel p-type region 152.

Next, in order to reduce the impurity concentration in the channel region of the high-concentration p-type region 15, a resist film 55 is formed so that ions can be implanted only into the channel region (see FIG. 3A). Using the resist film 55 as a mask, an n-type impurity is ion-implanted. After removing the resist film 55, diffusion is performed.

Thus, a low-concentration p-type region 19 is formed in the high-concentration p-type region 15. Further, a high-concentration n-type region 21 is formed in epitaxial layer 13. in this way,
After forming the p-type impurity region, an n-type impurity is implanted so that the channel region has a desired resistance value.

Next, a resist film 57 is formed to form the n-type source region 17 (see FIG. 3C). Then, an n-type impurity is ion-implanted and an annealing process is performed.
Thus, an n-type source region 17 is formed (FIG. 4A).
reference).

After forming oxide film 59, a polycrystalline silicon film 61 is formed thereon. Further, a resist film 63 is formed on the polycrystalline silicon film 61. The resist film 63 is patterned into a predetermined shape using photolithography or the like (see FIG. 4B).

Etching is performed using the patterned resist film 63 as a mask. Thereby, the gate electrode 25
To form

Thereafter, a protective layer 65 is formed by CVD or the like (see FIG. 5A). Then, the n-type source region 17
Is formed by etching or the like.
Thereby, oxide film 59 is etched, and gate oxide film 23 and protective film 27 are formed. Finally, aluminum is deposited to form a source electrode 29.

As described above, in this embodiment, the n-type impurity is implanted into a part of the surface in the high-concentration p-type region 15 to form the low-concentration p-type region 19 in the part, and the low-concentration p-type region 19 is formed. An n-type source region is formed in the high-concentration p-type region 15 so as to be adjacent to the region 19. Thus, the low-concentration p-type region 17 existing adjacent to the n-type source region 19 can be formed in the high-concentration p-type region 15.

Therefore, the impurity concentration of the low-concentration p-type region can be reduced, and the epitaxial layer 1
3. The breakdown voltage of the parasitic transistor formed by the high-concentration p-type region 15 and the n-type source region 19 can be increased. That is, the threshold voltage of the MOS FET 1 can be lowered, and the L load withstand capability,
The breakdown voltage and the like can be improved.

[Other Embodiments] In the above embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type is p-type, and the second conductivity type is p-type. It may be an n-type.

Further, in the above-described embodiment, the central portion p
Although the high-concentration p-type region 15 is formed by forming the channel p-type region 152 after forming the mold region 151, the high-concentration p-type region may be formed by one ion implantation. .

Further, in the above-described embodiment, the source electrode 29 is formed of aluminum. However, the present invention is not limited to this as long as it can be used as an electrode material. For example, copper may be used.

Further, in the above-described embodiment, the n-type source region 17 is formed after the n-type impurity is ion-implanted to form the low-concentration p-type region 19 in the high-concentration p-type region 15. However, first, after the n-type source region 17 is formed at a predetermined location by implanting n-type impurity ions or the like,
A low-concentration p-type region may be formed by implanting an n-type impurity or the like into a portion serving as a channel.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view of a main part of the OS FET1.

FIG. 2 is a diagram for explaining a method of manufacturing the MOS FET 1 in FIG.

FIG. 3 is a diagram for explaining a method of manufacturing the MOS FET 1 in FIG.

FIG. 4 is a diagram for explaining a method of manufacturing the MOS FET 1 in FIG.

FIG. 5 is a diagram for explaining the method for manufacturing the MOS FET1 in FIG.

FIG. 6 is a cross-sectional view of a main part of a conventional MOS FET 100.

FIG. 7 is a view for explaining the method for manufacturing the MOS FET 100 in FIG.

FIG. 8 is a drawing for explaining the method for manufacturing the MOS FET 100 in FIG.

[Explanation of symbols]

 1... MOS FET 13... Epitaxial layer 15... High-concentration p-type region 17... N-type source region 19. .... Gate electrodes

Claims (4)

[Claims] A second conductive type high-concentration impurity-containing region formed in the first conductive-type impurity-containing layer; and a first conductive type high-concentration impurity-containing region formed on a portion of a surface of the second conductive type high-concentration impurity-containing region. Forming a second conductive type low-concentration impurity-containing region in the portion by injecting an impurity, wherein the second conductive type high-concentration impurity-containing region is adjacent to the second conductive-type low-concentration impurity-containing region; Forming an impurity-containing region of the first conductivity type in the region. 2. A high-concentration impurity-containing region of a second conductivity type is formed in an impurity-containing layer of a first conductivity type, and an impurity-containing region of a first conductivity type is formed in the high-concentration impurity-containing region of the second conductivity type. Forming a second conductive type low-concentration impurity by implanting a first conductive type impurity into the second conductive type high-concentration impurity-containing region so as to be adjacent to the first conductive type impurity-containing region; A method for manufacturing a semiconductor device, comprising: forming a content region. 3. An impurity-containing layer of a first conductivity type, an impurity-containing region of a second conductivity type formed on the impurity-containing layer of the first conductivity type, and a second impurity-containing region formed on the impurity-containing region of the second conductivity type. An impurity-containing region of one conductivity type; a gate electrode formed on the impurity-containing region of the second conductivity type; formed in the impurity-containing region of the second conductivity type;
A channel region formed in a region through which a current flows between the first conductivity type impurity-containing region and the first conductivity type impurity-containing layer depending on whether a voltage is applied to the gate electrode. In the device, the impurity concentration of the channel region and the vicinity of the channel region is lower than the impurity concentration of the second conductivity type impurity-containing region other than the vicinity of the channel region and the channel region. . 4. The semiconductor device according to claim 3, wherein said semiconductor device is a MOS FET.