JP2000200973A - Low-temperature burning ceramic circuit substrate - Google Patents
Low-temperature burning ceramic circuit substrateInfo
- Publication number
- JP2000200973A JP2000200973A JP11001370A JP137099A JP2000200973A JP 2000200973 A JP2000200973 A JP 2000200973A JP 11001370 A JP11001370 A JP 11001370A JP 137099 A JP137099 A JP 137099A JP 2000200973 A JP2000200973 A JP 2000200973A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- low
- via conductor
- substrate
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、基板表面に表層導
体パターンをフォトリソグラフィ法等の湿式パターニン
グ法で形成した低温焼成セラミック回路基板に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-temperature fired ceramic circuit board having a surface conductor pattern formed on a substrate surface by a wet patterning method such as a photolithography method.
【0002】[0002]
【従来の技術】800〜1000℃で焼成する低温焼成
セラミック回路基板は、セラミックと同時焼成する内層
導体やビア導体として、低抵抗、低融点の金属(Ag
系、Au系、Cu系等)を使用でき、また、セラミック
の誘電率が低いという利点があり、近年の信号処理の高
速化に対応できるセラミック回路基板として知られてい
る。この低温焼成セラミック回路基板においても、近年
の高密度実装・小型化の要求を満たすために、基板内層
にコンデンサや抵抗体を内蔵させたり、基板表面の表層
導体パターンをフォトリソグラフィ法で形成してファイ
ンパターン化したものがある。2. Description of the Related Art A low-temperature fired ceramic circuit board fired at 800 to 1000 ° C. is a low-resistance, low-melting-point metal (Ag) used as an inner conductor and a via conductor that are fired simultaneously with ceramic.
System, an Au system, a Cu system, etc.), and has the advantage that the dielectric constant of the ceramic is low, and is known as a ceramic circuit board which can cope with recent high-speed signal processing. In order to meet the recent demand for high-density packaging and miniaturization, this low-temperature fired ceramic circuit board also incorporates a capacitor or resistor in the inner layer of the board, or forms a surface conductor pattern on the surface of the board by photolithography. Some have fine patterns.
【0003】[0003]
【発明が解決しようとする課題】ところで、ビア導体と
セラミック層との熱膨張率の差によりセラミック層にク
ラックが生じることを防止するため、ビア導体は、導体
粒子間の空隙をある程度大きく(緻密度を粗く)するこ
とで、セラミック層との熱膨張率の差を吸収するように
している。By the way, in order to prevent the ceramic layer from cracking due to the difference in the coefficient of thermal expansion between the via conductor and the ceramic layer, the via conductor has a relatively large gap between the conductive particles (density). The degree of thermal expansion is made coarse to absorb the difference in the coefficient of thermal expansion from the ceramic layer.
【0004】しかし、表層導体パターンをフォトリソグ
ラフィ法で形成する際に、露光後の現像工程で、基板表
面が現像液にさらされるため、基板表面に露出するビア
導体の導体粒子間の微細空隙から水分が浸入して、その
水分が内蔵コンデンサや内蔵抵抗体に浸入し、その水分
中のイオン(Na+ 、K+ 等)が内蔵コンデンサや内蔵
抵抗体に含まれた状態となる。この状態で、後焼成する
と、ショート等の電気的不具合が発生することがあり、
これが歩留り低下、信頼性低下を招く一因となってい
た。However, when the surface conductor pattern is formed by the photolithography method, the substrate surface is exposed to a developing solution in a development step after exposure. When water enters, the water penetrates into the built-in capacitor or the built-in resistor, and ions (Na + , K +, etc.) in the water are contained in the built-in capacitor or the built-in resistor. If post-baking is performed in this state, electrical defects such as short circuits may occur,
This has been one of the causes of lower yield and lower reliability.
【0005】本発明はこのような事情を考慮してなされ
たものであり、従ってその目的は、基板表層のビア導体
からの水分や湿気の浸入によるショート等の電気的不具
合を防止でき、歩留り向上、信頼性向上を実現できる低
温焼成セラミック回路基板を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and an object of the present invention is to prevent an electrical defect such as a short circuit due to intrusion of moisture or moisture from via conductors on the surface of a substrate, thereby improving the yield. Another object of the present invention is to provide a low-temperature fired ceramic circuit board capable of improving reliability.
【0006】[0006]
【課題を解決するための手段】上記目的を達成するため
に、本発明の低温焼成セラミック回路基板は、基板表層
に位置するAg系のビア導体の少なくとも表面部を他の
部分よりも緻密に形成したものである(請求項1)。こ
のように、基板表層のビア導体の少なくとも表面部の緻
密度を高めると、その部分の導体粒子間の空隙が小さく
なり、表層導体パターンをフォトリソグラフィ法等の湿
式パターニング法で形成しても、水分が基板表層のビア
導体に浸入しにくくなり、基板内層への水分の浸入が防
止される。この場合、基板全体のビア導体を緻密化する
のではなく、水分の浸入防止に必要最小限の基板表層の
ビア導体又はその表面部のみを緻密化するだけであるか
ら、他の層のビア導体は従来同様の比較的粗い緻密度に
して、導体粒子間の空隙をある程度大きくすることがで
きる。これにより、ビア導体とセラミック層との熱膨張
率の差を吸収することができ、低温焼成セラミック層の
ビア導体周辺にクラックが生じることを防止できる。In order to achieve the above object, in a low-temperature fired ceramic circuit board according to the present invention, at least a surface portion of an Ag-based via conductor located on a surface layer of a substrate is formed more densely than other portions. (Claim 1). As described above, when the denseness of at least the surface portion of the via conductor on the substrate surface is increased, the gap between the conductive particles in that portion is reduced, and even if the surface layer conductive pattern is formed by a wet patterning method such as a photolithography method, Moisture is less likely to penetrate into the via conductors on the surface layer of the substrate, preventing the penetration of moisture into the inner layer of the substrate. In this case, the via conductors on the entire substrate are not densified, but only the via conductors on the surface layer of the substrate or only the surface portion of the via conductors necessary for preventing the penetration of moisture are densified. Can be made relatively coarse and dense as in the prior art, and the gap between the conductive particles can be increased to some extent. This makes it possible to absorb the difference in the coefficient of thermal expansion between the via conductor and the ceramic layer, thereby preventing the low-temperature fired ceramic layer from being cracked around the via conductor.
【0007】上述したように、本発明の低温焼成セラミ
ック回路基板は、基板表層のビア導体に水分が浸入しに
くいため、請求項2のように、基板内層に内蔵コンデン
サと内蔵抵抗体の少なくとも一方を形成しても、内蔵コ
ンデンサや内蔵抵抗体への水分の浸入が防止され、ショ
ート等の電気的不具合が防止される。As described above, in the low-temperature fired ceramic circuit board of the present invention, since it is difficult for moisture to penetrate into the via conductor on the surface of the board, at least one of the built-in capacitor and the built-in resistor is provided in the inner layer of the board. Is formed, the penetration of moisture into the built-in capacitor and the built-in resistor is prevented, and electrical problems such as short-circuit are prevented.
【0008】ここで、ビア導体を緻密化する方法として
は、例えばAg系導体ペーストに添加物を混合して緻密
化しても良いが、請求項3のように、Ag系導体ペース
トに含まれる導体粒子の粒径を小さくすることで、ビア
導体を緻密化するようにしても良い。このようにすれ
ば、導体粒子の粒径を調整することで、ビア導体の緻密
度を容易に調整することができる。Here, as a method of densifying the via conductor, for example, an Ag-based conductor paste may be mixed with an additive to densify the via conductor, but the conductor contained in the Ag-based conductor paste may be densified. The via conductor may be densified by reducing the particle size of the particles. In this case, the fineness of the via conductor can be easily adjusted by adjusting the particle size of the conductive particles.
【0009】また、請求項4のように、ビア導体の緻密
な部分を、他の部分のビア導体と共に低温焼成セラミッ
ク層と同時焼成するようにしても良い。このようにすれ
ば、焼成工程が増加せず、生産性を低下させずに済む。Further, the dense portion of the via conductor may be co-fired with the low-temperature fired ceramic layer together with the other portion of the via conductor. In this case, the number of firing steps does not increase, and the productivity does not decrease.
【0010】或は、請求項5のように、ビア導体の緻密
な部分を、先に焼成されたビア導体上にAg系導体ペー
ストを印刷して後焼成するようにしても良い。例えば、
焼成後の基板表面に表層導体や表層抵抗体等を印刷して
後焼成する場合には、表層導体等を後焼成する工程で、
同時に、ビア導体の緻密な部分も後焼成することがで
き、焼成工程が増加せず、生産性を低下させずに済む。[0010] Alternatively, the dense portion of the via conductor may be post-fired by printing an Ag-based conductor paste on the previously fired via conductor. For example,
When printing a surface conductor or a surface resistor on the surface of the fired substrate and performing post-firing, in the step of post-firing the surface conductor or the like,
At the same time, the dense portion of the via conductor can be post-fired, so that the number of firing steps does not increase and the productivity does not decrease.
【0011】[0011]
【発明の実施の形態】[実施形態(1)]以下、本発明
の実施形態(1)を図1に基づいて説明する。低温焼成
セラミック層11は、CaO−Al2 O3 −SiO2 −
B2 O3 系ガラス粉末:50〜65重量%(好ましくは
60重量%)とAl2 O3 粉末:50〜35重量%(好
ましくは40重量%)との混合物からなるグリーンシー
トにより形成されている。低温焼成セラミックは、上記
の系の他に、MgO−Al2 O3 −SiO2 −B2O3
系のガラス粉末とAl2 O3 粉末との混合物、又は、S
iO2 −B2 O3 系のガラス粉末とAl2 O3 粉末との
混合物等、800〜1000℃で焼成できるセラミック
を用いれば良い。[Embodiment (1)] An embodiment (1) of the present invention will be described below with reference to FIG. The low-temperature fired ceramic layer 11 is made of CaO—Al 2 O 3 —SiO 2 —
B 2 O 3 based glass powder: 50-65% by weight (preferably 60 wt%) and Al 2 O 3 powder: 50-35% by weight (preferably 40 wt%) is formed by a green sheet consisting of a mixture of I have. Low temperature co-fired ceramic, in addition to the above system, MgO-Al 2 O 3 -SiO 2 -B 2 O 3
Mixture of Al-based powder and Al 2 O 3 powder, or S
A ceramic that can be fired at 800 to 1000 ° C., such as a mixture of iO 2 —B 2 O 3 -based glass powder and Al 2 O 3 powder, may be used.
【0012】各低温焼成セラミック層11の所定位置に
は、ビアホール12が形成され、各層のビアホール12
にAg系のビア導体13,14が充填されている。各層
のビア導体13,14は、Ag、Ag/Pd、Ag/P
t、Ag/Au等を主に含むAg系導体ペーストにより
形成されている。A via hole 12 is formed at a predetermined position of each low-temperature fired ceramic layer 11.
Are filled with Ag-based via conductors 13 and 14. The via conductors 13 and 14 of each layer are made of Ag, Ag / Pd, Ag / P
It is made of an Ag-based conductor paste mainly containing t, Ag / Au and the like.
【0013】基板表層に位置するビア導体13の表面部
は、他の部分よりも緻密度が高い緻密層15となり、A
g、Ag/Pd、Ag/Pt、Ag/Au等を主に含む
Ag系導体ペーストにより形成されている。緻密層15
は、これを形成するAg系導体ペーストに含まれる導体
粒子の平均粒径を1μm以下、好ましくは0.5μm以
下とすることで、緻密度が高められている。この際、導
体粒子の形状を球状にすれば、フレーク状等の不定形の
導体粒子よりも導体粒子間の隙間が少なくなり、緻密度
を更に高めることができる。The surface portion of the via conductor 13 located on the surface layer of the substrate becomes a dense layer 15 having a higher density than other portions.
g, Ag / Pd, Ag / Pt, Ag / Au, etc., and are formed of an Ag-based conductor paste. Dense layer 15
The density is increased by setting the average particle size of the conductive particles contained in the Ag-based conductive paste forming the conductive material to 1 μm or less, preferably 0.5 μm or less. In this case, if the shape of the conductive particles is made spherical, the gap between the conductive particles becomes smaller than in the case of irregular shaped conductive particles such as flakes, and the density can be further increased.
【0014】緻密層15以外のビア導体13,14は、
低温焼成セラミック層11との熱膨張率の差により低温
焼成セラミック層11にクラックが生じることを防止す
るため、使用するAg系導体ペーストの導体粒子の平均
粒径を数μm以上とすることで、比較的粗い緻密度にし
て、導体粒子間の空隙がある程度大きくなるようにして
いる。この場合、導体粒子の形状をフレーク状等の不定
形にすれば、球状の導体粒子よりも導体粒子間の隙間が
大きくなり、緻密度が粗くなる。The via conductors 13 and 14 other than the dense layer 15 are
In order to prevent cracks from occurring in the low-temperature fired ceramic layer 11 due to a difference in the coefficient of thermal expansion between the low-temperature fired ceramic layer 11 and the low-temperature fired ceramic layer 11, the average particle diameter of the conductive particles of the Ag-based conductive paste used is set to several μm or more. The density is relatively coarse so that the gap between the conductive particles is increased to some extent. In this case, if the shape of the conductive particles is made irregular, such as a flake shape, the gap between the conductive particles becomes larger than that of the spherical conductive particles, and the denseness becomes coarse.
【0015】各層の低温焼成セラミック層11を積層す
る前に、最上層の低温焼成セラミック層11を除く、各
層の低温焼成セラミック層11の上面には、Ag系導体
ペーストで内層配線パターン16をスクリーン印刷す
る。また、内蔵コンデンサ17を形成する内層の低温焼
成セラミック層11には、Ag系導体ペーストでコンデ
ンサ17の下面電極18をスクリーン印刷し、その上面
にPbペロブスカイト系、BaTiO3 系等の誘電体ペ
ーストで誘電体層19をスクリーン印刷し、更に、その
上面にAg系導体ペーストでコンデンサ17の上面電極
20をスクリーン印刷する。また、他の内層の低温焼成
セラミック層11には、RuO2 系の抵抗体ペーストで
内蔵抵抗体21をスクリーン印刷する。Before laminating the low-temperature fired ceramic layers 11 of each layer, an inner wiring pattern 16 is screened with an Ag-based conductor paste on the upper surface of each low-temperature fired ceramic layer 11 except for the uppermost low-temperature fired ceramic layer 11. Print. The lower electrode 18 of the capacitor 17 is screen-printed with an Ag-based conductor paste on the inner low-temperature fired ceramic layer 11 forming the built-in capacitor 17, and a Pb perovskite-based or BaTiO 3 -based dielectric paste is applied on the upper surface thereof. The dielectric layer 19 is screen-printed, and the upper surface electrode 20 of the capacitor 17 is screen-printed on the upper surface with an Ag-based conductor paste. Further, the built-in resistor 21 is screen-printed on another low-temperature fired ceramic layer 11 with a RuO 2 -based resistor paste.
【0016】印刷工程終了後、各層の低温焼成セラミッ
ク層11を積層して生基板を作り、これを例えば80〜
150℃、50〜250kgf/cm2 の条件で加熱圧
着して一体化する。更に、この生基板の両面に、加圧焼
成のためのアルミナグリーンシート22(ダミーグリー
ンシート)を積層し、上述と同様の方法で加熱圧着す
る。After the printing step, the low-temperature fired ceramic layers 11 of each layer are laminated to form a green substrate.
At 150 ° C., 50 to 250 kgf / cm 2 , they are heat-pressed and integrated. Further, alumina green sheets 22 (dummy green sheets) for firing under pressure are laminated on both surfaces of the green substrate, and are heat-pressed in the same manner as described above.
【0017】この後、2枚のアルミナグリーンシート2
2間に挟まれた生基板を、2〜20kgf/cm2 の範
囲内の圧力で加圧しながら800〜1000℃(好まし
くは900℃)で焼成し、内蔵コンデンサ17と内蔵抵
抗体21を有する低温焼成セラミック回路基板を同時焼
成する。この場合、基板両面に積層されたアルミナグリ
ーンシート22は1550〜1600℃まで加熱しない
と焼結しないので、800〜1000℃で焼成すれば、
アルミナグリーンシート22は未焼結のまま残される。
但し、焼成の過程で、アルミナグリーンシート22中の
バインダーが飛散してアルミナ粉体として残る。Thereafter, two alumina green sheets 2
The raw substrate sandwiched between the two is baked at 800 to 1000 ° C. (preferably 900 ° C.) while being pressed at a pressure in the range of 2 to 20 kgf / cm 2 , and has a low temperature having a built-in capacitor 17 and a built-in resistor 21. The fired ceramic circuit boards are fired simultaneously. In this case, since the alumina green sheets 22 laminated on both sides of the substrate do not sinter unless heated to 1550 to 1600 ° C., firing at 800 to 1000 ° C.
The alumina green sheet 22 is left unsintered.
However, during the firing process, the binder in the alumina green sheet 22 is scattered and remains as alumina powder.
【0018】焼成後、基板両面に残ったアルミナ粉体
(アルミナグリーンシート22)を研磨等により除去し
た後、基板表面に表層導体パターン23をフォトリソグ
ラフィ法で次のようにして形成する。まず、基板表面に
感光性導体ペーストを塗布し、これを乾燥させる。この
後、感光性導体ペースト膜に露光装置で露光し、これを
NaCO3 (1%)の水溶液で現像処理して、感光性導
体ペースト膜のうちの不要部分を除去して、表層導体パ
ターン23を形成する。この後、表層導体パターン23
を850℃で10分、焼成する。After firing, the alumina powder (alumina green sheet 22) remaining on both surfaces of the substrate is removed by polishing or the like, and then a surface conductor pattern 23 is formed on the surface of the substrate by photolithography as follows. First, a photosensitive conductor paste is applied to the surface of the substrate and dried. Thereafter, the photosensitive conductive paste film is exposed by an exposure device, and this is exposed to NaCO3. (1%) aqueous solution to remove unnecessary portions of the photosensitive conductive paste film to form a surface conductive pattern 23. After this, the surface conductor pattern 23
Is fired at 850 ° C. for 10 minutes.
【0019】以上説明した製造方法では、基板表層に位
置するビア導体13とその表面部の緻密層15とを低温
焼成セラミック層11と同時焼成するようにしたが、緻
密層15を除くビア導体13を低温焼成セラミック層1
1と同時焼成した後、このビア導体13上にAg系導体
ペーストを印刷して緻密層15を後焼成するようにして
も良い。In the manufacturing method described above, the via conductor 13 located on the surface of the substrate and the dense layer 15 on the surface thereof are simultaneously fired with the low-temperature fired ceramic layer 11. Low temperature firing ceramic layer 1
After firing simultaneously with the step 1, the Ag-based conductor paste may be printed on the via conductor 13 to post-fire the dense layer 15.
【0020】[実施形態(2)]上記実施形態(1)で
は、基板表層に位置するビア導体13の表面部のみを緻
密層15としたが、図2に示す本発明の実施形態(2)
では、基板表層に位置するビア導体25全体を緻密層と
している。この場合は、基板表層に位置するビア導体2
5(緻密層)を他の層のビア導体14と共に低温焼成セ
ラミック層11と同時焼成すれば良い。[Embodiment (2)] In the embodiment (1), only the surface portion of the via conductor 13 located on the surface layer of the substrate is the dense layer 15, but the embodiment (2) of the present invention shown in FIG.
Here, the entire via conductor 25 located on the surface of the substrate is a dense layer. In this case, the via conductor 2 located on the substrate surface layer
5 (dense layer) may be fired simultaneously with the low-temperature fired ceramic layer 11 together with the via conductors 14 of the other layers.
【0021】[0021]
【実施例】本発明者は、基板表層に位置するビア導体全
体又はその表面部を緻密層とした場合の信頼性を評価す
る試験を行ったので、その試験結果を次の表1に示す。EXAMPLES The present inventor conducted a test for evaluating the reliability when the entire via conductor located on the surface layer of the substrate or the surface portion thereof was a dense layer, and the test results are shown in Table 1 below.
【0022】[0022]
【表1】 [Table 1]
【0023】実施例,と比較例,は、いずれ
も、CaO−Al2 O3 −SiO2 −B2 O3 系の低温
焼成セラミックを用い、ビア導体をAgペーストで形成
し、内蔵コンデンサの誘電体層をPbペロブスカイト系
又はBaTiO3 系のペーストで形成し、内蔵抵抗体を
RuO2 系の抵抗体ペーストで形成したものである。In each of the embodiment and the comparative example, a low-temperature-fired ceramic of CaO-Al 2 O 3 -SiO 2 -B 2 O 3 system was used, a via conductor was formed with an Ag paste, and a dielectric of a built-in capacitor was used. The body layer is formed of a Pb perovskite-based or BaTiO 3 -based paste, and the built-in resistor is formed of a RuO 2 -based resistor paste.
【0024】実施例は、図1のビア導体構造を採用
し、基板表層のビア導体の表面部のみを緻密層としてい
る。緻密層は、Ag粒子の平均粒径が0.2μmで、粒
子形状が球状のものを使用した。緻密層以外の部分は、
Ag粒子の平均粒径が5μmで、粒子形状がフレーク状
のものを使用した。In the embodiment, the via conductor structure shown in FIG. 1 is adopted, and only the surface portion of the via conductor on the surface layer of the substrate is a dense layer. The dense layer used had an average particle diameter of Ag particles of 0.2 μm and a spherical particle shape. The parts other than the dense layer
Ag particles having an average particle size of 5 μm and a particle shape of flake were used.
【0025】実施例は、図2のビア導体構造を採用
し、基板表層のビア導体全体を緻密層としている。緻密
層は、Ag粒子の平均粒径が0.2μmで、粒子形状が
球状のものを使用した。緻密層以外の部分は、Ag粒子
の平均粒径が5μmで、粒子形状がフレーク状のものを
使用した。In the embodiment, the via conductor structure shown in FIG. 2 is adopted, and the entire via conductor on the surface layer of the substrate is a dense layer. The dense layer used had an average particle diameter of Ag particles of 0.2 μm and a spherical particle shape. Except for the dense layer, those having an average particle size of Ag particles of 5 μm and a particle shape of flake were used.
【0026】比較例は、従来例に相当し、全てのビア
導体を、Ag粒子の平均粒径が5μmで、粒子形状がフ
レーク状のAgペーストで多孔質状に形成した。比較例
は、全てのビア導体を、Ag粒子の平均粒径が0.2
μmで、粒子形状が球状のAgペーストで緻密に形成し
た。The comparative example corresponds to the conventional example, in which all the via conductors were formed in a porous form from a flake-shaped Ag paste having an average particle diameter of Ag particles of 5 μm. In the comparative example, all the via conductors had an average particle diameter of Ag particles of 0.2.
The particles were densely formed with a silver paste having a particle size of μm.
【0027】信頼性評価試験では、85℃、85%RH
の湿度環境下で、印加電圧50V(DC)、1000時
間の条件で、実施例,と比較例,について、サ
ンプル10個当たりの105 Ω以下のショートの発生数
を測定すると共に、ビア導体周辺のクラックの有無を観
察した。In the reliability evaluation test, 85 ° C., 85% RH
The number of short-circuit occurrences of 10 5 Ω or less per 10 samples was measured for the example and the comparative example under the conditions of an applied voltage of 50 V (DC) and 1000 hours under the humidity environment of, and the vicinity of the via conductor. Was observed for cracks.
【0028】従来例に相当する比較例は、全てのビア
導体の緻密度が粗く、多孔質状になっているため、基板
表面に露出するビア導体の導体粒子間の微細空隙から吸
湿して、全てのサンプルで105 Ω以下のショートが発
生し、ショート発生率が100%になった。In the comparative example corresponding to the conventional example, since all of the via conductors are coarse and porous, the via conductor absorbs moisture from the fine voids between the conductor particles of the via conductor exposed on the substrate surface. Short-circuits of 10 5 Ω or less occurred in all samples, and the short-circuit occurrence rate became 100%.
【0029】また、比較例は、全てのビア導体を緻密
に形成し、導体粒子間の空隙が小さくなっているので、
基板表層のビア導体からの吸湿が抑えられ、全てのサン
プルでショートは発生しなかったが、全てのビア導体を
緻密に形成すると、セラミック層との熱膨張率の差をビ
ア導体で吸収できなくなるため、セラミック層のビア導
体周辺にクラックが発生した。In the comparative example, all the via conductors are formed densely and the gap between the conductor particles is small.
Moisture absorption from the via conductor on the substrate surface was suppressed, and no short circuit occurred in all samples.However, if all via conductors were formed densely, the difference in coefficient of thermal expansion with the ceramic layer could not be absorbed by the via conductor. As a result, cracks occurred around the via conductor in the ceramic layer.
【0030】これに対し、実施例,は、基板表層の
ビア導体の表面部のみ、又は基板表層のビア導体全体を
緻密に形成して、導体粒子間の空隙が小さくなっている
ので、基板表層のビア導体からの吸湿が抑えられ、全て
のサンプルでショートは発生しなかった。しかも、実施
例,は、比較例とは異なり、基板全体のビア導体
を緻密化するのではなく、吸湿防止に必要最小限の基板
表層のビア導体又はその表面部のみを緻密化するだけで
あるから、他の層のビア導体は比較的粗い緻密度とな
り、セラミック層との熱膨張率の差をビア導体で吸収で
きる。このため、実施例,は、セラミック層のビア
導体周辺にクラックが発生しなかった。On the other hand, in the embodiment, only the surface portion of the via conductor on the surface layer of the substrate or the entire via conductor on the surface layer of the substrate is densely formed, and the gap between the conductive particles is reduced. , The moisture absorption from the via conductor was suppressed, and no short circuit occurred in all the samples. In addition, unlike the comparative example, the embodiment and the comparative example do not densify the via conductor of the entire substrate, but only densify the minimum via conductor of the surface layer of the substrate or its surface portion necessary for preventing moisture absorption. Therefore, the via conductors of the other layers have a relatively coarse density, and the difference in the coefficient of thermal expansion with the ceramic layer can be absorbed by the via conductors. Therefore, in the example, no crack occurred around the via conductor of the ceramic layer.
【0031】尚、本発明の低温焼成セラミック回路基板
は、表層導体パターン23をメッキ法等、フォトリソグ
ラフィ法以外の湿式パターニング法で形成しても良い。
また、図1及び図2の構成例では、基板下面にも表層導
体パターン23を形成したが、基板下面には表層導体パ
ターンを形成しない構成としても良い。In the low-temperature fired ceramic circuit board of the present invention, the surface conductor pattern 23 may be formed by a wet patterning method other than a photolithography method such as a plating method.
In the configuration examples of FIGS. 1 and 2, the surface conductor pattern 23 is also formed on the lower surface of the substrate. However, the structure may be such that the surface conductor pattern is not formed on the lower surface of the substrate.
【0032】また、前記実施形態では、焼成工程で生基
板を加圧しながら焼成する加圧焼成法を採用したが、加
圧せずに焼成しても良い。また、前記実施形態では、内
蔵コンデンサの誘電体層を誘電体ペーストを印刷して形
成したが、誘電体グリーンシートを基板内層に積層する
ようにしても良い。In the above-described embodiment, the pressure firing method in which the raw substrate is fired while pressing in the firing step is employed, but firing may be performed without pressing. Further, in the above embodiment, the dielectric layer of the built-in capacitor is formed by printing a dielectric paste, but a dielectric green sheet may be laminated on the inner layer of the substrate.
【0033】また、基板表層のビア導体に対する緻密層
の割合は、例えば、1/2、1/3、2/3、1/4、
3/4…にしても良く、要は、基板表層のビア導体の少
なくとも表面部を緻密層とすれば良い。また、内蔵コン
デンサと内蔵抵抗体の少なくとも一方を形成しない構成
としても良い。The ratio of the dense layer to the via conductor on the surface of the substrate is, for example, 1 /, 3, /, 4,
In other words, at least the surface portion of the via conductor on the surface layer of the substrate may be a dense layer. Further, a configuration in which at least one of the built-in capacitor and the built-in resistor is not formed may be adopted.
【0034】[0034]
【発明の効果】以上の説明から明らかなように、本発明
の請求項1では、基板表層に位置するAg系のビア導体
の少なくとも表面部を他の部分よりも緻密に形成したの
で、基板表層のビア導体からの水分や湿気の浸入を防止
できて、ショート等の電気的不具合を防止できる。しか
も、緻密層以外の部分のビア導体は、緻密度を粗くでき
るため、セラミック層との熱膨張率の差を吸収すること
ができ、低温焼成セラミック層のビア導体周辺にクラッ
クが生じることを防止でき、上述した防水・防湿効果と
相俟って、歩留り向上、信頼性向上を実現できる。As is apparent from the above description, in the first aspect of the present invention, at least the surface of the Ag-based via conductor located on the surface of the substrate is formed more densely than other portions. Of water or moisture from the via conductor can be prevented, and electrical problems such as short circuit can be prevented. Moreover, since the via conductors in the portions other than the dense layer can be made denser, the difference in the coefficient of thermal expansion from the ceramic layer can be absorbed, and cracks are prevented around the via conductor in the low-temperature fired ceramic layer. It is possible to realize an improvement in yield and an increase in reliability in combination with the above-described waterproof / moisture-proof effect.
【0035】また、請求項2では、基板内層に内蔵コン
デンサと内蔵抵抗体の少なくとも一方を形成したので、
低温焼成セラミック回路基板の高密度実装・小型化に貢
献することができる。According to the present invention, at least one of the built-in capacitor and the built-in resistor is formed in the inner layer of the substrate.
This can contribute to high-density mounting and miniaturization of low-temperature fired ceramic circuit boards.
【0036】また、請求項3では、Ag系導体ペースト
に含まれる導体粒子の粒径を小さくすることで、ビア導
体を緻密化するようにしたので、導体粒子の粒径によっ
てビア導体の緻密度を容易に調整することができる。In the third aspect, the via conductor is densified by reducing the particle size of the conductive particles contained in the Ag-based conductive paste. Can be easily adjusted.
【0037】また、請求項4では、ビア導体の緻密な部
分を、他の部分のビア導体と共に低温焼成セラミック層
と同時焼成するようにしたので、焼成工程が増加せず、
生産性を低下させずに済む。In the fourth aspect, the dense portion of the via conductor is co-fired with the low-temperature fired ceramic layer together with the other portions of the via conductor.
No loss of productivity.
【0038】また、請求項5では、ビア導体の緻密な部
分を、先に焼成されたビア導体上にAg系導体ペースト
を印刷して後焼成するようにしたので、後焼成するビア
導体の緻密な部分の焼成条件を独自に設定でき、導体ペ
ーストの選択の幅を広げることができる。According to the fifth aspect of the present invention, the dense portion of the via conductor is printed on the previously fired via conductor with an Ag-based conductor paste and post-fired. It is possible to independently set the firing conditions for various parts, and to expand the range of choice of conductor paste.
【図1】本発明の実施形態(1)を示すもので、(a)
は加圧焼成工程を説明する縦断面図、(b)は表層導体
パターンを形成した低温焼成セラミック回路基板の縦断
面図FIG. 1 shows an embodiment (1) of the present invention, in which (a)
Is a vertical cross-sectional view illustrating a pressure firing step, and (b) is a vertical cross-sectional view of a low-temperature fired ceramic circuit board on which a surface conductor pattern is formed.
【図2】本発明の実施形態(2)を示す低温焼成セラミ
ック回路基板の縦断面図FIG. 2 is a longitudinal sectional view of a low-temperature fired ceramic circuit board showing an embodiment (2) of the present invention.
11…低温焼成セラミック層、12…ビアホール、1
3,14…ビア導体、15…緻密層、16…内層配線パ
ターン、17…内蔵コンデンサ、18…下面電極、19
…誘電体層、20…上面電極、21…内蔵抵抗体、22
…アルミナグリーンシート、23…表層導体パターン、
25…ビア導体(緻密層)。11: low temperature firing ceramic layer, 12: via hole, 1
3, 14: Via conductor, 15: Dense layer, 16: Inner layer wiring pattern, 17: Built-in capacitor, 18: Lower electrode, 19
... dielectric layer, 20 ... top electrode, 21 ... built-in resistor, 22
... Alumina green sheet, 23 ... Surface conductor pattern,
25 ... via conductor (dense layer).
───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E317 AA24 BB04 BB14 CC17 CC22 CD01 CD21 GG05 GG11 GG17 5E346 AA12 AA14 AA15 AA43 BB20 CC18 CC39 DD34 EE24 EE27 FF18 FF45 GG02 GG06 GG09 HH08 HH21 HH33 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5E317 AA24 BB04 BB14 CC17 CC22 CD01 CD21 GG05 GG11 GG17 5E346 AA12 AA14 AA15 AA43 BB20 CC18 CC39 DD34 EE24 EE27 FF18 FF45 GG02 GG06 GG09 HH08 HH21 HH33
Claims (5)
各層間をAg系のビア導体で電気的に接続し、基板表面
に表層導体パターンをフォトリソグラフィ法等の湿式パ
ターニング法で形成した低温焼成セラミック回路基板に
おいて、 基板表層に位置するAg系のビア導体の少なくとも表面
部を他の部分よりも緻密に形成したことを特徴とする低
温焼成セラミック回路基板。Claims: 1. A plurality of low-temperature fired ceramic layers are laminated,
In a low-temperature fired ceramic circuit board in which each layer is electrically connected with an Ag-based via conductor and a surface layer conductor pattern is formed on the substrate surface by a wet patterning method such as a photolithography method, an Ag-based via conductor located on the substrate surface layer A low-temperature fired ceramic circuit board, characterized in that at least the surface portion of the ceramic circuit board is formed more densely than other portions.
の少なくとも一方を形成したことを特徴とする請求項1
に記載の低温焼成セラミック回路基板。2. The semiconductor device according to claim 1, wherein at least one of a built-in capacitor and a built-in resistor is formed in an inner layer of the substrate.
A low-temperature fired ceramic circuit board according to item 1.
成するAg系導体ペーストに含まれる導体粒子の粒径を
小さくすることで、緻密化することを特徴とする請求項
1又は2に記載の低温焼成セラミック回路基板。3. The dense portion of the via conductor is densified by reducing the particle size of conductive particles contained in an Ag-based conductive paste forming the via portion. A low-temperature fired ceramic circuit board as described.
のビア導体と共に前記低温焼成セラミック層と同時焼成
されていることを特徴とする請求項1乃至3のいずれか
に記載の低温焼成セラミック回路基板。4. The low-temperature firing according to claim 1, wherein the dense portion of the via conductor is co-fired with the low-temperature firing ceramic layer together with another portion of the via conductor. Ceramic circuit board.
されたビア導体上にAg系導体ペーストを印刷して後焼
成されていることを特徴とする請求項1乃至3のいずれ
かに記載の低温焼成セラミック回路基板。5. The method according to claim 1, wherein the dense portion of the via conductor is printed after an Ag-based conductor paste is printed on the previously fired via conductor and then fired. A low-temperature fired ceramic circuit board as described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00137099A JP4122612B2 (en) | 1999-01-06 | 1999-01-06 | Low temperature fired ceramic circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00137099A JP4122612B2 (en) | 1999-01-06 | 1999-01-06 | Low temperature fired ceramic circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000200973A true JP2000200973A (en) | 2000-07-18 |
| JP4122612B2 JP4122612B2 (en) | 2008-07-23 |
Family
ID=11499624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP00137099A Expired - Lifetime JP4122612B2 (en) | 1999-01-06 | 1999-01-06 | Low temperature fired ceramic circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4122612B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006156934A (en) * | 2004-12-01 | 2006-06-15 | Samsung Electro Mech Co Ltd | Printed board with built-in capacitor and its manufacturing method |
| JP2007096232A (en) * | 2005-09-30 | 2007-04-12 | Fujitsu Ltd | Interposer and method for manufacturing electronic device |
| JP2008159940A (en) * | 2006-12-25 | 2008-07-10 | Kyocera Corp | Multilayer wiring board and manufacturing method thereof |
| JP2008235641A (en) * | 2007-03-22 | 2008-10-02 | Matsushita Electric Ind Co Ltd | Manufacturing method of ceramic multilayer substrate |
| JP2012069911A (en) * | 2010-08-26 | 2012-04-05 | Kyocera Corp | Wiring board |
| WO2016068248A1 (en) * | 2014-10-29 | 2016-05-06 | 京セラ株式会社 | Circuit board and electronic device provided with same |
| WO2025117214A1 (en) * | 2023-11-29 | 2025-06-05 | KYOCERA AVX Components Corporation | Multilayer electronic component including at least one via connected to a capacitor outside its capacitive area |
-
1999
- 1999-01-06 JP JP00137099A patent/JP4122612B2/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006156934A (en) * | 2004-12-01 | 2006-06-15 | Samsung Electro Mech Co Ltd | Printed board with built-in capacitor and its manufacturing method |
| JP2007096232A (en) * | 2005-09-30 | 2007-04-12 | Fujitsu Ltd | Interposer and method for manufacturing electronic device |
| US7937830B2 (en) | 2005-09-30 | 2011-05-10 | Fujitsu Limited | Interposer and electronic device fabrication method |
| JP2008159940A (en) * | 2006-12-25 | 2008-07-10 | Kyocera Corp | Multilayer wiring board and manufacturing method thereof |
| JP2008235641A (en) * | 2007-03-22 | 2008-10-02 | Matsushita Electric Ind Co Ltd | Manufacturing method of ceramic multilayer substrate |
| JP2012069911A (en) * | 2010-08-26 | 2012-04-05 | Kyocera Corp | Wiring board |
| WO2016068248A1 (en) * | 2014-10-29 | 2016-05-06 | 京セラ株式会社 | Circuit board and electronic device provided with same |
| JPWO2016068248A1 (en) * | 2014-10-29 | 2017-08-03 | 京セラ株式会社 | Circuit board and electronic device having the same |
| WO2025117214A1 (en) * | 2023-11-29 | 2025-06-05 | KYOCERA AVX Components Corporation | Multilayer electronic component including at least one via connected to a capacitor outside its capacitive area |
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| Publication number | Publication date |
|---|---|
| JP4122612B2 (en) | 2008-07-23 |
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