JP2000201190A - Clock phase error detection circuit and clock phase error detection method - Google Patents

Abstract

(57) Abstract: To obtain a clock phase error signal that satisfies clock recovery performance at low C / N used for correction of a recovered clock phase of a clock recovery circuit. A clock phase error detection circuit for obtaining a clock phase error signal for correcting a recovered clock phase used in a circuit for recovering a clock synchronized with a predetermined phase from a band-limited pulse code signal. Determining means 2 for detecting a pattern by detecting a code pattern of a signal sampled by the clock and determining a pattern; phase error calculating means for obtaining a phase error by a predetermined calculation from the determined code pattern and the sampled signal 1 is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock phase for obtaining a clock phase error signal used for phase correction of a clock recovery circuit used in a receiving apparatus in a system for transmitting a digital signal using a band-limited pulse signal. The present invention relates to an error detection circuit and a clock phase error detection method.

[0001]

2. Description of the Related Art In a system for transmitting a digital signal using a band-limited pulse wave, code transmission is generally performed using a pulse whose roll-off spectrum has been shaped. For this reason, a slight shift in the sample timing on the receiving side sharply degrades the characteristics.

Conventionally, simple sample timing, ie, clock recovery, rectifies an input signal, extracts a clock component, and passes the extracted clock component through a narrow-band bandpass filter to recover a clock. I was However, in recent years, spectral shaping characteristics with a small roll-off factor have been used in order to further save transmission bandwidth, so that higher performance of clock recovery has been required.

As a clock recovery circuit that meets such a demand, for example, a control method as shown in FIG. 11A has been proposed. This is to detect the phase control signal of the clock before and after the zero cross point. Here, this control method will be referred to as a zero cross control method.

[0004] The zero cross control method will be described. FIG. 11 (A)
(A) simply shows the eye pattern of a binary digital signal, and on average there is no problem in the state of the signal itself. Then, when sampling this binary digital signal, if the sample timing matches the signal phase as in S1 and S2, the transmission code can be taken in correctly, so that the data can be reproduced correctly.

[0005] Next, as shown in FIG. 11 (b), the sampling timing is delayed by Te seconds and S1 ',
Consider what happens when the position shifts to the position of S2 '.
In this case, since the shift from S1 to S1 ', the opening of the eye pattern of the binary digital signal narrows from W0 to W1, while the timing at which sampling should be performed at S2, which is the zero cross point position, is also shifted by Te seconds. FIG.
The input signal is sampled at the timing position of S2 'in (A) (c), and the sampled value (sample value) at this sampling timing is represented by e.
Then, this e takes a larger value than the value that should have been near zero originally.

In this case, if the transmission code changes from "-1" to "+1" before and after the zero cross point, the sample value takes a positive value e (-+), and conversely, "+1" When the value changes from "-1" to "-1", the sample value takes a negative value of e (+-). Therefore, by knowing the transmission codes before and after the zero cross point, it is possible to know the shift of the sample timing. This is the principle of zero cross control.

As described above, in the zero cross control method, since the value near the zero cross point is used, there is a feature that the zero cross control operates regardless of the amplitude of the eye pattern. However, actually, the eye pattern has a waveform as shown in FIG. 12, and even if the clock phases are synchronized, e (− +) and e (+
In some cases,-) does not become zero. At this time, since a control signal is generated, the problem that jitter is large remains.

On the other hand, a control method as shown in FIG. 11B has been developed. This is a method of detecting a phase control signal of a clock before and after an eye pattern convergence point. Here, this method will be referred to as an eye convergence point control method. That is, the eye convergence point control method is the following control method. (A) of FIG. 11 (B) shows the eye pattern of the binary digital signal as T-1, T0, T1 of (b) of FIG. 11 (B).
Indicates the optimal clock phase. In this example, sampling is performed at the reference levels L1, L2, and L3 by the 2-bit A / D converter, but an example using a multi-level A / D converter will be considered. When the transmission code changes to a-1, B0, C1, if the clock phase is shifted by + Δt, the sample value becomes larger than the reference level L1, and if the clock phase is shifted by -Δt, the sample value becomes smaller than the reference level L1. Value.

Therefore, it is possible to detect a shift in the sample timing based on the difference between the transmission code before and after the control point and the reference level at the control point.

As described above, since the value near the eye convergence point is used in the eye convergence point control method, the jitter at the time of phase synchronization can be reduced. However, in the case where the amplitude of the eye pattern changes, there is a problem that the clock phase cannot be controlled because the difference value from the reference level does not accurately indicate the shift of the sample timing.

Therefore, as a clock recovery circuit which solves these problems and improves the performance of clock recovery, a technique as disclosed in Japanese Patent Application No. 4-126041 (see Japanese Patent Application Laid-Open No. 5-327681) has been developed. Have been.

This is shown in FIG. 13 and will be referred to as a clock phase error detection control method. This clock phase error detection control method will be described. FIG. 13A shows an eye pattern, and shows a case where the sample values of the eye convergence point are “L0” and “−L0”. Now, consider a case where the clock phase is shifted by “+ Δt”.
If the transmission code changes to “A1” and “B2” in this state, the sample value of “A1” is “− (L0−Δ
l) ”and“ B2 ”are“ (L0 + Δl). ”Here, comparing the absolute values of the respective sample values, | L0 + Δl | − | − (L0−Δl) | = 2Δl> 0 and the sample value of “B2” is larger in absolute value.

When the transmission code changes to "B1" and "A2", the sample value of "B1" becomes "(L0-Δ
l) ", the sample value of" A2 "is"-(L0 + Δl) ".
Becomes Here, when comparing the absolute values of the respective sample values, |-(L0 + Δl) | − | (L0−Δl) | = 2Δl>
0, indicating that the sample value of “A2” is larger in absolute value.

That is, when the clock phase is delayed (clock phase “+ Δt”), the absolute value of two consecutive samples is larger in the latter value, and similarly, the clock phase is advanced (clock phase “+ Δt”). -Δt ″), it can be seen that the absolute value of two consecutive samples is smaller in the latter value.

Thus, a phase difference can be obtained by obtaining an amplitude difference between two consecutive samples.

That is, when the phase error in the clock phase error detection control method can be detected, as shown in FIG. 14, which is a diagram schematically illustrating the principle described in FIG.
The input pattern which is the generation pattern of four consecutive symbols of the input pulse code is the symbol "A0", "A
When the positions of “1”, “B2”, and “B3” are taken, if the sample points are shifted by Δt, the phase error can be obtained as “2Δl”.

On the contrary, FIG. 15 shows an example in which the phase error cannot be detected. In this example, the input pattern of the input signal which is a generation pattern of four consecutive symbols of the input pulse code is used. Are the symbols "B0", "A
If the sample points are shifted by Δt when the positions of “1”, “B2”, and “A3” are taken, the phase error becomes “O” and cannot be obtained.

Therefore, the phase error can be detected by the clock phase error detection control method disclosed in Japanese Patent Application No. 4-126041.
Only when the input signal is monotonically increasing or monotonically decreasing from immediately before the sample timing T1 to immediately after the next sample timing T2.

This is the case where the signal is as shown in FIG. 14, and the input pattern of four consecutive symbols is "A0",
Cases where the positions of “A1”, “B2” and “B3” are taken;
There are a total of two cases of taking the positions of "B0", "B1", "A2", and "A3". Since the input pattern variation of four consecutive symbols is 16 types, the phase error can be detected by the clock phase error detection control method only with a probability of “１ ／” with respect to the input data.
The phase error can be obtained only with a low probability of 8 ".

As described above, since the probability that the phase error can be detected is low, the clock reproduction at a low C / N is insufficient.

[0021]

In a system for transmitting a digital signal using a band-limited pulse wave, a spectral shaping characteristic having a small roll-off factor is used in order to save a transmission bandwidth. There has been a demand for higher performance of clock reproduction. Japanese Patent Application No. Hei 4-126041 (Japanese Unexamined Patent Application Publication No.
-327681) has been developed.

However, the phase error can be detected by this technique only when the input signal monotonically increases or monotonically decreases from immediately before the sample timing to immediately after the next sample timing.

This is because there are only two types of input patterns, but there are 16 types of input patterns of four consecutive symbols. Therefore, the clock phase error detection control method can detect a phase error. The phase error can be obtained only with a probability of "1/8" with respect to the input data, and with a low probability of "1/8".

As described above, since the probability that the phase error can be detected is low in the conventional method, there is a problem that the clock reproduction performance at a low C / N is insufficient.

Therefore, it is an object of the present invention to detect a phase error with a high probability, obtain a clock phase error signal used for phase correction of a clock recovery circuit, and satisfy the clock recovery performance at a low C / N. A clock phase error detection circuit and a clock phase error detection method are provided.

[0026]

In order to achieve the above object, the present invention is configured as follows. That is, in a clock phase error detection circuit for obtaining a clock phase error signal for correcting a reproduced clock phase used in a circuit for reproducing a clock synchronized with a predetermined phase from a band-limited pulse code signal, Determining means for detecting a code pattern of a signal obtained by sampling according to the above, and determining a pattern; and a phase error calculation for obtaining a clock phase error signal by a predetermined phase error calculation from the determined code pattern and the signal obtained by sampling. Means. In addition, the phase error calculation means is particularly configured by an FIR filter, and the phase error calculation is configured to switch the coefficient of the FIR filter according to the detected code pattern.

According to the present invention, when reproducing a clock synchronized with a predetermined phase from a band-limited pulse code signal, the present invention detects a code pattern of a signal obtained by sampling the pulse code signal with the clock and detects the pattern. The phase error is determined by a predetermined calculation from the determined code pattern and the signal obtained by sampling.
Then, the obtained phase error is used for phase correction of clock recovery.

Further, when the FIR filter is used, the phase error calculating means can be easily configured. In addition, the error calculation is performed by changing the filter coefficient corresponding to the input pattern so that the phase error detection can be performed for all the consecutive code patterns. This makes it possible to quickly correct the phase shift when a clock phase shift occurs during clock recovery.

In particular, according to the present invention, a circuit for reproducing a clock synchronized with a predetermined phase from a band-limited pulse code signal detects a code pattern of a signal sampled by the clock, and detects the detected code pattern. By calculating the phase error according to, the phase error can be detected in all the continuous code patterns, so that the phase error can be detected in many cases. The probability of detection can be increased, and low C / N (carrier noise ratio)
Clock recovery performance can be improved.

Therefore, according to the present invention, it is possible to perform clock reproduction that satisfies clock reproduction performance at a low C / N.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing an embodiment of a clock phase error detection circuit according to the present invention. In the figure, 1 is a phase error calculation circuit, 2 is a pattern determination circuit, 3 is a level determination circuit, 4 is a validity determination circuit, 5 is a hold circuit, 6 is an input terminal, 7 is a threshold input terminal, and 8 is an output terminal. It is.

Of these, an input signal obtained by sampling the received pulse code signal at the reproduction clock timing is input to the input terminal 6. Here, the pulse code signal is a band-limited pulse code signal. The phase error calculation circuit 1 performs an error calculation according to the code pattern of the input signal, and supplies error data as a calculation result to the hold circuit 5.

The pattern determination circuit 2 is for determining the code pattern of the input signal input from the input terminal 6, and the level determination circuit 3 determines the level of the input signal input from the input terminal 6. This is to detect that the level of the input signal is higher than the threshold value supplied from the threshold value input terminal 7.

The validity judging circuit 4 judges whether the pattern judgment result by the pattern judging circuit 2 and the level judgment result by the level judging circuit 3 are satisfied at the same time. If the result is satisfied, the result is "effective". If the determination result of the validity determination circuit 4 is "valid", the hold circuit 5 passes the error data output from the phase error calculation circuit 1 as it is, and A phase error signal is output. If the determination result of the validity determination circuit 4 is "invalid", this is used as a hold signal to hold the error signal of the phase error calculation circuit 1 immediately before the hold signal and output it as a clock phase error signal. is there. A clock phase error signal from the hold circuit 5 is output to the output terminal 8.

In this device having such a configuration, an input signal obtained by sampling the pulse code signal at the reproduction clock timing is input from the input terminal 6. This input signal is branched to a phase error calculation circuit 1, a level determination circuit 3, and a pattern determination circuit 2.

First, the level determination circuit 3 detects that the input signal level is higher than the threshold supplied from the threshold input terminal 7. It is a problem if the threshold is too large or too small, so that an empirically optimum value is selected according to the purpose.
As shown in the figure, the input signal level is a value near 50% of the input signal level "+ L0", "-L0", for example, "+ L0 / 2", "-L0".
L0 / 2 "is preferable.

In this embodiment, since the phase error is calculated using "4 samples" as described later, in the level determination circuit 3, even in this level determination, successive "4 samples" simultaneously exceed the threshold value. It is determined that it is large. The determination result is supplied to the validity determination circuit 4.

Next, the pattern determination circuit 2 determines the code pattern of the "4 samples". The determination result is supplied to the phase error calculation circuit 1 as a coefficient switching signal for the phase error calculation, and the validity determination circuit 4 determines whether the pattern is valid for the error calculation.
Is also supplied.

The validity judging circuit 4 judges whether the pattern judgment result and the level judgment result are simultaneously satisfied. That is, when the code pattern of consecutive "4 samples" matches the pattern in which the phase error calculation can be performed, and the signal amplitude is larger than a predetermined threshold value, it is determined as "valid". If the above two determinations are not satisfied at the same time, it is determined as “invalid”, and the “invalid” determination signal is used as a hold signal as a hold signal in the hold circuit 5.
To supply.

On the other hand, the phase error calculation circuit 1 performs an error calculation according to the code pattern of the input signal, and supplies error data as a calculation result to the hold circuit 5. Hold circuit 5
Outputs the error data supplied from the phase error calculation circuit 1 to the output terminal 8 as a clock phase error signal. However, when the hold signal is supplied from the validity determination circuit 4, the immediately preceding clock phase error signal is held, and the error data supplied from the phase error calculation circuit 1 is determined to be "invalid".

Therefore, when the determination result of the validity determination circuit 4 is "valid", the hold circuit 5 passes the error data output from the phase error calculation circuit 1 as it is, and uses it as a clock phase error signal at the output terminal 8. If the determination result of the validity determination circuit 4 is "invalid", this is used as a hold signal to hold the error signal of the phase error calculation circuit 1 immediately before the hold signal and output it to the output terminal 8 as a clock phase error signal. become. <Configuration of Phase Error Calculation Circuit> Next, a specific embodiment of the phase error calculation circuit 1 will be described with reference to FIG. As shown in FIG. 3, the phase error calculation circuit 1 includes a serially connected delay element 2.
01, 202, 203, and 204, and each of these delay elements 2
The variable coefficient units 205, 206, 207, and 208 are supplied with delay outputs from the output units 01, 202, 203, and 204, and the adder 209 adds the outputs of the variable coefficient units 205, 206, 207, and 208. This is realized by an FIR filter.

The sampling signal is supplied from a sampling signal input terminal 210. The sampling signal supplied from the sampling signal input terminal 210 is a delay element 201, a delay element 202, a delay element 203, a delay element 2
04. The delayed signals are respectively applied to the corresponding variable coefficient units 205, 206, 207, and 20 of the variable coefficient units 205, 206, 207, and 208.
After being amplified according to the respective coefficients at 8, the adder 20
The result is added at 9 to complete the error calculation, and is output from the output terminal 212 to the hold circuit 5 as error data.

A coefficient switching signal from the pattern determination circuit 2 is supplied to the input terminal 211, and the coefficient C of the variable coefficient units 205, 206, 207, and 208 is changed according to the coefficient switching signal.
3, C2, C1 and C0 are controlled to switch the filter characteristics.

<Method of Error Calculation> A method of error calculation will be described with reference to FIG. (A) in FIG.
10 is a sampling signal supplied from. The code pattern of the signal shown here is “A0” (=
−L0), “A1” (= −L0), “B2” (= + L
0) ”and“ A3 ”(= + L0). For this code pattern, as shown in FIG.
0) 205, variable coefficient unit (C1) 206, variable coefficient unit (C2) 207, and variable coefficient unit (C3) 208
When a coefficient is set to “−1”, “+2”, “0”, “−1” in order to configure an FIR filter, the FIR filter
The filter output, that is, the error calculation result is "-3L0" when there is one clock delay, "0" when there is no clock delay, and "+ 3L0" when there is one clock advance in FIG. (C).

The coefficient shown in FIG. 4B is "C0 =-
1 "," C1 = 2 "," C2 = 0 ", and" C3 = -1 ", and each sample value takes a value shown in FIG. 4A (the sample value is" L0 "or" L0 "). −L0 ”) is a state where the phase error is“ zero ”, and the time t in FIG.
Is the error calculation result.

Here, consider the case where there is one clock phase error. Then, as can be seen from FIG. 4 (c), when the time is delayed by one clock, the time t is "t = -1", and the filter output at this time is "-3L0".
When the clock is advanced by one clock, the time t becomes “t = +
1 ”, the filter output at this time is“ + ”
3L0 ".

Although the above description is based on a sampled value of the input signal, a continuous result as shown in FIG. 4D is obtained when a continuous signal having a band-limited pulse code is input. This is because when the sampling timing shifts, that is, when a sampling phase error occurs, FIG.
This means that the filter output changes near time t = 0 shown in FIG.

As described above, in the phase error calculation circuit 1 of this embodiment, the filter output constituting the phase error calculation circuit 1 takes a positive value when the clock phase is delayed, and takes a negative value when the clock phase is delayed. Take. When there is no phase error, the value becomes zero, so that the filter output, that is, the output of the phase error calculation circuit 1 indicates the phase error.

FIG. 5 shows filter coefficients for which error calculation can be performed for each input pattern. Although different depending on the symbol values before and after “4 symbols”, according to the phase error calculation circuit 1 configured by the filter in FIG.
It is possible to obtain a filter output that continuously increases from the time of the phase lag to the time of the phase advance as shown in FIG.

According to the phase error calculation circuit 1 having the configuration of the filter of FIG. 3, among the “16 patterns” of the code pattern of “4 symbols”, as shown in FIG.
Error calculation is possible for "16 patterns".

That is, when the phase error can be detected, FIG. 6 is a diagram schematically showing the principle described in FIG.
As shown in the figure, the input patterns are [1] "A0", "A
1 "," B2 ", and" B3 ", [2]" B
0 "," B1 "," A2 "," A3 ", [3]" A0 "," A1 "," B2 "," A3 ", [4]" B0 ""," B1 "," A2 ",
When the arrangement of “B3” is taken, [5] “A0”, “B1”,
When the arrangement of “A2” and “A3” is taken, [6] “B0”,
When arranging “A1”, “B2”, “B3”,
[7] When the arrangement of “A0”, “A1”, “A2”, “B3” is taken, [8] “B0”, “B1”, “B2”, “A
3 ", [9]" B0 "," A1 "," A
2 "," A3 ", [10]" A0 ",
When “B1”, “B2”, and “B3” are arranged, [1
1] When the arrangement of “A0”, “B1”, “B2”, “A3” is taken, [12] “B0”, “A1”, “A2”, “B”
3 ”, [13]“ A0 ”,“ B1 ”,
When the arrangement of “A2” and “B3” is taken, [14] “B
0 "," A1 "," B2 "," A3 "
In a total of 14 patterns, the phase error can be obtained according to the phase shift of the sample point.

On the contrary, FIG. 7 shows an example in which the phase error cannot be detected conventionally. In this example, the input patterns of "B0", "B1", "B2", and "B3" are used. Time,
In the case of "A0", "A1", "A2", and "A3", even if the sample points were shifted, the phase error was "O" and could not be obtained.

However, according to the present invention, a phase error can be detected.

That is, the variation of the code pattern of "4 symbols" is as shown in FIG.
0 "," B1 "," B2 "," B3 "
[16] When the arrangement of “A0”, “A1”, “A2”, and “A3” is taken, there are a total of “16 patterns” including those of “A0”, “A0”, "A
An error calculation is possible including a total of two patterns, a pattern having the arrangement of "1", "A2", and "A3" and a pattern having the arrangement of "B0", "B1", "B2", and "B3". This means that the phase error detection accuracy is higher than the conventional error calculation method.

In order to prevent deterioration of the phase error detection accuracy due to a pattern determination error at the time of low C / N, when the amplitude of the sampling signal is smaller than a predetermined threshold, the error calculation result is used. Instead, the hold circuit 5 operates to hold the immediately preceding phase error signal.

Then, using the phase error signal obtained via the hold circuit 5 as a phase control signal, the phase control of the clock recovery circuit is performed, and the phase shift of the recovered clock is corrected corresponding to the phase control signal. .

In this embodiment, if the sample points are shifted for a total of 16 patterns including two patterns in which the appearance form of four consecutive symbols has no sign change, the phase error can be obtained in any case. Using the obtained and obtained phase error signal as a phase control signal, the phase control of the clock recovery circuit can be performed, and the phase shift of the recovered clock can be corrected corresponding to the phase control signal. Therefore, all the variations of the symbol arrangement are 16
Since the phase error signal can be obtained for all 16 patterns in the pattern, the phase error detection accuracy is dramatically increased as compared with the conventional error calculation method, and when the phase shift of the clock recovery circuit occurs, the phase error signal is quickly obtained. It becomes possible to carry out displacement correction control.

Accordingly, a clock which can detect a phase error with a high probability, obtain a clock phase error signal used for phase correction of a clock recovery circuit, and satisfy the clock recovery performance at a low C / N. A phase error detection circuit is obtained.

Next, another embodiment of the present invention will be described as a second embodiment.

(Embodiment 2) FIG. 8 shows another embodiment of the present invention. 8, reference numeral 1 denotes a phase error calculation circuit, 502 denotes a pattern determination circuit, 3 denotes a level determination circuit, 4 denotes a validity determination circuit, 5 denotes a hold circuit, 6 denotes an input terminal, 7 denotes a threshold input terminal, and 8 denotes an output. A terminal 501 is an absolute value circuit for obtaining an absolute value of an input signal input from the input terminal 6.

In this embodiment, an absolute value circuit 501 is provided at a stage preceding the phase error calculation circuit 1 so that an input signal input to the input terminal 6 is supplied to the phase error calculation circuit 1 via the absolute value circuit 501. Point and level judgment circuit 3
Also converts the input signal input from the input terminal 6 into an absolute value circuit 5
The difference from the first embodiment lies in that the absolute value is given in step 01 to determine the level thereof, but the other configuration is basically the same as that of the first embodiment. However, in this embodiment, when the input signal sampled at the reproduction clock timing is input to the input terminal 6, the pattern determination circuit 50
No. 2 makes a pattern judgment on this.

The phase error calculation circuit 1 is composed of an absolute value circuit 5
In step 01, an error calculation is performed according to the code pattern of the input signal by using an input signal obtained by converting the code pattern of the input signal into an absolute value, and error data as a calculation result is supplied to the hold circuit 5.

The level determination circuit 3 is for determining the level of the absolute value of the input signal input from the input terminal 6 by the absolute value circuit 501. The validity judging circuit 4 detects that the level of the input signal is higher than the threshold value supplied from the input circuit, and the validity judging circuit 4 satisfies the pattern judgment result by the pattern judgment circuit 502 and the level judgment result by the level judgment circuit 3 simultaneously The hold circuit 5 determines whether the determination is "valid" if the result of the validity determination circuit 4 is "valid". In some cases, the error data output from the phase error calculation circuit 1 is passed as it is, and this is output as a clock phase error signal. If the determination result of the validity determination circuit 4 is "invalid", Holds the error signal of the phase error calculation circuit 1 in the immediately preceding a record as a hold signal, and outputs a clock phase error signal. A clock phase error signal from the hold circuit 5 is output to the output terminal 8.

In this device having such a configuration, the input signal sampled at the reproduction clock timing is supplied to the input terminal 6.
Input from This input signal is branched to an absolute value circuit 501 and a pattern determination circuit 502.

Then, the absolute value circuit 501 converts the absolute value of the input signal, and then supplies the input signal to the phase error calculation circuit 1 and the level determination circuit 3. Therefore, the phase error calculation circuit 1 and the level determination circuit 3 are provided with the absolute value of the code pattern of the input signal.

The level determination circuit 3 detects whether the absolute value of the input signal level is larger than the threshold value supplied from the threshold value input terminal 7. Here, since the phase error is calculated using “4 samples”, it is determined in this level determination that consecutive “4 samples” are simultaneously larger than the threshold. The determination result is supplied to the validity determination circuit 4.

The pattern determining circuit 502 determines the code pattern of “4 samples” for the input signal from the input terminal 6. Then, the determination result is supplied to the phase error calculation circuit 1 as a coefficient switching signal for the phase error calculation, and is also supplied to the validity determination circuit 4 to determine whether the pattern is valid for the error calculation. You.

The validity judging circuit 4 judges whether the pattern judgment result and the level judgment result are simultaneously satisfied. That is, when the code pattern of consecutive "4 samples" matches the pattern in which the phase error calculation can be performed, and the signal amplitude is larger than a predetermined threshold value, it is determined as "valid". If the above two determinations are not satisfied at the same time, it is determined as “invalid”, and the “invalid” determination signal is used as a hold signal as a hold signal in the hold circuit 5.
To supply.

On the other hand, the phase error calculation circuit 1 performs an error calculation according to the code pattern of the input signal that has been converted into an absolute value, and supplies the error data as the calculation result to the hold circuit 5.
The hold circuit 5 outputs the error data supplied from the phase error calculation circuit 1 to the output terminal 8 as a clock phase error signal. However, when the hold signal is supplied from the validity determination circuit 4, the immediately preceding clock phase error signal is held, and the error data supplied from the phase error calculation circuit 1 is determined to be "invalid".

Therefore, when the determination result of the validity determination circuit 4 is “valid”, the hold circuit 5 passes the error data output from the phase error calculation circuit 1 as it is, and uses the error data as a clock phase error signal at the output terminal 8. If the determination result of the validity determination circuit 4 is "invalid", this is used as a hold signal to hold the error signal of the phase error calculation circuit 1 immediately before the hold signal and output it to the output terminal 8 as a clock phase error signal. become.

Then, using this phase error signal as a clock phase error signal, the phase control of the clock recovery circuit is performed by the amount corresponding to this signal, and the phase shift of the recovered clock is corrected so as to correspond to the phase control signal. I do.

As described above, this embodiment is characterized in that the error calculation is performed on an input signal that has been subjected to absolute value conversion.

That is, the difference between this embodiment and the first embodiment will be described with reference to FIG. In order to obtain the same error calculation result as that of the above-described embodiment with respect to the input signal subjected to the absolute value conversion, a symbol whose sign is converted by the absolute value conversion, that is, a variable coefficient through which a signal having a negative value passes What is necessary is just to change the sign of the container. This can be easily determined from the configuration of the FIR filter.

Therefore, when the filter coefficients having 16 variations in FIG. 5 are code-converted when the corresponding input pattern is a negative value to reduce the variations, the filter coefficients become variations as shown in FIG. Here, focusing on the variations of the filter coefficients, the filter coefficients are “A”, “A ′”, “B”, “B ′”, “C”,
It can be seen that there are seven types, "C '" and "D".

That is, the number of filter coefficients can be reduced by converting the absolute value of the input signal.

This means simplification of the circuit configuration, that is, reduction of the circuit scale and facilitation of control. Also, it can be seen that the variations of the filter coefficients "A" and "A '", "B" and "B'", and "C" and "C '" are only the signs of the coefficients inverted. For example, when a filter coefficient of variation “A ′” is required, an error operation is performed using the filter coefficient of variation “A”,
By inverting the sign of the operation result, the same result as that of performing the error operation using the filter coefficient of variation “A ′” can be obtained.

In this manner, only four types of filter coefficients are required, and it can be seen that an error calculation can be performed by preparing these four types of filter coefficients.

Using the phase error signal obtained via the hold circuit 5 as a phase control signal, the phase control of the clock recovery circuit is performed, and the phase shift of the recovered clock is corrected corresponding to the phase control signal.

In this embodiment, if the sample points are shifted in all 16 patterns including two patterns in which the appearance of four consecutive symbols has no sign change, the phase error is determined in any case. Using the obtained phase error signal (clock phase error signal) as a clock phase control signal to perform clock phase control of the clock recovery circuit, and correct the phase shift of the recovered clock corresponding to the phase control signal. Can be. As a result, phase error signals can be obtained for all 16 patterns out of the 16 patterns which are all variations of the symbol arrangement. When a phase shift occurs, the phase shift correction control can be quickly performed.

Further, in this embodiment, the input signal is subjected to the absolute value conversion, whereby the number of filter coefficients used in the filter constituting the phase error calculating circuit is reduced from the 16 patterns to the half 7 patterns when the absolute value is not converted. , And can be further reduced to four patterns. Therefore, the circuit configuration can be simplified, that is, the circuit scale can be reduced and the control can be easily performed.

Accordingly, a clock capable of detecting a phase error with a high probability, obtaining a clock phase error signal used for phase correction of a clock recovery circuit, and satisfying a low C / N clock recovery performance. A phase error detection circuit is obtained.

(Embodiment 3) FIG. 10 shows a receiver for demodulating quadrature amplitude modulation, for example, a QPSK modulation signal in an application of the above embodiment.

Since the QPSK modulated signal is composed of an I signal and a Q signal, an error operation is performed on each of the I signal and the Q signal, and a phase error signal is output from each validity determination result. Basically, the configuration shown in FIG. 8 is prepared for two systems for the I signal and the Q signal. For the I signal system, the absolute value circuit 501, the phase error calculation circuit 1, It comprises a pattern determining circuit 502, a level determining circuit 3, and a validity determining circuit 4. For the Q signal system, an absolute value circuit 706 and a phase error calculating circuit 70
1, the pattern determination circuit 702, and the level determination circuit 70
3 and a validity determination circuit 704.

Here, the absolute value circuit 706 is the absolute circuit 50
1 and the phase error calculation circuit 701
And the pattern judgment circuit 702
The level judgment circuit 703 is the same as the level judgment circuit 3, and the validity judgment circuit 704 is the same as the validity judgment circuit 4.

This configuration further includes an averaging circuit 707, a selector 708, a delay circuit 709, and an IQ determination circuit 710. The averaging circuit 707 averages the error data from the I signal and the error data from the Q signal. The averaging circuit 707 receives the outputs of the phase error calculation circuit 1 and the phase error calculation circuit 701, and calculates the average value. To the selector 708.

The selector 708 receives the output of the phase error calculation circuit 1, the output of the phase error calculation circuit 701, the output of the averaging circuit 707, and the output of the delay circuit 709, and selects one of these outputs by the IQ determination circuit 710. The signal is selected and output.

The IQ judging circuit 710 determines whether the two systems are based on the validity judgment result of the I signal system output from the validity judging circuit 4 and the validity judgment result from the Q signal system output from the validity judging circuit 704. In the case of "valid", the averaging circuit 707
And the output of the phase error calculation circuit 1 when only the validity determination result of the I signal system is “valid”, and the phase output when only the validity determination result of the Q signal system is “valid”. A selection signal is generated so as to select the output of the error calculation circuit 701 and the output of the delay circuit 709 when both the I signal system and the Q signal system are “invalid”, and the selection signal is provided to the selector 708. is there.

The delay circuit 709 delays the output of the selector 708 by one clock and outputs it to the selector 708 again to obtain a phase error signal delayed by one clock. Therefore, although the third embodiment does not have a hold circuit, the delay circuit 709 and the selector 708 play the role of the hold circuit in the second embodiment.

In this device having such a configuration, the I signal sampled at the reproduction clock timing is input from the input terminal 6, and the Q signal sampled at the reproduction clock timing is input from the input terminal 705.

Then, the input I signal is branched to an absolute value circuit 501 and a pattern determination circuit 502.
The input Q signal is branched to an absolute value circuit 706 and a pattern determination circuit 702.

Then, the absolute value circuit 501 of the I signal system to which the I signal has been input performs the absolute value conversion of the input signal, and then supplies it to the phase error calculation circuit 1 and the level determination circuit 3. Therefore, the phase error calculation circuit 1 and the level determination circuit 3 are provided with the absolute value of the code pattern of the input signal.

The level determination circuit 3 detects whether the absolute value of the input signal level is larger than the threshold value supplied from the threshold value input terminal 7. Here, since the phase error is calculated using “4 samples”, it is determined in this level determination that consecutive “4 samples” are simultaneously larger than the threshold. The determination result is supplied to the validity determination circuit 4.

The pattern determination circuit 502 determines whether the I signal which is a direct input signal from the input terminal 6 is "4".
The code pattern of the sample is determined. The determination result is supplied to the phase error calculation circuit 1 as a coefficient switching signal for the phase error calculation, and the determination is made to determine whether the pattern is effective for the error calculation. , Is also supplied to the validity determination circuit 4.

The validity determination circuit 4 determines whether the pattern determination result and the level determination result are simultaneously satisfied. That is, when the code pattern of consecutive "4 samples" matches the pattern in which the phase error calculation can be performed, and the signal amplitude is larger than a predetermined threshold value, it is determined as "valid". If the above two determinations are not satisfied at the same time, it is determined to be “invalid”, and the “invalid” determination signal is used as a hold signal by the IQ determination circuit 7.
Supply 10

On the other hand, the phase error calculation circuit 1 performs an error calculation in accordance with the code pattern of the input signal that has been converted into an absolute value, and outputs the I error data (error calculation result of the I signal system) as the calculation result to an averaging circuit 707. And to the selector 708. The averaging circuit 707 outputs the result of averaging the Q error data (error calculation result of the Q signal system) from the phase error calculation circuit 701 for the Q signal system, and supplies the result to the selector 708.

On the other hand, the absolute value circuit 706 of the Q signal system to which the Q signal is input performs the absolute value conversion of the input signal, and then supplies the converted signal to the phase error calculation circuit 701 and the level determination circuit 703. Therefore, the phase error calculation circuit 701 and the level determination circuit 703 are provided with the absolute value of the code pattern of the input signal.

The level determination circuit 703 detects whether the absolute value of the input signal level is larger than the threshold value supplied from the threshold value input terminal 7. Here, since the phase error is calculated using “4 samples”, it is determined in this level determination that consecutive “4 samples” are simultaneously larger than the threshold value. The determination result is supplied to the validity determination circuit 4.

The pattern determination circuit 702 determines the code pattern of “4 samples” for the Q signal which is a direct input signal from the input terminal 705. The determination result is supplied to the phase error calculation circuit 701 as a coefficient switching signal for the phase error calculation, and is also supplied to the validity determination circuit 704 to determine whether the pattern is valid for the error calculation. You.

The validity judging circuit 704 judges whether the pattern judgment result and the level judgment result are simultaneously satisfied. That is, when the code pattern of consecutive "4 samples" matches the pattern in which the phase error calculation can be performed, and the signal amplitude is larger than a predetermined threshold value, it is determined as "valid". If the above two determinations are not satisfied at the same time, it is determined to be “invalid”, and the “invalid” determination signal is used as a hold signal by the IQ determination circuit 7.
Supply 10

On the other hand, the phase error calculation circuit 701 performs an error calculation according to the code pattern of the input signal that has been converted into an absolute value, and Q error data (error calculation result of the Q signal system) as the calculation result is averaged. 707 and selector 708
To supply. The averaging circuit 707 outputs the result of averaging the I error data (the error calculation result of the I signal system) from the I signal system phase error calculation circuit 1, if any.
This is given to the selector 708.

The IQ decision circuit 710 to which the validity decision result of the I error data and the validity decision result of the Q error data are supplied,
The validity determination is performed, and a switching signal corresponding to the determination result is output to the selector 708.

That is, when the decision of the IQ decision circuit 710 is "valid only for the I signal", the I error data from the phase error calculation circuit 1 is selected so as to select the error data from the I signal. When the determination in 710 is “valid only for the Q signal”, the Q error data from the phase error calculation circuit 701 is selected to select error data from the Q signal, and the determination in the IQ determination circuit 710 is “I signal, When both the Q signals are invalid, the output of the delay circuit 709 is selected so as to select the error data one clock before, and the IQ determination circuit 710
Is "Either I signal and Q signal are valid"
The output of the averaging circuit 707 is selected so as to select the average data of the error data from the signal and the error data from the Q signal, and the output is used as a clock phase error signal at the output terminal 711.
It works to output to.

That is, the system of the third embodiment is provided with error calculation and validity determination functions for the I signal system and the Q signal system, respectively, and the averaging circuit 707 uses error data from the I signal and error data from the Q signal. The data is averaged and supplied to the selector 708. The selector 708 is also supplied with error data from the I signal, error data from the Q signal, and a phase error signal obtained by delaying the output of the selector 708 by one clock. The IQ determination circuit 710 outputs a switching signal to the selector 708 based on the validity determination result from the I signal and the validity determination result from the Q signal. When the validity determination is only the I signal, error data from the I signal is output. Is selected, and when the validity determination is only the Q signal, error data from the Q signal is selected.
When both Q signals are "invalid", a phase error signal delayed by one clock is selected. When both I and Q signals are "valid", error data from I signal and error data from Q signal are selected. The average is selected and output as a clock phase error signal. Then, the clock phase error signal is used as a phase control signal for correcting the phase shift of the reproduced clock, the phase control of the clock recovery circuit is performed, and the phase shift of the reproduced clock is corrected corresponding to the phase control signal. I did it. With this, QPS
The phase error detection accuracy can be further improved in the K system.

Note that the present invention is not limited to the QPSK system, and it is needless to say that the present invention can be applied to modulation systems such as the BPSK system and the 8PSK system.

[0106]

As explained above, according to the present invention,
Since it is possible to greatly increase the number of input patterns for which the phase error can be calculated, it is possible to greatly improve the clock reproduction performance. Therefore, a phase error can be detected with a high probability, a clock phase error signal used for phase correction of the clock recovery circuit can be obtained, and clock recovery performance at a low C / N can be satisfied. A circuit and a clock phase error detection method can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a clock phase error detection circuit according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a setting example of a threshold value of a level determination circuit used in the device of the present invention.

FIG. 3 is a block diagram illustrating a configuration example of a phase error calculation circuit used in the device of the present invention.

FIG. 4 is a diagram for explaining an operation example of the clock phase error detection circuit of the present invention.

FIG. 5 is a diagram illustrating a correspondence between a pattern of an input signal of the phase error calculation circuit of the present invention and a filter coefficient.

FIG. 6 is a diagram for explaining a pattern of an input signal.

FIG. 7 is a diagram for explaining a pattern of an input signal in which a clock phase error cannot be detected at all in the related art.

FIG. 8 is a block diagram illustrating another embodiment of the clock phase error detection circuit of the present invention.

FIG. 9 is a diagram illustrating a correspondence between an input pattern of a phase error calculation circuit and a filter coefficient according to another embodiment of the present invention.

FIG. 10 is a block diagram showing an example of a clock phase error detection circuit of the present invention when applied to quadrature detection output.

FIG. 11 is a diagram for explaining a conventional technique.

FIG. 12 is a diagram illustrating an example of an eye pattern.

FIG. 13 is a diagram for explaining a conventional technique.

FIG. 14 is a diagram schematically showing a conventional clock phase error detection method.

FIG. 15 is a diagram schematically showing a conventional clock phase error detection method, and is a diagram for explaining a pattern of an input signal for which a clock phase error cannot be detected.

[Explanation of symbols]

1, 701... Phase error calculation circuit, 2, 502, 702.
Pattern determining circuit, 3,703 ... level determining circuit, 4,
704: validity judgment circuit, 5: hold circuit, 501, 7
06 ... absolute value circuit, 707 ... average circuit, 708 ... selector, 709 ... delay circuit, 710 ... IQ judgment circuit.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Masaki Nishikawa 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa F-term in Toshiba Multimedia Engineering Laboratory (reference) 5J106 BB02 CC46 CC58 DD13 DD44 EE01 EE05 EE15 FF02 JJ02 KK05 5K004 AA05 FA03 FA05 FA06 FG02 FH08 FJ14 5K047 AA06 EE02 GG09 MM33 MM38 MM60

Claims (7)

[Claims] 1. A clock phase error detection circuit for obtaining a clock phase error signal for correcting a reproduced clock phase used in a circuit for reproducing a clock synchronized with a predetermined phase from a band-limited pulse code signal. Determining a pattern by detecting a code pattern of a signal obtained by sampling with the clock, and obtaining a clock phase error signal by a predetermined phase error calculation from the determined code pattern and the signal obtained by sampling. A clock phase error detection circuit comprising: a phase error calculation unit. 2. The clock phase error detection circuit according to claim 1, wherein the phase error calculation in the phase error calculation means is performed for four consecutive symbols. 3. The phase error calculator according to claim 1, wherein the phase error calculator is configured to switch the coefficient of the FIR filter in accordance with the detected code pattern. Clock phase error detection circuit. 4. A clock phase error detecting circuit for obtaining a clock phase error signal for correcting a reproduced clock phase used in a circuit for reproducing a clock synchronized with a predetermined phase from a band-limited pulse code signal, wherein the pulse code signal Judgment means for detecting a code pattern of a signal obtained by sampling with the clock to determine a pattern, an absolute value conversion means for converting a signal obtained by sampling the pulse code signal with the clock to an absolute value, Clock phase error detection, comprising: a phase error calculation means for obtaining a clock phase error signal by a predetermined phase error calculation from the code pattern determined by the determination means and the signal whose absolute value is converted by the absolute value conversion means. circuit. 5. A level determining circuit for detecting that a band-limited pulse code signal is larger than a predetermined amplitude, wherein the phase error calculation is performed when the pulse code signal is larger than a predetermined amplitude. The clock phase error detection circuit according to claim 1, wherein the clock phase error detection circuit performs: 6. The method according to claim 1, wherein the phase error calculation is performed on each of the I signal and the Q signal, and a value obtained by averaging the respective phase error calculation results is used as a phase error detection signal.
A clock phase error detection circuit according to any one of claims 1 to 5. 7. When reproducing a clock synchronized with a predetermined phase from a band-limited pulse code signal, a code pattern of a signal obtained by sampling the pulse code signal by the clock is detected and pattern determination is performed. A phase error is determined by a predetermined operation from the determined code pattern and the signal obtained by sampling, and the determined phase error is used for phase correction of clock recovery.