JP2000206209A - Test system - Google Patents

Abstract

(57) [Summary] [PROBLEMS] An LSI design with a large gate scale is divided into functionally integrated modules, and is performed in module units. In this case, it is necessary to create a plurality of test patterns for verifying whether each module and the entire LSI operate correctly, and there is a problem in that creating the test patterns requires a lot of man-hours. In a test system for verifying an entire LSI, a mechanism for applying a test pattern converted to a serial format to a module is provided in the LSI, and a parallel-type test pattern used for module verification of the LSI is provided on a test bench. A mechanism for converting the simulation pattern into a serial form, inputting the result to a module, converting the simulated result into a parallel form, and comparing the simulation result of the module verification with the simulation result of the LSI is provided.
Divert to the whole verification.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test system for verifying an entire LSI, and more particularly, to an LSI test system.
The test pattern used for verifying the modules constituting I is diverted to the verification of the entire LSI, thereby reducing the number of test pattern creation steps.

[0002]

2. Description of the Related Art As a gate size increases, an LSI design is not performed collectively for the entire LSI, but is divided into functionally integrated blocks (hereinafter, referred to as modules) and performed in module units. It is becoming. When the entire LSI is divided into modules and designed in module units, a test pattern for verifying whether the modules operate logically correctly and an L
Both test patterns are created to verify that the entire SI operates correctly.

FIG. 3 is an explanatory diagram of a conventional LSI logic verification. For example, as shown in FIG.
It is assumed that the configuration of I includes a module A and a module B.

In this case, first, as shown in FIG. 3B, the logic verification of the module A is performed by executing a simulation using the module A and the test pattern of the module A, and confirming the simulation result of the module A.

Next, as shown in FIG. 3C, a logic verification of the module B is performed by executing a simulation using the module B and a test pattern of the module B, and confirming a simulation result of the module B.

[0006] Finally, as shown in FIG.
The whole logic verification is performed by executing a simulation using the LSI and the LSI test pattern and confirming the simulation result of the LSI.

[0007]

As described above, according to the prior art shown in FIG. 3, when the entire LSI is divided into modules and the module is designed in units of modules, the module verification and the L
There is a problem in that two test patterns for verifying the entire SI must be created, and the creation of the test patterns requires many man-hours.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-described problems, and in a test system for verifying an entire LSI, a test pattern converted into a serial format is applied to a module to an LSI. The test bench converts the parallel test pattern used for the LSI module verification into a serial format, inputs it to the module, converts the simulated result into the parallel format, converts the simulation result into the parallel format, and simulates the module verification. A mechanism for comparing the result with the simulation result of the LSI is provided, and the test pattern used for module verification is diverted to the verification of the entire LSI, thereby reducing the number of test pattern creation steps.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a test system for verifying an entire LSI, a test circuit for applying a test pattern converted into a serial format to a module is provided in the LSI, and a test bench is used in a parallel format used for module verification. A test pattern format conversion unit for converting the test pattern into a serial format, a test pattern input / output control unit for inputting the test pattern to the test circuit unit and outputting the output of the module from the LSI, and a parallel format for the output from the module. An output format conversion unit to be converted, and a simulation result and L
A comparison unit for confirming that the output from the SI matches the test pattern used in the module verification and the simulation result output in the module verification are applied to the verification of the entire LSI. The man-hour for creating a test pattern for verifying the whole can be greatly reduced.

[0010]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, 1 is an LSI, 2 is a test bench, 3 is L
A simulator that reads SI1 and test bench 2 and verifies that LSI1 operates logically correctly.
Test patterns 5 used for verifying the modules constituting the SI1 are simulation results output by the verification of the modules constituting the LSI1.

The LSI 1 is provided with a test circuit section 11 for applying a test pattern converted into a serial format to the modules A and B.

The test bench 2 converts a parallel test pattern used for module verification into a serial test pattern format conversion unit 21, inputs the test pattern to the test circuit unit 11, and outputs the output of the module. A test pattern input / output control unit 22 that outputs from the LSI, an output format conversion unit 23 that converts the output from the module to a parallel format, and a check that the simulation result output from the module verification matches the output from the LSI. And a comparing unit 24 for checking.

FIG. 2 shows a processing flowchart of an embodiment of the present invention. Hereinafter, the operation will be described according to this flow. This process is a process after the LSI and the test bench are read into the simulator.

Step S201: A test pattern is input to a test bench.

Step S202: The input test pattern is converted from a parallel format to a serial format.

Step S203: Test clock (TC
K signal), and outputs the value of the output pin of the module to the test circuit section.

Step S204: The test pattern converted into the serial format is input to the test circuit section in synchronization with the test clock (TCK signal). Note that the test pattern is input from the IN terminal. At the same time, the value of the output pin of the module output to the test circuit section is output from the OUT terminal as a simulation result.

Step S205: Test clock (TC
K signal) and outputs the value of the test circuit section to the input pin of the module.

Step S206: Simulation is performed only for one cycle.

Step S207: It is determined whether all test patterns have been simulated. If all the simulations have been performed, the process proceeds to step S208. If all the simulations have not been performed, the process returns to step S203.

Step S208: Test clock (TC
K signal), and outputs the value of the output pin of the module to the test circuit section.

Step S209: The value of the output pin of the module output to the test circuit is output from the OUT terminal as a simulation result. The input from the IN terminal is optional.

Step S210: The simulation result is converted from a serial format to a parallel format.

Step S211: The simulation result output in the module verification is input to the test bench as an expected value pattern.

Step S212: The simulation result processed in step S210 is compared with the expected value pattern.

As a result, the test pattern used for verifying the modules constituting the LSI can be used for verifying the entire LSI.

[0027]

The present invention is embodied in the form described above, and has the following effects.

Since the test pattern used for verifying the module can be used for verifying the entire LSI, the number of test pattern creation steps can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of an embodiment of the present invention.

FIG. 2 is a processing flowchart of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a conventional LSI logic verification.

[Explanation of symbols]

 Reference Signs List 1 LSI 2 Test bench 3 Simulator 4 Test pattern 5 Simulation result 11 Test circuit section 21 Test pattern format conversion section 22 Test pattern input / output control section 23 Output format conversion section 24 Comparison section

Claims (1)

[Claims] In a test system for verifying an entire LSI, an LSI (1) is provided with a test circuit section (11) for applying a test pattern converted into a serial format to a module, and a test bench (2) is provided on the module. A test pattern format conversion unit (21) for converting a parallel format test pattern used for the verification into a serial format, a test pattern input to the test circuit unit (11), and a test pattern input to output a module output from the LSI. Output control unit (2
2), an output format conversion unit (23) for converting the output from the module into a parallel format, and a comparison unit (24) for confirming that the simulation result output from the module verification matches the output from the LSI. The test pattern used for module verification and the simulation result output during module verification are
A test system characterized by being used for overall verification.