JP2000209505A - White spot signal level suppression device for solid-state imaging device - Google Patents

Abstract

(57) [Object] To provide a white flaw signal level suppressing device that discriminates a white flaw signal from a video signal output from an imaging element, suppresses a white flaw signal level, and improves image quality. In a level suppression circuit, a video signal output from an image sensor is a prominent signal having a higher level than previous and subsequent signal levels and a width corresponding to a set number of pixels to be suppressed (suppression). (The number of pixels in the horizontal direction) is determined to be a white defect signal, and the signal level of the protruding portion is suppressed to the previous and subsequent signal levels. Further, the control circuit 12 controls the level suppression circuit 6 according to the charge accumulation time of the image sensor 1. The discrimination circuit 11 calculates a difference between the current video signal and the video signal one frame or one field before with respect to the video signal from the image sensor 1, and determines whether or not the video signal is a white defect signal based on the difference value. Is configured to be able to be determined.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention suppresses the signal level of white spots in a video signal output from an image sensor,
The present invention relates to a white spot signal level suppression device of a solid-state imaging device for improving image quality.

[0002]

2. Description of the Related Art Conventionally, a CCD (Charge Coupled Device) is used in a solid-state imaging device used for a video camera or the like.
An imaging device such as an electronic device is configured by arranging a large number of photoelectric conversion elements such as photodiodes and includes a photoelectric conversion unit that accumulates photoelectrically converted charges and a transfer unit that transfers the accumulated charges in time series. In the photoelectric conversion unit, electric charges corresponding to the amount of light are accumulated in the potential well of each pixel. The transfer unit transfers the accumulated charges to the horizontal transfer unit in units of rows (for each line) and outputs the charges in chronological order. By performing this operation for all rows, data for one screen is output.

By the way, white spots may occur in a luminance signal of a video signal output from an image pickup device. Such white flaws occurring in the image sensor appear as an image due to a flaw in the image sensor itself, and always occur in the same pixel. As the charge accumulation time in the photoelectric conversion unit becomes longer, the signal level of the white flaw also increases, so that the flaw becomes conspicuous and the image quality deteriorates.

Therefore, when the sensitivity is to be increased by long-time exposure, white flaws become conspicuous and the image quality deteriorates.

[0005]

As described above, the conventional solid-state imaging device has a problem that if the charge accumulation time is prolonged due to long-time exposure, white flaws become conspicuous and the image quality deteriorates. .

In view of the above-mentioned problems, the present invention has been developed for a solid-state imaging device which determines a white flaw signal from a video signal output from an image sensor, suppresses the signal level of the white flaw, and improves image quality. It is an object of the present invention to provide a flaw signal level suppressing device.

[0007]

According to the first aspect of the present invention, there is provided a white defect signal level suppressing apparatus for a solid-state image pickup device, wherein a video signal output from an image pickup device has a higher level than a preceding and succeeding signal level. If the signal of the protruding portion is a signal having a width equal to or smaller than the set number of pixels (the number of pixels in the horizontal direction to be suppressed), it is determined that the signal is a white defect, A level suppression circuit that suppresses the signal level of the protruding portion to the signal level before and after,
A control circuit for controlling a width corresponding to the number of pixels to be suppressed by the level suppression circuit in accordance with the accumulation time of long-time exposure of the imaging element.

According to a second aspect of the present invention, there is provided a solid-state image pickup device for suppressing a white spot signal level in a solid-state image pickup device, wherein a current image signal and one frame or one image signal are output from an image sensor.
A discriminating circuit for taking a difference from the video signal before the field and discriminating whether or not the video signal is a signal of a white defect based on the difference value, and the discriminating circuit determines that the signal is a signal of a white defect. The video signal is a protruding signal whose level is higher than the preceding and succeeding signal levels, and the signal of the protruding portion has a width corresponding to a predetermined number of pixels (the number of pixels in the horizontal direction to be suppressed). In the case of the following signals, a level suppression circuit is provided which determines that the signal is a white flaw signal and suppresses the signal level of the protruding portion to the signal levels of the preceding and following parts.

According to a third aspect of the present invention, there is provided a white defect signal level suppressing device for a solid-state image pickup device, wherein a current image signal and one frame or one image signal are output from an image pickup device.
A discriminating circuit for discriminating whether or not the video signal is a white flaw signal based on a difference value between the video signal before the field and a video signal which is discriminated as a white flaw signal by the discrimination circuit; Is a protruding signal whose level is higher than the previous and subsequent signal levels, and the signal of the protruding portion is a signal having a width equal to or less than a predetermined number of pixels (the number of horizontal pixels to be suppressed). In this case, the signal is determined to be a white flaw signal, and the level suppression circuit suppresses the signal level of the protruding portion to the previous and next signal levels, and the level suppression circuit according to the accumulation time of long-time exposure of the image sensor. And a control circuit for controlling the width corresponding to the number of pixels to be suppressed.

According to a fourth aspect of the present invention, in the white defect signal level suppressing device for a solid-state image pickup device according to the first or third aspect, the control circuit is configured such that the level suppressing circuit increases as the accumulation time of the image sensor increases. The width corresponding to the number of pixels to be suppressed is increased.

According to the fourth aspect of the present invention, if the accumulation time is long, the signal level of the white defect becomes high, and at the same time, the level of the pixel surrounding the flaw of one pixel becomes high. Increase the width by a few minutes, and shorten the width if the accumulation time is short.

According to a fifth aspect of the present invention, in the white defect signal level suppressing device for a solid-state image pickup device according to the second or third aspect, the discriminating circuit includes a current video signal and a video signal one frame or one field before. If the difference value is smaller than the set reference value, it is determined as a white flaw, and if it is larger than the reference value, it is determined that it is not a white flaw.

In the first, third, and fourth aspects of the present invention, the level suppression circuit suppresses the signal level of the protruding portion, and has a width corresponding to a predetermined number of pixels to be suppressed (the number of pixels in the horizontal direction to be suppressed). Is controlled according to the length of the accumulation time. That is, when the accumulation time is long, the width corresponding to the number of pixels whose level is suppressed is increased, and when the accumulation time is short, the width corresponding to the number of pixels whose level is suppressed is reduced, so that the optimum white defect signal level is suppressed.

According to the second and third aspects of the present invention, it is determined whether or not there is a white flaw according to the magnitude of the difference value between the current video signal and the video signal one frame before or one field before, and whether or not there is a white defect is determined. In the case where there is a flaw, the level of the white signal is suppressed by a level suppression circuit.

[0015]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a white spot signal level suppressing device of a solid-state imaging device according to an embodiment of the present invention.

In FIG. 1, a picked-up video signal is converted into an electric signal by an image pickup device 1 and input to an AGC circuit 3 via a sample-and-hold circuit (S / H circuit) 2. The S / H circuit 2 samples and holds the electric signal for each pixel generated by the photoelectric conversion in the image sensor 1 using a clamp pulse to extract a signal portion. The extracted signal component is amplified at a predetermined gain by the AGC circuit 3, converted to a digital signal by the A / D converter 4, subjected to signal processing such as gamma and detail processing by the signal processing circuit 5, and processed into a video signal. Is output as

The video signal output from the signal processing circuit 5 is supplied to the level suppression circuit 6 in the level suppression circuit block 14.
Is converted into an analog video signal by the D / A converter 7,
The signal is NTSC-encoded by the encoder 8 and added with various signals such as a synchronization signal and output.

The level suppression circuit block 14 is a block for detecting and suppressing a signal of a white defect, and includes a level suppression circuit 6, a frame memory 9 as a delay unit, a subtracter 10, a discriminating circuit 11, and a control circuit 12. It is configured.

The luminance signal of the video signal output from the signal processing circuit 5 is supplied to the level suppression circuit block 14 as an input. Then, the input luminance signal becomes an input to the level suppression circuit 6 and the frame memory 9 and also becomes a subtraction input of the subtracter 10. The output of the frame memory 9 is a video signal delayed by one frame period,
0 is the subtracted input. A subtraction output of the subtractor 10 is an input of the discrimination circuit 11.

In the level suppression circuit 6, the signal of the protruding portion having a higher level than the level of the preceding and succeeding signals, and the signal of the protruding portion corresponds to the number of pixels set to be controllable by the control circuit 12. If the signal is smaller than the width (the number of pixels in the horizontal direction to be suppressed), it is determined on a pixel-by-pixel basis that the signal is a white defect signal, and the signal level of the protruding portion is suppressed to the previous and next signal levels. Thus, the level of the white flaw signal is suppressed. As described above, the level suppression circuit 6 suppresses the signal level of the white defect according to the control signal input from the control circuit 12. However, in the above-described level suppression circuit 6, since the level suppression is controlled by a change in level between adjacent pixels, a change in video level may be erroneously recognized as a white defect.

Therefore, in the present embodiment, a frame memory 9, a subtractor 10, and a discriminating circuit 11 are further provided, and the magnitude of the difference between the current video signal and the video signal one frame before is provided to the discriminating circuit 11. By comparing with a reference value and using the result of the comparison, the probability of confirming a white defect is increased (no misidentification). Only when the comparison result (discrimination signal) outputted from the discrimination circuit 11 is not a change in the video level but a signal of a white defect, the level suppression circuit 6 protrudes with a higher level than the previous and subsequent signal levels. It is possible to suppress the signal level of the portion that has been changed to the level of the previous and subsequent signals.

The discrimination circuit 11 outputs a discrimination signal as to whether or not the signal is a white defect signal in accordance with the subtraction result of the subtractor 10. Since the signal of the white defect always occurs at the same pixel and has a constant level, a difference value (subtraction value of the subtractor 10) between the current video signal and the video signal delayed by one frame by the frame memory 9 is set. If the value is smaller than the reference value, it is determined that the image is a white defect. If the value is larger than the reference value, it is determined that the image is not a white defect. If the difference value is larger than the reference value, it is determined that the difference is the video change amount between the previous video signal and the current video signal, and is not a white defect. Conversely, if the difference value is smaller than the reference value,
Assuming that the level is almost the same between the previous video signal and the current video signal, white flaws are generated. Then, the signal level of the pixel signal determined to be not a white defect by the determination circuit 11 can be suppressed by the level suppression circuit 6.

The control circuit 12 uses the level suppression circuit 6 to convert the white defect signal to a certain number of pixels according to the length of the pulse signal indicating the charge accumulation time (ie, exposure time) of the image pickup device 1 input to the terminal 13. A control signal indicating whether or not the level is to be suppressed is output. Control is performed so that the width (the number of pixels in the horizontal direction to be suppressed) by the number of pixels to be suppressed by the level suppression circuit 6 is increased as the charge accumulation time becomes longer. This is because the longer the charge accumulation time of the image sensor 1, the higher the signal level of white flaws, and the flaw of one pixel increases the level of surrounding pixels. Therefore, the control circuit 12 increases the width of the number of pixels set by the level suppression circuit 6 if the accumulation time is long, and increases the width of the level suppression circuit 6 if the accumulation time is short.
Is controlled so as to shorten the width corresponding to the number of pixels set in.

FIG. 2 is a block diagram showing a configuration example of the level suppression circuit 6, and FIGS. 3 and 4 are timing charts of the operation of FIG.

In FIG. 2, a level suppression circuit 6 includes an input terminal 61 for a video signal (pixel signal) and a minimum value selection circuit 6.
2, a delay circuit 63, a minimum value selection circuit 64, a maximum value selection circuit 66, a switch 67, a control signal input terminal 68 from the control circuit 12, and a determination signal input terminal 69 from the determination circuit 11. And an output terminal 70.

A video signal (pixel signal) is input to the input terminal 61 from the signal processing circuit 5 and supplied to one input terminal of the minimum value selection circuit 62 and the delay circuit 63. The delay circuit 63 is a circuit for giving a time width of a predetermined number of pixels (the number of pixels in the horizontal direction to be suppressed), for example, a time delay of one pixel to the input video signal. The setting of ()) can be changed by a control signal from the input terminal 68. The minimum value selection circuit 62 is a circuit that selectively outputs the smaller one of the two input signals, and outputs the signal of that level when the two input signals have the same level. The delay output from the delay circuit 63 is supplied to the other input terminal of the minimum value selection circuit 62 and to one input terminal of the minimum value selection circuit 64 and the delay circuit 65. The delay circuit 65 has a delay time similar to that of the delay circuit 63, and its delay output is supplied to the other input terminal of the minimum value selection circuit 64. Similarly to the minimum value selection circuit 62, the minimum value selection circuit 64 selectively outputs the smaller one of the two input signals, and outputs the signal of the level when the two input signals are at the same level. Circuit. Minimum value selection circuit 62
And the selected output of the minimum value selection circuit 64 are supplied to two input terminals of the maximum value selection circuit 66. The maximum value selection circuit 66 is a circuit that selectively outputs the larger one of the two input signals, and outputs the signal of that level when the two input signals have the same level. The selected output of the maximum value selection circuit 66 is supplied to one input terminal P of the switch 67, and the other input terminal Q of the switch 67 is supplied with the delayed output from the delay circuit 63. The switch 67 receives a determination signal from the input terminal 69 (that is, determines whether or not the signal determined by the determination circuit 11 is a white defect).
If it is a white defect discrimination signal, the input terminal P, that is, the maximum value selection circuit 6
6 is selected, and if it is determined that the signal is not a white defect, the input terminal Q, that is, the output of the delay circuit 63 is selected and output from the output terminal 70.

Next, the operation of FIG. 2 will be described. Here, it is assumed that the delay time width of the delay circuits 63 and 65 is set to one pixel by the control circuit 12.

FIG. 3 is a timing chart when the width of the input video signal from the input terminal 61 is one pixel (ie, when the width of the protruding signal whose level is higher than the preceding and succeeding signal levels is one pixel). . When the width of the input video signal is one pixel as shown in FIG. 3 (a), it is delayed by one pixel by the delay circuits 63 and 65, respectively, as shown in FIGS. 3 (b) and 3 (c). The minimum value selection circuit 62 selects the smaller one of the signals (a) and (b) to produce the output of FIG. The minimum value selection circuit 64 selects the smaller one of the signals (b) and (c) to produce the output shown in FIG. Then, the maximum value selection circuit 66 selects the larger one of the signals (d) and (e) to produce the output of FIG. Therefore, the delay circuit 63,
When the delay time of 65 is set to one pixel and the width of the input video signal is one pixel (that is, when it is equal to or less than the set value), it is determined that the signal of one pixel is a white defect,
The protruding signal level of one pixel can be suppressed to the preceding and following signal levels and supplied to the input terminal P of the switch 67.

FIG. 4 is a timing chart when the width of the input video signal from the input terminal 61 is two pixels. When the width of the input video signal is two pixels as shown in FIG. 4A, the width is delayed by one pixel in each of the delay circuits 63 and 65.
(c). In the minimum value selection circuit 62, the signal (a)
, (B) results in the output of FIG. 4 (d). In the minimum value selection circuit 64, the signals (b),
By selecting the smaller one of (c), the output of FIG. 4 (e) is obtained. Then, in the maximum value selection circuit 66, the signal (d) and
By selecting the larger one of (e), the output of FIG. 4 (f) is obtained (this is a signal similar to that of FIG. 4 (b)). Therefore, if the delay time of the delay circuits 63 and 65 is set to one pixel and the width of the input video signal is two pixels (that is, exceeds the set value), the signal of these two pixels is It is determined that there is no change (that is, a change in image), and the signal level can be supplied to the input terminal P of the switch 67 without suppressing the protruding signal level of two pixels.

As described above with reference to FIGS. 3 and 4, white defect determination based on the width of a predetermined number of pixels is performed by the circuit portion 6A indicated by the broken line frame in FIG. The protruding signal level can be suppressed to the preceding and following signal levels and supplied to the input terminal P of the switch 67.

In the switch 67, in addition to the white defect determination and suppression by the circuit portion 6A shown by the broken line frame in FIG. 2, the above-described determination circuit (the current video signal and the video signal one frame or one field before, The input terminal P is selected only when the determination result of the circuit 11 determines that the video signal is a white defect based on the difference value, and determines that the video signal is a white defect. At this time, the maximum value selection circuit 6
From the output terminal 70, the output (f) in which white scratches are suppressed is
/ A converter 7. If the result of the determination by the determination circuit 11 is not a white defect, the input terminal Q is selected. At this time, the output (b) from the delay circuit 63 where white defects are not suppressed is output from the output terminal 70 to the D / A converter. Output to the container 7. The switch 67 can increase the certainty of white spot determination and suppression.

FIG. 5 shows a circuit portion 6A indicated by a broken-line frame in FIG.
2 schematically shows the level suppression operation. FIG. 5A shows a case where the high-level protruding signal in the input video signal is equal to or smaller than the width of the number of pixels set by the control circuit 12.
This shows a state in which a protruding signal portion is removed as an output. FIG. 5B shows a state in which the protruding signal having a high level in the input video signal is output as it is without being removed when the protruding signal portion is larger than the width of the number of pixels set by the control circuit 12. Is shown.

FIGS. 6A and 6B show examples of control characteristics of the control circuit 12, and show two examples of changes in the width of the number of pixels set in accordance with the value of the input accumulation time. ing. FIG.
FIG. 6A shows a control characteristic in which the width of the number of pixels whose level is suppressed increases linearly as the charge storage time (exposure time) increases, and FIG. 6B shows the charge storage time (exposure time). It shows a control characteristic in which the width of the number of pixels whose level is suppressed increases stepwise with an increase.

In the above-described embodiment, the circuit for determining the signal level of white spots using the frame correlation has been described. However, by using a field memory in place of the frame memory 9, the field correlation can be utilized. Then, a circuit for determining the signal level of the white defect may be configured.

In the embodiment of FIG. 1, a case is described in which a circuit for determining the signal level of a white defect using a frame correlation is used (that is, 1 is used as a delay unit in the level suppression circuit block 14). Although a frame memory for delaying a frame is used), when the solid-state imaging device is used in a high sensitivity mode described later, a field memory for delaying one field is used instead of the frame memory as delay means. You may.

As described above, in the high sensitivity mode of the solid-state imaging device, a circuit using a field correlation can be used as the level suppression circuit block 14. Hereinafter, the normal sensitivity mode and the high sensitivity mode will be described.

That is, in the white defect signal level suppressing device in the solid-state image pickup device, a white defect component is suppressed from a video signal obtained on the basis of the charge accumulated and exposed in the photoelectric conversion unit of the image pickup element every field period ( In the normal sensitivity mode, the video signal has a correlation between the frames (the odd field and the even field constituting one frame are interlaced, so that the correlation is small and the correlation between the frames is relatively small). Utilizing that, the difference between the currently input video signal and the video signal delayed by one frame is extracted to extract a change component between frames, and the extracted component is supplied to the determination circuit 11.

Further, in the white defect signal level suppressing device in the solid-state image pickup device, the exposure charge is based on the charge accumulated in the photoelectric conversion portion of the image pickup element every n times (n is a natural number) of one frame period. In the case of suppressing white spot components from a video signal obtained by performing interpolation on a non-existing field (in the high sensitivity mode), the field is always fixed to one of the odd field and the even field.
Utilizing the fact that video signals have correlation between fields, a difference component between frames is extracted by taking a difference between a currently input video signal and a video signal delayed by one field, and a discrimination circuit 11 to suppress white flaws. In the case of the high sensitivity mode, it is also possible to extract a white defect component by calculating the difference between the current video signal and the video signal delayed by one frame.
That is, if a frame memory is used as the delay means, it can be applied to both the normal sensitivity mode and the high sensitivity mode.

Generally, in a solid-state imaging device such as a video camera, a CCD (Charge Coupled Device) is used as a solid-state imaging device.
ice) is used. The normal sensitivity mode and the high sensitivity mode will be described with reference to FIGS.

FIG. 7 is a diagram showing an example of the configuration of a CCD. The CCD shown in FIG. 7 includes a photoelectric conversion unit 21 that receives light from a subject and converts the light into an electric signal;
The signal charge accumulated in the field shift pulse (FS)
Vertical transfer unit 22 which is transferred in synchronization with
2 includes a horizontal transfer unit 23 in which signal charges for one screen transferred to one line are transferred for each line, and an output unit 24 for outputting the horizontally transferred signal charges from a terminal 25 for each pixel.

FIG. 8 shows a timing chart of the CCD output and the video output in the normal sensitivity mode of the video camera. The exposure time of the CCD video camera in the normal sensitivity mode is one field (1/60 s).

FIG. 8A shows an exposure time (one field), FIG. 8B shows a field shift pulse (FS) for reading signal charges from the photoelectric conversion unit 21 to the vertical transfer unit 22, and FIG. 8C.
8 shows a CCD output signal, and FIG. 8D shows a video output signal.

As shown in FIG. 8B, a field shift pulse is output to the CCD for each field.
Thus, the charges accumulated in the photoelectric conversion unit 21 for one field period (that is, the periods A, B, C, and D shown in FIG.
.. Are output as CCD output signals delayed by one field period as shown in FIG. 8 (c), which are further processed by signal processing means (signal processing circuit 5, encoder 8, etc.). The video signal is converted and output as shown in (d).

On the other hand, in a CCD video camera (or a frame dropping long exposure video camera) in the high sensitivity mode,
By increasing the exposure time from normal one field to 2, 4, 6,... Fields by thinning out the field shift pulse, high sensitivity is realized. Note that the change in the exposure time is made every two fields.
This is to prevent the jitter of the video output by fixing the odd field / even field (ODD / EVEN) of the signal charge to be read to any one.

Next, the high sensitivity mode operation by long-time exposure will be described with reference to FIG. FIG. 9 shows a timing chart of the CCD output and the video output in the high sensitivity mode of the video camera.

FIG. 9A shows an exposure time (two fields), FIG. 9B shows a field pulse for reading out signal charges from the photoelectric conversion unit 21 to the vertical transfer unit 22, and FIG. 9C shows a CCD output signal. 9 (d) shows a video output signal.

FIG. 9B shows an example in which a field shift pulse is output every two fields instead of every field. The CCD output signal is output every two fields as shown in FIG. This CCD output signal is 2
Since the charges accumulated and exposed during the field period 33 are output during the one-field period 31, a signal exposed for a long time can be obtained.

However, since there is no exposure signal output during the field period 32 following the field period 31, it is necessary to interpolate the field period 32 with the exposure signal of the field period 31 using the memory of the signal processing circuit 5 at the subsequent stage. In this way, long-time exposure is performed by the photoelectric conversion unit 21, and a video output signal shown in FIG. 9D with high sensitivity is obtained. The memory interpolation is performed by using a known method. For example, the signal immediately before the output of the exposure signal is lost is used as it is, or the signal before and after the output of the exposure signal is lost is obtained by interpolation (using the average value before and after).

Automatic control of the exposure time according to the brightness of the video output as shown in FIGS. 8 and 9 is called automatic sensitivity switching. In the automatic sensitivity switching, for example, the level of the integrated value or the peak value of the luminance signal is compared with two threshold values of light and dark, and when it is determined that the image is dark, the exposure time is set to 2 fields (1/30 s) and 4 fields. ,..., And when it is determined that the image is bright, the exposure time is reduced by two fields or only one field. That is, when the image is dark, a field shift pulse having an extended period of 2 field periods, 4 field periods,..., And when the image is bright, a field shift pulse having a period shortened by 2 field periods or a field shift pulse of 1 field period. Is supplied to the CCD.

FIG. 10 is a block diagram showing a white spot signal level suppressing device of a solid-state imaging device having an automatic sensitivity switching function according to another embodiment of the present invention.

10 is different from FIG. 1 in that an exposure time control circuit 15 and a CCD drive circuit 16 are provided to enable automatic sensitivity switching, while an exposure time control signal S4 corresponding to an accumulation time is supplied to a terminal 13. By doing so, it is possible to automatically set the number of pixels for white defect determination in accordance with the brightness of light from the subject. The luminance signal from the signal processing circuit 5 is led to the exposure time control circuit 15 and the level of the integrated value or the peak value of the luminance signal is set to 2 for light / dark.
An exposure time control signal S4 indicating the comparison result is generated and supplied to the CCD drive circuit 16.
The CCD drive circuit 16 outputs a field shift pulse (F
S) and a CCD driving pulse S5 including
The pulse period of the FS in the CCD drive pulse S5, that is, the amount of FS pulse thinning-out is controlled by the exposure time control signal S4. That is, when the exposure time control circuit 15 determines that the image is bright (in the normal sensitivity mode), the cycle of the FS is set to, for example, one field, the charge accumulation time of the photoelectric conversion unit of the image sensor 1 is set short, and the control is performed simultaneously. When the number of pixels set in the circuit 12 is also set small and it is determined that the image is dark (in the high sensitivity mode)
Means that the FS cycle is, for example, two fields and the image sensor 1
, The charge storage time of the photoelectric conversion unit is set to be long, and at the same time, the number of pixels set in the control circuit 12 is set to be large. The exposure time (FS pulse cycle) is set by the exposure time control circuit 15 as described above. When the image is dark, the field shift pulse having the extended period of 2 field periods, 4 field periods,. Is brighter, a field shift pulse having a period shortened by two field periods or a one-field period can be supplied to the imaging device (CCD). Alternatively, the sensitivity may be switched by enabling switching between two threshold values of light and dark. Further, an exposure time control circuit 1
If the exposure time control signal S4 from 5 indicates a dark image, the frame memory 9 can be switched to a field memory.

In accordance with the magnitude of the difference between the current video signal and the video signal delayed by one frame or one field by the discrimination circuit 11 described above, and the length of the charge storage time of the image sensor 1 by the control circuit 12, the level is suppressed. By controlling the circuit 6, it is possible to optimally suppress white spots.

In the above embodiment, the level control circuit is controlled in accordance with the difference between the current video signal from the image sensor and the video signal delayed by one frame or one field and the charge accumulation time of the image sensor. However, the present invention is not limited to the case where the control is performed in accordance with both the difference between the current video signal and the video signal delayed by one frame or one field and the charge accumulation time of the image sensor, and any one of these is controlled. The control may be performed by using. For example, the level of the white flaw signal may be suppressed by keeping the width of the number of pixels suppressed by the level suppression circuit constant without performing control by the accumulation time.

In the above embodiment, the white defect signal level suppressing device of the solid-state imaging device according to the present invention is not limited to a video camera, but also a white defect signal in a video device such as a VTR or a TV receiver. It can be applied to a level suppression device.

Furthermore, the solid-state imaging device according to the present invention can be used not only for video cameras but also for imaging devices for various purposes, such as medical imaging devices.

[0056]

As described above, according to the present invention, it is possible to discriminate a white flaw signal from a video signal output from an image pickup device, suppress the white flaw signal level, and improve image quality. Become. Further, white spot suppression control is performed in accordance with the difference value between the current video signal and the video signal delayed by one frame or field or the charge accumulation time of the image sensor,
The level of the white flaw signal can be suppressed by suppressing the level of the signal of the pixel determined to be a white flaw signal to levels before and after the signal. Further, since the level of the white flaw signal is suppressed in units of one pixel and in real time, it is possible to adapt to many flaws and newly generated flaws.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a white spot signal level suppression device of a solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a level suppression circuit.

FIG. 3 is a timing chart of the operation of FIG. 2;

FIG. 4 is a timing chart of the operation of FIG. 2;

FIG. 5 is a diagram schematically showing a level suppressing operation of a circuit portion 6A indicated by a broken line frame in FIG. 2;

FIG. 6 is a characteristic diagram showing an example of control characteristics of the control circuit 12.

FIG. 7 is a diagram showing an example of the configuration of a CCD.

FIG. 8: CCD in a normal sensitivity mode of a video camera
6 is a timing chart showing the timing of output and video output.

FIG. 9 is a timing chart showing timings of a CCD output and a video output in a high sensitivity mode of the video camera.

FIG. 10 is a block diagram showing a white spot signal level suppression device of a solid-state imaging device according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Image sensor 6 ... Level suppression circuit 9 ... Frame memory (delay means) 10 ... Subtractor 11 ... Judgment circuit 12 ... Control circuit 13 ... Storage time setting terminal 14 ... Level suppression circuit block

Continued on the front page (72) Inventor Kei Tashiro 1-9-2 Hara-cho, Fukaya-shi, Saitama Prefecture Inside the Toshiba Fukaya Plant (72) Inventor Masatoshi Okubo 1-9-1-2 Hara-cho, Fukaya-shi, Saitama Stock Company Inside the Toshiba Fukaya Plant (72) Inventor Akira 1-9-2 Hara-cho, Fukaya City, Saitama Prefecture Inside the Toshiba Fukaya Plant (72) Inventor Tetsuo Sakurai 3-3-9 Shimbashi, Minato-ku, Tokyo Toshiba Air・ F-term in bu E. Co., Ltd. (reference) 5C024 AA01 CA06 CA09 CA13 CA17 DA05 DA07 FA01 FA11 HA01 HA03 HA06 HA08 HA10 HA14 HA18 HA24

Claims (5)

[Claims] An image signal output from an image sensor is a protruding signal whose level is higher than the preceding and succeeding signal levels, and the signal of the protruding portion has a width corresponding to a predetermined number of pixels. If the signal is equal to or less than (the number of pixels in the horizontal direction to be suppressed), the signal is determined to be a white flaw signal, and a level suppression circuit that suppresses the signal level of the protruding portion to the previous and subsequent signal levels; And a control circuit for controlling a width corresponding to the number of pixels to be suppressed by the level suppression circuit in accordance with the accumulation time of the long-time exposure of the solid-state imaging device. 2. A difference between a current video signal and a video signal one frame or one field before in a video signal output from an image sensor, and the video signal is a white defect signal based on the difference value. A discriminating circuit for discriminating whether or not the video signal determined to be a white defect signal by the discriminating circuit is a protruding signal having a higher level as compared to the signal levels before and after, and the protruding signal If the signal of the portion is a signal having a width equal to or smaller than a predetermined number of pixels (the number of pixels in the horizontal direction to be suppressed), it is determined that the signal is a white defect, and the signal level of the protruding portion is increased or decreased. And a level suppression circuit for suppressing the signal level to the level of the white defect signal of the solid-state imaging device. And determining whether the video signal is a white defect signal based on a difference value between a current video signal and a video signal one frame or one field before by a video signal output from the image sensor. A discriminating circuit for discriminating, with respect to the video signal discriminated as being a signal of a white defect by the discriminating circuit, a protruding signal having a higher level compared with the signal levels before and after, and the signal of the protruding portion is If the signal is equal to or smaller than the set width of the predetermined number of pixels (the number of pixels in the horizontal direction to be suppressed), it is determined that the signal is a white flaw signal, and the signal level of the protruding portion is increased to the level of the preceding and following signals. A solid-state imaging device, comprising: a level suppression circuit for suppressing, and a control circuit for controlling a width corresponding to the number of pixels to be suppressed by the level suppression circuit in accordance with an accumulation time of long-time exposure of the imaging element. apparatus White flaw signal level suppressing device. 4. The control circuit according to claim 1, wherein the control circuit increases a width corresponding to the number of pixels to be suppressed by the level suppression circuit as the accumulation time of the image sensor increases. White defect signal level suppression device for solid-state imaging devices. 5. A discriminating circuit for discriminating a white defect if a difference value between a current video signal and a video signal of one frame or one field before is smaller than a set reference value, and white if the difference value is larger than the reference value. 4. The white flaw signal level suppression device for a solid-state imaging device according to claim 2, wherein it is determined that the flaw is not a flaw.