JP3989112B2 - White scratch signal level suppression device for solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a white scratch signal level suppressing device for a solid-state imaging device that suppresses the signal level of white scratches in a video signal output from an image sensor and improves image quality.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a solid-state imaging device used for a video camera or the like, an imaging element such as a CCD (Charge Coupled Device) is an array of a large number of photoelectric conversion elements such as photodiodes, and a photoelectric conversion unit that accumulates photoelectrically converted charges. And a transfer unit that transfers the accumulated charges in time series. In the photoelectric conversion unit, a charge corresponding to the amount of light is accumulated in the potential well of each pixel. The transfer unit transfers the accumulated charges to the horizontal transfer unit in units of rows (each line) and outputs them in time series. By performing this operation on all lines, data for one screen is output.
[0003]
Incidentally, white flaws may occur in the luminance signal of the video signal output from the image sensor. Such white scratches that occur in the image sensor appear as images due to scratches in the image sensor itself, and always occur at the same pixel. As the charge accumulation time in the photoelectric conversion unit becomes longer, the signal level of white scratches also increases, so that the scratches become conspicuous and the image quality deteriorates.
[0004]
Therefore, if the sensitivity is increased by long exposure, white flaws become conspicuous and the image quality deteriorates.
[0005]
[Problems to be solved by the invention]
As described above, in the conventional solid-state imaging device, there is a problem that when the charge accumulation time becomes longer due to long exposure, white scratches become conspicuous and image quality deteriorates.
[0006]
Therefore, in view of the above problems, the present invention discriminates a white scratch signal from the video signal output from the image sensor, suppresses the white scratch signal level, and improves the image quality. The object is to provide a suppression device.
[0007]
[Means for Solving the Problems]
A white scratch signal level suppressing device for a solid-state imaging device according to the invention of claim 1 is provided.
The video signal output from the image sensor is a protruding signal having a higher level than the preceding and following signal levels, and the width of the protruding portion of the signal corresponding to a predetermined number of pixels (suppressing horizontal direction) A level suppression circuit that determines that the signal is a white scratch signal and suppresses the signal level of the protruding portion to the front and rear signal levels,
And a control circuit for controlling the width corresponding to the number of pixels to be suppressed by the level suppression circuit in accordance with an accumulation time of long exposure of the image sensor.
[0008]
A white scratch signal level suppressing device for a solid-state imaging device according to a second aspect of the present invention comprises:
Regarding the video signal output from the image sensor, the difference between the current video signal and the video signal of one frame or one field before is taken, and whether or not the video signal is a white scratch signal is determined based on the difference value. A discriminating circuit for
The video signal determined to be a white defect signal by the determination circuit is a protruding signal having a higher level than the preceding and following signal levels, and the signal of the protruding portion is a predetermined value set in advance. When the signal is equal to or less than the width of the number of pixels (the number of pixels in the horizontal direction to be suppressed), the level suppressing circuit determines that the signal is a white defect signal and suppresses the signal level of the protruding portion to the previous and next signal levels. Are provided.
[0009]
A white scratch signal level suppressing device for a solid-state imaging device according to a third aspect of the present invention comprises:
A discriminating circuit for discriminating whether or not the video signal is a white defect signal based on a difference value between the current video signal and the video signal of one frame or one field before the video signal output from the image sensor; ,
The video signal determined to be a white defect signal by the determination circuit is a protruding signal having a higher level than the previous and subsequent signal levels, and a predetermined pixel in which the signal of the protruding portion is set A level suppression circuit that determines that the signal is a white defect signal when the signal is less than a few minutes (the number of pixels in the horizontal direction to be suppressed), and suppresses the signal level of the protruding portion to the previous and next signal levels; ,
And a control circuit for controlling the width corresponding to the number of pixels to be suppressed by the level suppression circuit in accordance with an accumulation time of long exposure of the image sensor.
[0010]
According to a fourth aspect of the present invention, in the white scratch signal level suppressing device for the solid-state imaging device according to the first or third aspect,
The control circuit increases the width corresponding to the number of pixels to be suppressed by the level suppression circuit as the accumulation time of the image sensor increases.
[0011]
In the invention of claim 4, when the accumulation time is long, the signal level of white scratches is increased, and at the same time, the pixel level around the scratch for one pixel is also increased. The width is increased, and if the accumulation time is short, the width is shortened.
[0012]
The invention according to claim 5 is the white scratch signal level suppressing device for the solid-state imaging device according to claim 2 or 3,
The discriminating circuit discriminates as a white flaw if the difference value between the current video signal and the video signal of one frame or one field before is smaller than the set reference value, and discriminates that it is not a white flaw if larger than the reference value. It is characterized by doing.
[0013]
In the first, third, and fourth aspects of the invention, the level suppression circuit suppresses the signal level of the protruding portion, and the accumulation time is set to a width corresponding to a predetermined number of pixels (the number of pixels in the horizontal direction to be suppressed). Control according to the length. That is, when the accumulation time is long, the width corresponding to the number of pixels whose level is suppressed is increased, and when the accumulation time is short, the width corresponding to the number of pixels whose level is suppressed is decreased so as to suppress the optimum white scratch signal level.
[0014]
According to the second and third aspects of the present invention, it is determined whether or not there is a white flaw according to the size of the difference value between the current video signal and the video signal one frame before or one field before. In this case, the level suppression circuit suppresses the white signal level.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a white scratch signal level suppressing device for a solid-state imaging device according to an embodiment of the present invention.
[0016]
In FIG. 1, a picked-up video signal is converted into an electric signal by an image pickup device 1 and input to an AGC circuit 3 through a sample and hold circuit (hereinafter referred to as S / H circuit) 2. In the S / H circuit 2, a signal portion is extracted by sampling and holding a clamp pulse from an electrical signal for each pixel generated by photoelectric conversion in the image sensor 1. The extracted signal component is amplified by the AGC circuit 3 with a predetermined gain, converted to a digital signal by the A / D converter 4, and subjected to signal processing such as gamma and detail processing by the signal processing circuit 5. Is output as
[0017]
The video signal output from the signal processing circuit 5 is converted into an analog video signal by the D / A converter 7 through the level suppression circuit 6 in the level suppression circuit block 14, NTSC encoded by the encoder 8, and various kinds of synchronization signals and the like. Are added and output.
[0018]
The level suppression circuit block 14 is a block that detects and suppresses white scratch signals, and includes a level suppression circuit 6, a frame memory 9 as a delay means, a subtractor 10, a discrimination circuit 11, and a control circuit 12. Yes.
[0019]
The level suppression circuit block 14 is supplied with the luminance signal of the video signal output from the signal processing circuit 5 as an input. The input luminance signal is input to the level suppression circuit 6 and the frame memory 9 and is also input to the subtracter 10. The output of the frame memory 9 is a video signal delayed by one frame period and becomes a subtracted input of the subtracter 10. The subtraction output of the subtracter 10 is input to the discrimination circuit 11.
[0020]
In the level suppression circuit 6, a signal corresponding to a protruding portion whose level is higher than the levels of the preceding and following signals and a width corresponding to the number of pixels set to be controllable by the control circuit 12 (suppression) If the signal is less than or equal to the number of pixels in the horizontal direction), it is determined in units of pixels that the signal is a white defect, and the signal level of the protruding portion is suppressed to the previous and next signal levels, thereby causing a white defect. The signal level is suppressed. Thus, the level suppression circuit 6 suppresses the signal level of white flaws according to the control signal input from the control circuit 12. However, in the level suppression circuit 6 described above, the level suppression is controlled by a change in level between adjacent pixels, and thus a change in the video level may be mistaken as a white defect.
[0021]
Therefore, in the present embodiment, a frame memory 9, a subtracter 10, and a discrimination circuit 11 are further provided, and the discrimination circuit 11 determines the magnitude of the difference value between the current video signal and the video signal one frame before. By comparing with the value and using the comparison result, the probability that white scratches can be confirmed is increased (no misidentification). Then, only when the comparison result (discrimination signal) output from the discrimination circuit 11 is not a change in the video level but is considered to be a white defect signal, the level suppression circuit 6 has a higher level compared to the previous and subsequent signal levels. The signal level of the portion that has been adjusted can be suppressed to the previous and next signal levels.
[0022]
The discrimination circuit 11 outputs a discrimination signal according to the subtraction result of the subtracter 10 as to whether or not the signal is a white scratch signal. Since a white scratch signal is always generated at the same pixel and the level is constant, a difference value (subtraction value of the subtractor 10) between the current video signal and the video signal delayed by one frame by the frame memory 9 is set. If the value is smaller than the reference value, it is determined that there is a white defect, and if the value is greater than the reference value, it is determined that there is no white defect. If the difference value is larger than the reference value, it is assumed that the amount of video change between the previous video signal and the current video signal is not white scratches. On the other hand, if the difference value is smaller than the reference value, it is assumed that the previous video signal and the current video signal are at substantially the same level, resulting in white scratches. The signal level can be configured not to be suppressed by the level suppression circuit 6 for the pixel signal determined to be not white flaws by the determination circuit 11.
[0023]
The control circuit 12 levels the white defect signal over the number of pixels in the level suppression circuit 6 according to the length of the pulse signal indicating the charge accumulation time (that is, exposure time) of the image sensor 1 input to the terminal 13. A control signal indicating whether to suppress is output. Control is performed to increase the width of the number of pixels to be suppressed by the level suppression circuit 6 (the number of pixels in the horizontal direction to be suppressed) as the charge accumulation time increases. This is because as the charge accumulation time of the image sensor 1 becomes longer, the signal level of white scratches increases, and the scratch for one pixel also increases the level of surrounding pixels. Therefore, the control circuit 12 increases the width for the number of pixels set by the level suppression circuit 6 if the accumulation time is long, and shortens the width for the number of pixels set by the level suppression circuit 6 if the accumulation time is short. Control.
[0024]
FIG. 2 is a block diagram showing a configuration example of the level suppression circuit 6, and FIGS. 3 and 4 show timing charts of the operation of FIG.
[0025]
2, the level suppression circuit 6 includes a video signal (pixel signal) input terminal 61, a minimum value selection circuit 62, a delay circuit 63, a minimum value selection circuit 64, a maximum value selection circuit 66, and a switch 67. A control signal input terminal 68 from the control circuit 12, a determination signal input terminal 69 from the determination circuit 11, and an output terminal 70.
[0026]
A video signal (pixel signal) is input from the signal processing circuit 5 to the input terminal 61 and supplied to one input terminal of the minimum value selection circuit 62 and the delay circuit 63. The delay circuit 63 is a circuit for giving a time width corresponding to a predetermined number of pixels (the number of pixels in the horizontal direction to be suppressed), for example, one pixel, to the input video signal. The delay time width (the number of delay pixels) ) Can be changed by a control signal from the input terminal 68. The minimum value selection circuit 62 is a circuit that selectively outputs the smaller one of the two input signals, and outputs a signal of that level when the two input signals are at the same level. The delay output from the delay circuit 63 is supplied to the other input terminal of the minimum value selection circuit 62 and to one input terminal of the minimum value selection circuit 64 and the delay circuit 65. The delay circuit 65 has a delay time similar to that of the delay circuit 63, and the delay output is supplied to the other input terminal of the minimum value selection circuit 64. Similarly to the minimum value selection circuit 62, the minimum value selection circuit 64 selectively outputs the smaller one of the two input signals, and outputs a signal of that level when the two input signals are at the same level. It is a circuit to do. The selection output of the minimum value selection circuit 62 and the selection output of the minimum value selection circuit 64 are supplied to two input terminals of the maximum value selection circuit 66. The maximum value selection circuit 66 is a circuit that selectively outputs the larger one of the two input signals, and outputs a signal of that level when the two input signals are at the same level. The selection output of the maximum value selection circuit 66 is supplied to one input terminal P of the switch 67, and the delay output from the delay circuit 63 is supplied to the other input terminal Q of the switch 67. The switch 67 selects the input terminal P, that is, the output of the maximum value selection circuit 66 if it is a white defect determination signal based on the determination signal from the input terminal 69 (that is, whether the signal determined by the determination circuit 11 is white defect). If the signal is determined not to be white, the input terminal Q, that is, the output of the delay circuit 63 is selected and output from the output terminal 70.
[0027]
Next, the operation of FIG. 2 will be described. Here, it is assumed that the delay time width of the delay circuits 63 and 65 is set to one pixel by the control circuit 12.
[0028]
FIG. 3 is a timing chart when the width of the input video signal from the input terminal 61 is one pixel (that is, when the width of the protruding signal having a high level compared to the preceding and following signal levels is one pixel). When the width of the input video signal is one pixel as shown in FIG. 3 (a), the delay circuits 63 and 65 respectively delay the input video signal by one pixel and become as shown in FIGS. 3 (b) and 3 (c). In the minimum value selection circuit 62, the smaller one of the signals (a) and (b) is selected to obtain the output of FIG. 3 (d). Further, in the minimum value selection circuit 64, the smaller one of the signals (b) and (c) is selected to obtain the output of FIG. 3 (e). In the maximum value selection circuit 66, the larger one of the signals (d) and (e) is selected, and the output shown in FIG. 3 (f) is obtained. Therefore, when the delay time of the delay circuits 63 and 65 is set to 1 pixel and the width of the input video signal is 1 pixel (that is, when it is equal to or smaller than the set value), the signal of 1 pixel is white scratched. Therefore, the protruding signal level for one pixel can be suppressed to the previous and next signal levels and supplied to the input terminal P of the switch 67.
[0029]
FIG. 4 is a timing chart when the width of the input video signal from the input terminal 61 is 2 pixels. When the width of the input video signal is 2 pixels as shown in FIG. 4 (a), the delay circuits 63 and 65 respectively delay the input video signal by 1 pixel and become as shown in FIGS. 4 (b) and 4 (c). In the minimum value selection circuit 62, the smaller one of the signals (a) and (b) is selected to obtain the output of FIG. 4 (d). Further, in the minimum value selection circuit 64, the smaller one of the signals (b) and (c) is selected to obtain the output of FIG. 4 (e). In the maximum value selection circuit 66, the larger one of the signals (d) and (e) is selected to obtain the output of FIG. 4 (f) (this is the same signal as in FIG. 4 (b)). Therefore, when the delay time of the delay circuits 63 and 65 is set to 1 pixel and the width of the input video signal is 2 pixels (that is, exceeds the set value), the signal of these 2 pixels is white scratch. It can be determined that there is no change (that is, a video change), and can be supplied to the input terminal P of the switch 67 without suppressing the protruding signal level for two pixels.
[0030]
As described above with reference to FIGS. 3 and 4, the circuit portion 6A indicated by the broken line frame in FIG. 2 performs white defect determination based on the width of a predetermined number of pixels. The level can be suppressed to the front and rear signal levels and supplied to the input terminal P of the switch 67.
[0031]
In the switch 67, in addition to the white scratch detection and suppression by the circuit portion 6A shown by the broken line frame in FIG. 2, the determination circuit as described above (the difference between the current video signal and the video signal of one frame or one field before is calculated). Therefore, the input terminal P is selected only when the discrimination result of the video signal 11 is determined to be white flaw based on the difference value. An output (f) in which white flaws are suppressed is output from the value selection circuit 66 to the D / A converter 7 from the output terminal 70. If the discrimination result of the discrimination circuit 11 is not white scratch, the input terminal Q is selected. At this time, the output (b) from the delay circuit 63 which is not suppressed from white scratch is output from the output terminal 70 to D / A conversion. Is output to the device 7. The switch 67 can increase the certainty of white flaw discrimination and suppression.
[0032]
FIG. 5 schematically shows the level suppressing operation of the circuit portion 6A in the broken line frame in FIG. FIG. 5A shows a state in which the protruding signal portion as an output is removed when the protruding signal having a high level in the input video signal is equal to or smaller than the width of the number of pixels set by the control circuit 12. . FIG. 5B shows a state in which the protruding signal portion is output as it is without being removed when the protruding signal having a high level in the input video signal is larger than the width of the number of pixels set by the control circuit 12. Is shown.
[0033]
FIGS. 6A and 6B show examples of control characteristics of the control circuit 12 and show two examples of changes in the width corresponding to the number of pixels set in accordance with the input storage time value. FIG. 6A shows a control characteristic in which the width of the number of pixels to suppress the level increases linearly as the charge accumulation time (exposure time) increases, and FIG. 6B shows the charge accumulation time (exposure time). ) Shows a control characteristic in which the width of the number of pixels for which the level is suppressed increases stepwise.
[0034]
In the above embodiment, the circuit for determining the white scratch signal level using the frame correlation has been described. However, by using a field memory instead of the frame memory 9, the white correlation can be obtained using the field correlation. A circuit for determining the signal level of the scratch may be configured.
[0035]
In the embodiment of FIG. 1, the case where a circuit for discriminating the signal level of white scratches using frame correlation has been described (that is, one frame is delayed as a delay means in the level suppression circuit block 14). However, when the solid-state imaging device is used in a high sensitivity mode, which will be described later, a field memory for delaying one field instead of the frame memory may be used as the delay means. good.
[0036]
Thus, in the high sensitivity mode of the solid-state imaging device, a circuit using field correlation can be used as the level suppression circuit block 14. The normal sensitivity mode and the high sensitivity mode will be described below.
[0037]
That is, in the white scratch signal level suppressing device in the solid-state imaging device, the white scratch component is suppressed from the video signal obtained based on the charge accumulated in the photoelectric conversion unit of the image sensor for each field period (normal sensitivity mode). The video signal has a correlation between the frames (this is because the odd field and the even field constituting one frame are interlaced, so the correlation is small and the correlation between the frames is relatively large. By utilizing the difference between the currently input video signal and the video signal delayed by one frame, a change component between frames is extracted and supplied to the discrimination circuit 11.
[0038]
Further, in the white scratch signal level suppressing device in the solid-state imaging device, a field having no exposure charge based on the charge accumulated and exposed every n times (n is a natural number) of one frame period in the photoelectric conversion unit of the image sensor. When the white flaw component is suppressed from the video signal obtained by interpolation (in high sensitivity mode), the odd number field or even field is always fixed, so the video signal is correlated between the fields. The difference between the currently input video signal and the video signal delayed by one field is extracted by using this, and the change component between frames is extracted and supplied to the discrimination circuit 11 to suppress white scratches. Can be achieved. In the high sensitivity mode, it is possible to extract a white defect component by taking the difference between the current video signal and the video signal delayed by one frame. That is, if a frame memory is used as the delay means, it can be applied to both the normal sensitivity mode and the high sensitivity mode.
[0039]
In general, a solid-state imaging device such as a video camera uses a CCD (Charge Coupled Device) as a solid-state imaging device. The normal sensitivity mode and the high sensitivity mode will be described with reference to FIGS.
[0040]
FIG. 7 is a diagram showing an example of the configuration of a CCD.
The CCD shown in FIG. 7 receives a light from a subject and converts it into an electrical signal, and a vertical transfer in which signal charges accumulated in the photoelectric conversion unit 21 are transferred in synchronization with a field shift pulse (FS). The transfer unit 22, the horizontal transfer unit 23 that transfers the signal charges for one screen transferred to the vertical transfer unit 22 for each line, and the output unit that outputs the horizontally transferred signal charges from the terminal 25 for each pixel. 24.
[0041]
FIG. 8 shows a timing chart of CCD output and video output in the normal sensitivity mode of the video camera. The exposure time of the CCD video camera in the normal sensitivity mode is 1 field (1/60 s).
[0042]
8A shows an exposure time (one field), FIG. 8B shows a field shift pulse (FS) for reading signal charges from the photoelectric conversion unit 21 to the vertical transfer unit 22, and FIG. 8C shows a CCD output signal. FIG. 8D shows video output signals.
[0043]
As shown in FIG. 8B, a field shift pulse is output to the CCD for each field. As a result, the charges accumulated in the photoelectric conversion unit 21 for one field period (that is, the charges accumulated in the periods A, B, C, D... Shown in FIG. 8A) are respectively shown in FIG. As shown in FIG. 8 (d), it is output as a CCD output signal delayed by one field period, and further converted into a video signal by a signal processing means (signal processing circuit 5, encoder 8, etc.).
[0044]
On the other hand, in a CCD video camera (or frame dropping long exposure video camera) in the high sensitivity mode, the exposure time is increased from the normal one field to 2, 4, 6,... Field by thinning out the field shift pulse. High sensitivity is realized by this. The reason for changing the exposure time every two fields is to prevent jitter in the video output by fixing the odd field / even field (ODD / EVEN) of the signal charge to be read out to any one.
[0045]
Next, the high sensitivity mode operation by long exposure will be described with reference to FIG.
FIG. 9 shows a timing chart of CCD output and video output in the high sensitivity mode of the video camera.
[0046]
9A is an exposure time (2 fields), FIG. 9B is a field pulse for reading signal charges from the photoelectric conversion unit 21 to the vertical transfer unit 22, FIG. 9C is a CCD output signal, and FIG. ) Indicate video output signals.
[0047]
As shown in FIG. 9B, an example is shown in which the field shift pulse is output every two fields without being output every field. The CCD output signal is output every two fields as shown in FIG. 9 (c). In this CCD output signal, since the charge accumulated during the two-field period 33 is output during the one-field period 31, a signal exposed for a long time is obtained.
[0048]
However, since there is no exposure signal output in the field period 32 following the field period 31, it is necessary to interpolate the field period 32 with the exposure signal of the field period 31 using the memory of the signal processing circuit 5 at the subsequent stage. In this way, the photoelectric conversion unit 21 performs long-time exposure, and a high-sensitivity video output signal shown in FIG. 9D is obtained. The memory interpolation is performed using a known method. For example, the signal immediately before the exposure signal output disappears is used as it is, or the signal before and after the exposure signal output disappears is obtained by interpolation (using an average value before and after, etc.).
[0049]
Automatic control of the exposure time according to the brightness of the video output as shown in FIGS. 8 and 9 is called automatic sensitivity switching. In the automatic sensitivity switching, for example, the level of the integrated value or peak value of the luminance signal is compared with two threshold values of light / dark, and when it is determined to be dark, the exposure time is set to 2 fields (1/30 s), 4 fields. ,..., And if it is judged bright, the exposure time is decreased by two fields or only one field. That is, when the image is dark, a field shift pulse with a period expanded by 2 field periods, 4 field periods,..., And when the image is bright, a field shift pulse with a period shortened by 2 field periods or a field shift pulse with 1 field period. This is realized by supplying to the CCD.
[0050]
FIG. 10 is a block diagram of a white scratch signal level suppressing device for a solid-state imaging device having an automatic sensitivity switching function according to another embodiment of the present invention.
[0051]
10 differs from FIG. 1 in that an exposure time control circuit 15 and a CCD drive circuit 16 are provided to enable automatic sensitivity switching, while an exposure time control signal S4 corresponding to the accumulation time is supplied to a terminal 13. In other words, it is possible to automatically set the set number of pixels for discriminating white flaws according to the brightness of the light from the subject. The brightness signal from the signal processing circuit 5 is guided to the exposure time control circuit 15 and the level of the integrated value or peak value of the brightness signal is compared with two threshold values of light / dark, and an exposure time control signal indicating the comparison result. S4 is generated and supplied to the CCD driving circuit 16. The CCD drive circuit 16 generates a CCD drive pulse S5 including a field shift pulse (FS) to drive the image pickup device 1. The FS pulse period in the CCD drive pulse S5, that is, the FS pulse decimation amount. Is controlled by the exposure time control signal S4. That is, when the exposure time control circuit 15 determines that the image is bright (in the normal sensitivity mode), the FS cycle is set to one field, for example, and the charge accumulation time of the photoelectric conversion unit of the image sensor 1 is set to be short and controlled simultaneously. When the number of pixels set in the circuit 12 is also set small and it is determined that the image is dark (in the high sensitivity mode), the cycle of FS is set to 2 fields, for example, and the charge accumulation time of the photoelectric conversion unit of the image sensor 1 is set long. At the same time, the number of set pixels of the control circuit 12 is set large. The exposure time (FS pulse cycle) is set by the exposure time control circuit 15 when the video is dark as described above, with the field shift pulse having a period expanded as 2 field periods, 4 field periods,. Can be performed by supplying a field-shift pulse having a period shortened by two field periods or a field shift pulse to the image sensor (CCD). Further, the sensitivity may be switched by making it possible to switch between two threshold values of light / dark. Further, when the exposure time control signal S4 from the exposure time control circuit 15 indicates that the image is dark, the frame memory 9 can be switched to the field memory.
[0052]
In accordance with the difference between the current video signal by the discrimination circuit 11 described above and the video signal delayed by one frame or one field and the length of the charge accumulation time of the image sensor 1 by the control circuit 12, the level suppression circuit 6 is controlled. By controlling it, it becomes possible to perform the optimum white flaw suppression.
[0053]
In the above embodiment, the case where the level suppression circuit is controlled according to the difference value between the current video signal from the image sensor and the video signal delayed by one frame or one field and the charge accumulation time of the image sensor has been described. However, in the present invention, the control is not limited to the case where the control is performed according to both the difference between the current video signal and the video signal delayed by one frame or one field and the charge accumulation time of the imaging device, but any one of these is controlled. You may do it. For example, the level of the white flaw signal may be suppressed by making the width corresponding to the number of pixels suppressed by the level suppression circuit constant without performing control based on the accumulation time.
[0054]
In the above embodiment, the white flaw signal level suppressing device of the solid-state imaging device of the present invention is not limited to a video camera, but a white flaw signal level suppressing device in video equipment such as a VTR and a TV receiver. It is possible to apply to.
[0055]
Furthermore, the solid-state imaging device according to the present invention can be used not only for video cameras but also for imaging devices for various purposes such as medical imaging devices.
[0056]
【The invention's effect】
As described above, according to the present invention, it is possible to determine a white defect signal from the video signal output from the image sensor, suppress the signal level of the white defect, and improve the image quality. Also, white flaw suppression control is performed according to the difference value between the current video signal and the video signal delayed by one frame or field, or the charge accumulation time of the image sensor, and the pixel of the pixel determined to be a white flaw signal is controlled. By suppressing the level of the signal to the level before and after that, the level of the white scratch signal can be suppressed. Furthermore, since the white scratch signal level is suppressed in real time in units of pixels, it can be applied to many scratches and newly generated scratches.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a white scratch signal level suppressing device of a solid-state imaging device according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration example of a level suppression circuit.
FIG. 3 is a timing chart of the operation of FIG.
4 is a timing chart of the operation of FIG.
5 is a diagram schematically showing a level suppressing operation of a circuit portion 6A in a broken line frame in FIG. 2;
FIG. 6 is a characteristic diagram illustrating an example of control characteristics of the control circuit 12;
FIG. 7 is a diagram illustrating an example of a configuration of a CCD.
FIG. 8 is a timing chart showing the timing of CCD output and video output in the normal sensitivity mode of the video camera.
FIG. 9 is a timing chart showing the timing of CCD output and video output in the high sensitivity mode of the video camera.
FIG. 10 is a block diagram showing a white scratch signal level suppressing device of a solid-state imaging device according to another embodiment of the present invention.
[Explanation of symbols]
1 ... Image sensor
6 ... Level suppression circuit
9: Frame memory (delay means)
10 ... Subtractor
11: Discrimination circuit
12 ... Control circuit
13 ... Accumulation time setting terminal
14 ... Level suppression circuit block

Claims (5)

The video signal output from the image sensor is a protruding signal having a higher level than the preceding and following signal levels, and the width of the protruding portion of the signal corresponding to a predetermined number of pixels (suppressing horizontal direction) A level suppression circuit that determines that the signal is a white scratch signal and suppresses the signal level of the protruding portion to the front and rear signal levels,
And a control circuit that controls a width corresponding to the number of pixels to be suppressed by the level suppression circuit in accordance with an accumulation time of long exposure of the image sensor. apparatus. Regarding the video signal output from the image sensor, the difference between the current video signal and the video signal of one frame or one field before is taken, and whether or not the video signal is a white scratch signal is determined based on the difference value. A discriminating circuit for
The video signal determined to be a white defect signal by the determination circuit is a protruding signal having a higher level than the preceding and following signal levels, and the signal of the protruding portion is a predetermined value set in advance. When the signal is equal to or less than the width of the number of pixels (the number of pixels in the horizontal direction to be suppressed), the level suppressing circuit determines that the signal is a white defect signal and suppresses the signal level of the protruding portion to the previous and next signal levels. A white flaw signal level suppressing device for a solid-state imaging device. A discriminating circuit for discriminating whether or not the video signal is a white defect signal based on a difference value between the current video signal and the video signal of one frame or one field before the video signal output from the image sensor; ,
The video signal determined to be a white defect signal by the determination circuit is a protruding signal having a higher level than the previous and subsequent signal levels, and a predetermined pixel in which the signal of the protruding portion is set A level suppression circuit that determines that the signal is a white defect signal when the signal is less than a few minutes (the number of pixels in the horizontal direction to be suppressed), and suppresses the signal level of the protruding portion to the previous and next signal levels; ,
And a control circuit that controls a width corresponding to the number of pixels to be suppressed by the level suppression circuit in accordance with an accumulation time of long exposure of the image sensor. apparatus. 4. The white of the solid-state imaging device according to claim 1, wherein the control circuit increases a width corresponding to the number of pixels to be suppressed by the level suppression circuit as an accumulation time of the imaging element becomes longer. Scratch signal level suppression device. The discriminating circuit discriminates as a white flaw if the difference value between the current video signal and the video signal of one frame or one field before is smaller than the set reference value, and discriminates that it is not a white flaw if larger than the reference value. The white flaw signal level suppressing device for a solid-state imaging device according to claim 2 or 3, wherein

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