JP2000215219A - Circuit correction device - Google Patents

Abstract

(57) Abstract: A transition delay time violation is corrected in a layout design of a semiconductor integrated circuit device. SOLUTION: A repeater cell insertion determining means 10 is provided for a violating node 121 specified by a violating point specifying means 101.
In step 2, it is determined whether or not to insert a repeater cell. The virtual wiring means 103 performs virtual wiring of a net related to the node into which the repeater is to be inserted, the segment determining means determines the place where the repeater is to be inserted, and the grouping means 105
To optimize the number of repeater cells. The netlist creating means 106 creates a netlist into which the repeater has been inserted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a layout design of a semiconductor integrated circuit device, and more particularly to a circuit correction device associated with a transition delay time violation.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, it is necessary to make a signal transition delay time smaller than a guaranteed reference value for quality assurance.

After the layout design, the transition delay time is checked, and if there is a violation portion larger than the guaranteed reference value, the circuit needs to be modified.

In the standard cell design, as a correction method at this time, there is a method of (1) increasing the cell size to increase the driving capability and reduce the transition delay time.

However, even when the transition delay time is short at the output terminal of the cell, the waveform is rounded depending on the resistance and capacitance of the wiring, so that the transition delay time at the input terminal of the subsequent cell becomes large and it is illegal. There is.

In such a case, (2) the repeater cell can be inserted to improve the transition delay time.

In the waveform rounding correction system disclosed in Japanese Patent Application Laid-Open No. 9-212536, an element for correction is determined from the resistance value and the capacitance value of the wiring, and the circuit is corrected.

[0008]

When one repeater cell is inserted into an input terminal of one cell with respect to a wiring having a large fan-out, an excessive number of repeater cells are inserted and compared with the circuit before the correction, and the correction is performed. Since the cell area of the post-circuit is greatly increased, the amount of change in cell arrangement and wiring in layout correction is increased.

In order to reduce the number of inserted repeater cells, it is necessary to drive input terminals of a plurality of cells with one repeater cell. For example, when grouping is performed in consideration of only the cell arrangement, the actual wiring and the wiring estimated from the arrangement are different, so the wiring path is controlled by inserting the repeater cells, and the wiring shape is greatly different in the layout correction. There is. In addition, when determining the insertion position of the repeater cell in consideration of not only the cell layout but also the wiring shape, wiring shape data is required, and thus there is a problem that the amount of data to be handled becomes enormous.

An object of the present invention is to provide a circuit correction apparatus which aims to eliminate transition delay time violations by inserting repeater cells while suppressing a change in wiring due to rewiring at the time of layout design change with a data amount smaller than wiring shape data. It is.

[0011]

In order to achieve the above object, a circuit repair apparatus according to the present invention includes: means for specifying a transition delay time violation portion from a wiring parasitic capacitance and a resistance extraction result of layout data; Means for attempting to change the driving capability in response to the violation and determining whether or not to insert a repeater cell; and means for performing virtual wiring based on wiring branch information for a net determined to insert a repeater cell by the determination means. Means for determining a position where a repeater cell is inserted on the virtual wiring, means for deleting unnecessary repeater cells to reduce the number of the repeater cells, and reflection of the repeater cell inserted on the virtual wiring as a circuit correction Means for creating a netlist.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention.

This circuit correction device includes a violation point specifying means 101 for specifying a transition delay time violation node 121 from a wiring parasitic capacitance and resistance extraction result 111 of layout data, and a repeater violation correction method for the transition delay time violation node 121. A repeater cell insertion target node 1 based on a netlist 112 and wiring branch position information 113 for determining whether or not to insert a cell.
A virtual wiring means 103 for virtually wiring a net connected to the node 22 and a segment for inserting a repeater cell for correcting a violation of the repeater cell insertion target node 122 in the virtual wiring 123 are determined. Segment determining means 104 for creating the wiring 124;
Grouping means 105 for grouping repeater cells in the same segment from the virtual wire 124 with the repeater cell inserted therein to create a virtual interconnect 125 processed with repeater cells, and a net for creating a corrected netlist 114 from the virtual interconnect 125 processed with repeater cells. And a list creation means 106.

Next, the processing flow will be described.

The violating point specifying means 101 calculates a delay from the wiring parasitic capacitance and the resistance extraction result 111 and specifies a transition delay time violation node 121 having a transition delay time larger than a preset reference transition delay time.

The process of the repeater cell insertion determining means 102 will be described with reference to FIG. Node 202 is a transition delay time violation node, cell 212 has node 202,
The cell 211 is a cell that drives the cell 212,
One.

The repeater cell insertion judging means 102 extracts the cell 211 driving the violating node 202 from the netlist 112, changes the cell 211 to a cell 221 having a large driving ability based on the cell library 115, performs delay calculation,
If there is no violation of the transition delay time at the node 202, the process is terminated. If there is a violation, the node 202 is set as the repeater cell insertion target node 122.

Here, the drive capability of the cell 211 is changed and the repeater insertion is determined. However, as another method, the difference between the transition delay time of the node 201 and the transition delay time of the node 202 is determined by a predetermined reference value. Is larger, there is a method of determining the node 202 as the repeater cell insertion target node 122.

The virtual wiring means 103 performs virtual wiring for the net connected to the repeater cell insertion target node 122 from the net list 112 and the wiring branch position information 113, and creates a virtual wiring 123.

Next, a virtual wiring method will be described with reference to FIG.

The circuit structure of the net connected to the repeater cell insertion target node 122 is extracted from the net list 112. The branch information of this net is extracted from the wiring branch position information. In the wiring branch position information, as shown in FIG. 5, the coordinates of the connection node between the net and the cell, the coordinates of the branch node of the net, and the connection relationship between the nodes are described.

Each node 301, 302, 303, 30
Based on the coordinates of 4, 305, and 306, the nodes having a connection relationship are wired in a Steiner tree.

The processing of the segment determining means 104 will be described with reference to FIG.

The wiring shown in FIG. 3 is a virtual wiring 123 created by the virtual wiring means 103. Nodes 301 and 30
Reference numerals 2, 303, 304, 305, and 306 denote wiring branch positions, and a node 303 is a repeater cell insertion target node.

The virtual wiring has segments 321, 322, 323, 324, and 325 divided by each node.

The intermediate position on the wiring between the node 303 to be inserted with the repeater cell and the node 301 of the cell 311 that drives the cell 312 having the node 303 is estimated as the repeater cell insertion position, and the segment 322 is inserted into the repeater cell. The segment is determined, and a repeater cell is inserted on the virtual wiring 123.

If the nodes 304 and 306 are repeater cell insertion nodes, the node 3
A repeater cell is inserted into a segment 323 including an intermediate position from 01.

The segment determining means 104 obtains the virtual wiring 124 into which the repeater cell has been inserted. Since each segment is divided at the branch position, it is always a fan-out 1 wiring.

For this reason, even if the virtual wiring is different from the actual wiring, the fan-out does not change due to the insertion of the repeater cell. Therefore, the cells can be inserted and arranged on the actual wiring without greatly changing the wiring shape. It is possible to

The grouping means 105 optimizes the number of the repeater cells in the virtual wiring 124 into which the repeater cell is inserted, and obtains the virtual wiring 125 after the repeater cell processing.

The processing of the grouping means 105 will be described with reference to FIG.

FIG. 4A shows the processing result of the segment determining means 104. Nodes 403, 404, and 406 are repeater cell insertion target nodes, and the repeater cells for each node are cells 431, 433, and 432, respectively.

The grouping means 105 combines repeater cells in the same segment into one. Cell 43
Since the cells 2 and 433 exist in the same segment 423, the cell 433 is deleted, and the virtual wiring shown in FIG. 4B is obtained.

By this processing, unnecessary repeater cells inserted redundantly are deleted, so that the number of repeater cells can be minimized.

The netlist creating means 106 creates a netlist 114 from the virtual wiring 125 subjected to the repeater cell processing as a result of the processing by the grouping means 105.

[0037]

As described above, according to the present invention, since the repeater cell is inserted in consideration of only the branch position of the wiring, the amount of data to be handled is small and the wiring path can be reduced with the minimum number of repeater cells. An advantageous effect is obtained that a netlist whose layout design can be changed without changing it can be created.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a circuit correction device.

FIG. 2 is a diagram illustrating an example of determination of repeater cell insertion;

FIG. 3 is a diagram showing an example of virtual wiring;

FIG. 4 is a diagram showing an example of a virtual wiring in which a repeater cell is inserted.

FIG. 5 is a diagram showing an example of wiring branch position information;

[Explanation of symbols]

 101 Violation point identification means 102 Repeater cell insertion determination means 103 Virtual wiring means 104 Segment determination means 105 Grouping means 106 Netlist creation means 111 Wiring parasitic capacitance, resistance extraction result 112 Netlist 113 Wiring branch position information 114 Modified netlist 115 cell Library 121 Transition delay time violation node 122 Repeater cell insertion target node 123 Virtual wiring 124 Repeater cell inserted virtual wiring 125 Repeater cell processed virtual wiring

Claims (3)

[Claims] 1. A device comprising: a transition delay time violation point specifying unit; a correction element insertion determining unit; a virtual wiring unit; a correction element insertion position determining unit; a correction element optimizing unit; and a result output unit. An apparatus for correcting a transition delay time violation of a circuit, wherein the transition delay time violation location specifying means specifies a violation location where a transition delay time of a signal is equal to or greater than a predetermined reference value, and The insertion determining means determines a circuit correction method for the violating portion, and the virtual wiring means determines a virtual wiring based on the wiring branch position information when the correcting element insertion determining means determines that the correcting element is to be inserted. The correction element insertion place determining means determines the insertion place of the correction element in the virtual wiring, and the correction element optimization means deletes the inserted correction element in the virtual wiring. A circuit correction device configured to output the circuit in which the correction element is inserted, wherein the result output unit outputs the circuit in which the correction element is inserted. 2. The method according to claim 1, wherein the repair element is inserted at a location between branches of the wiring, and when the repair element overlaps between branches of the wiring, reduction is performed by the repair element optimizing means. The circuit correction device according to claim 1, wherein: 3. The circuit repair apparatus according to claim 1, wherein said repair element is a repeater cell.