JP2000224131A - Transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmitter that converts the speed of rearranged time slot data into the speed of an output frame independently of the speed of an input frame. SOLUTION: Memories 11, 12 store data DT of a frame that is time division multiplexed. A level of a MENSEL signal is switched for each frame, and if the level of the signal is 'H', the memory 11 acts like a wire only memory and the memory 12 acts as a read only memory and a selector 13 gives a storage address SA to the memory 11, to which the input frame is received in a prescribed order to be rearranged into an output frame and data DT are written in the memory 11. A selector 14 gives a read address RA, whose number is sequentially increased to the memory 12, and a selector 15 gives read data to a speed conversion section 6. The speed conversion section 6 converts the speed of the input frame into the speed of an output frame. When the MENSEL signal is at 'L' level, the memory 11 acts as a read only memory and the memory 12 acts as a write only memory and they are subjected to reverse operation to the case when the MENSEL signal is at 'H' level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission apparatus for transmitting digital signals while multiplexing / demultiplexing them.
The present invention relates to a transmission apparatus having a function of rearranging time slots of a multiplexed digital signal flowing on a transmission path.

[0002]

2. Description of the Related Art In the process of transmitting a digital signal in the form of a frame or the like, a frame transmitted from a transmission path is distributed to a destination such as a subscriber terminal or transmitted by a plurality of subscriber terminals. In order to collectively transmit frames to a transmission line, digital signals are separated and time-division multiplexed. In order to realize such processing, a transmission device such as a multiplexing device rearranges time slots constituting a transmitted frame. The functional blocks in the transmission device that perform this sort are called TS
It is called an I (Time Slot Interchanger) section or the like. Such a TSI section is for realizing a so-called cross-connect function, and the procedure for rearranging such time slots is individually determined in advance by a frame format specific to each transmission interface.

FIG. 3 is a block diagram showing a conventional configuration of a TSI section provided in a transmission apparatus. The TSI section converts data of each time slot constituting a transmitted frame in accordance with a frame format. A method is employed in which the data is sequentially stored at the addresses of the memory, and then the data is sequentially read from the memory to rearrange the data. Therefore, the details of this method will be described below. In the figure, a memory 1 is a storage means for temporarily storing data of a time slot constituting a frame, as described above. As shown in the figure, the memory 1 is divided into two areas, area A and area B, which have the same logical capacity.

Each of these areas has a capacity to store one frame of data determined by a frame format. For convenience of explanation, here, the capacity of the memory 1 is 256 bytes (decimal number), and x “0” to x
Address “7F” (hereinafter “1” when “x” is added at the beginning)
Area A, x "80" to x
It is assumed that the address “FF” is area B. Further, in the figure, a data input terminal Din, an address input terminal ADR,
Although both the data output terminal Dout and the terminal W / R are described as if they were provided for each area, in practice, these terminals are the same as those of a commonly used memory element. Physically, only one system is provided for each.

[0005] Data DT input to a data input terminal Din of the memory 1 is data of a frame input from a transmission line. On the other hand, the storage address SA is an address signal designating the storage position of the data DT in the area A or the area B of the memory 1, and similarly, the read address RA is the data read position in the area A or the area B of the memory 1. Is an address signal for specifying As described above, since the capacity of each of the areas A and B is 128 bytes, the storage address SA and the read address RA are used.
Are 7-bit signals. In addition, MENSEL
The signal is triggered by a frame pulse (not shown in FIG. 3) output for each frame, and has an “H” (high) level.
This signal is a signal whose “L” (low) level is alternately switched, and is a signal for designating which of area A and area B is to be read or written.

The frame pulse is obtained by detecting a synchronization pattern included in the frame, and indicates the start of each frame, that is, the timing of the first time slot. Here, MENS
When the EL signal is at the “L” level, it is assumed that writing to area A and reading from area B are performed.
When the ENSEL signal is at the “H” level, on the contrary, reading from the area A and writing to the area B are performed. To this end, the inverter 2 supplies an inverted signal of the MENSEL signal supplied to the connection unit 3 to the connection unit 4 so that the write address and the read address indicate the area A, the area B, or the reverse.

[0007] The connection unit 3 has a storage address SA and a MENSE.
By concatenating the L signal with a bit value that is regarded as a binary value, the MENSEL signal is converted to a most significant bit
An 8-bit address signal is generated as t). Also,
The linking unit 4 has the same configuration as the linking unit 3, and connects the read address RA and a bit value obtained by regarding the MENSEL signal as a binary value, thereby forming an 8-bit address signal having the MENSEL signal as the MSB. Generate. In FIG. 3, M
SB is represented by [An + 1], and parts other than the MSB are represented by [An. . [A0]. Therefore, n = 6 in the case of FIG.

The W / R signal is used for writing / writing to the memory 1.
This is a signal for designating a read period, and is a signal synchronized with the data DT. As is clear from the timing chart of FIG. 4 described later, in the first half of each cycle, W / R
The signal is at “H” level, and during this period, the memory 1
Is the period for writing to On the other hand, in the latter half of each cycle, the W / R signal is at the “L” level, and this period is a period for reading from the memory 1. Note that the period during which the W / R signal is at the “H” level is longer than the period during which the signal is at the “L” level. This is because the speed conversion unit 6 converts the data DO read from the memory 1. This is because the latch timing is considered. Then, the selector 5 outputs the W / R input to the terminal S.
According to the signal, either the output of the connection unit 3 input to the terminal A or the output of the connection unit 4 input to the terminal B is selected, and the selected address signal is input to the memory 1 as an address MA to be input to the memory 1. Output from Y. That is, the selector 5 selects a write address input to the terminal A when the W / R signal is at “H” level, and a read address input to the terminal B when the W / R signal is at “L” level. Select the address.

On the other hand, the speed conversion section 6 outputs data obtained by performing speed conversion on the data DO output from the memory 1. In other words, the speed conversion unit 6 is a functional block for converting the multiplexed signal input to the TSI unit into a multiplexed signal having a different speed from the multiplexed signal. For example, 6.3 Mbit / s as shown in FIG. And data transmitted at a rate of 19.44 Mbit / s as shown in FIG. 6 (hereinafter, may be referred to as a "19 mega interface"). . Although the output destination of the speed conversion unit 6 is not shown, a subsequent functional block provided in the transmission device, such as a functional block for adding information indicating that an alarm has occurred to data in a frame, is provided. The output destination. The speed conversion unit 6 is realized by, for example, a dual port memory and its control circuit, and outputs the data DO output from the memory 1.
Are sequentially written from one port of the dual-port memory, and are sequentially read from the other port of the dual-port memory at a speed different from that at the time of writing according to the speed of the frame to be converted.

Next, the operation of the TSI unit shown in FIG. 3 will be described with reference to the timing chart of FIG. In FIG. 4, the same signals as those shown in FIG. 3 are given the same names. The frame pulse FP shown in the drawing is a frame pulse not shown in FIG. As shown in FIG. 4, a frame signal supplied from a transmission line is input to the data DT, and each frame signal has a plurality of time slots TS1, TS2,..., TS7,. TS95, T
S96... Note that these 96 time slots are for transmitting data, and
In addition to these, a control signal is also transmitted after the time slot TS96.

FIG. 5 and FIG. 6 show an example of a frame in which time slots are to be rearranged. In the following, a case where the time slots are rearranged from the frame in FIG. 5 to the frame in FIG. 6 will be described, but the reverse case is naturally possible. FIG. 5 shows a format of a main part of a frame before rearrangement, and illustrates a format of a frame having a speed of 6.3 Mbit / sec (frame period 125 μs, frame length 789 bits). . As shown, the time slots TS1 to TS98 and the field F are transmitted for each frame in this order.
Each time slot is composed of 8 bits, and the field F is composed of 5 bits. Of these, the time slot F is a bit string used for frame synchronization, alarm, and the like.
The time slot TS97 and the time slot TS98 are bit strings for notifying the status.

Here, the operation unit of the network is six lines ("CH1" to "CH6" in the figure), which are multiplexed as one handling group ("HG" in the figure). Further, four HGs constitute one unit to constitute the HW, and for example, HG1 to HG4 correspond to HW1 or HW5 shown in FIG. From the above,
As shown in the figure, first, HG1 to HG1 are set for CH1.
6 are transmitted as time slots TS1 to TS16, then, for CH2, data of HG1 to HG16 is transmitted as time slots TS17 to TS32, and similarly, data belonging to CH3 to CH6 is transmitted in time slots TS33 to TS96. Go on. The data B1 to B24 and HW1 to HW8 in the figure correspond to the reference numerals shown in FIG.

FIG. 6 shows the format of the main part of the rearranged frame.
A frame format of a mega interface (frame period 125 μs, frame length 2430 bits) is illustrated. In the figure, the OH part at the head of the frame is a fixed value of 8 bits used for the path pattern check. The data portion of 2048 bits following this is composed of eight fields HW1 to HW8 also shown in FIG. Each HW consists of 256 bits, and the leading part indicated by “* 0” is an empty byte.
The data B1 to B24 are the same as those shown in FIG. 5, and in the case of the illustrated HW2, HGn to HGn +
3 corresponds to HG5 to HG8 in FIG.

That is, the data B1 is the time slot TS
5, data B2 corresponds to time slot TS21, and so on.
This corresponds to S88. “* 1” to “* 7” following the data B1 to B24 are all empty bytes. After the data part, a 128-bit OH part and 2
An empty field of 46 bits follows. 5 and 6
, Time slots TS1 to TS96 in a frame input from the transmission path are
Data 1 to HW8 are rearranged in the order of data B1 to B24 and transmitted. That is, the time slots TS1,
These time slots are transmitted in the order of TS17, TS33, TS49,....

In FIG. 4, when a new frame is supplied to the TSI section at time t1, a frame pulse FP indicating the head of the frame is output, and at the same time, data of the head time slot TS1 is output. Become like Further, the MENSEL signal switches from “H” level to “L” level in synchronization with the falling of the frame pulse FP. Therefore, “0” is supplied to the connection unit 3 as the MSB of the address, and “1” is supplied to the connection unit 4 through the inverter 2 as the MSB of the address. At this time, since x "00" is supplied to the storage address SA, x "00" is output from the connection unit 3 as a write address. Here, since the W / R signal is at “H” level and instructs writing (“W” in the figure), the selector 5 selects the write address x “00” supplied to the terminal A. , This is the address M
A is the address input terminal ADR of the memory 1 from the terminal Y as A
Output to As described above, the data of the time slot TS1 is written to the address x “00” of the memory 1 (that is, the area A).

Next, at time t2, when the W / R signal switches to the "L" level to instruct reading ("R" in the figure), the selector 5 selects the terminal B side. At this time, since x “00” is given to the read address RA, the link unit 4 outputs x “8” as an address.
0 "is output, and this address value is supplied as an address MA to the address input terminal ADR of the memory 1. As a result, a time slot TS1 as data DO from the address x" 80 "(that is, area B) of the memory 1 is obtained. It is read out and output to the speed conversion unit 6. Then, from time t3 to time t20 thereafter, the time t1 to time
The operation follows the operation at time t2. That is,
At time t3, a value obtained by adding x “10” to the value of the storage address SA at time t1 is input, and the time slot TS2 is assigned to the address (area A) on the memory 1.
At time t4, a value obtained by adding x "01" to the value of the read address RA at time t2 is input, and the data of the time slot TS17 is read from the address x "81" of the memory 1.

Thereafter, similarly, when the storage address SA is x “1”
0, and the read address RA becomes x “0”.
1 ”. As a result, at times t5, t7,
At t9 and t11, x “20” and x “3” of the memory 1
Data of the time slots TS3 to TS6 are respectively written to addresses 0 ", x" 40 ", and x" 50 ", and at times t6, t8, t10, and t12, x" 81 "to x" of the memory 1 are written. The data of the time slots TS17, TS33, TS49, and TS65 are read from the address 84 ", respectively. At time t13, x" 01 "is input as the storage address SA and the memory 1 is read.
The data of the time slot TS7 is written to the above address. Further, at time t15 and time t17, x “4F” and x “5” are stored as storage addresses SA, respectively.
F "is input, and the data of the time slots TS95 and TS96 are written to these addresses on the memory 1. In addition, at times t16 and t18, x" 5E "and x" 5F "are read addresses RA respectively. The data of the time slots TS80 and TS96 are read and read.

Thereafter, at time t20, a frame pulse FP is generated again, and data D for the next frame is generated.
T is input, and at the same time, the MENSEL signal switches from “L” level to “H” level. As a result, the relationship between writing and reading for the areas A and B is switched. In this case, the storage address SA
And the change of the read address RA are the same as in the case of the time t1 to the time t19, but the MSB of the address supplied to the connection unit 3 and the connection unit 4 is opposite to that of the previous case. Therefore, at times t20, t22, t24, t26, and t28, x “80”, x “90”, x “A
0 ", x" B0 "and x" C0 "(area B), and at times t21, t23, t25 and t25.
At x27 and t29, x “00” to x “0” of the memory 1 are respectively stored.
Data is read from address 4 "(area A). In parallel with the above-described operation of reading data from area A or area B of memory 1, speed conversion processing is performed by speed conversion unit 6.

As described above, conventionally, the writing operation and the reading operation are alternately repeated with respect to one memory, and when writing to the area A, reading is performed from the area B subsequently, while When writing data to the area B, the data is subsequently read from the area A. In addition, when writing to area A and reading from area B are performed for a certain frame, writing to area B and reading from area A are performed in the next frame. At this time, since the time slot data on the area A has been rearranged by writing to the area A in the immediately preceding frame,
By sequentially reading data from the area A in the frame, the sorted time slot data is sequentially output to the speed conversion unit 6. This is area B
Is exactly the same. In this way, the data storage processing of the time slot in the current frame and the data reading processing of the time slot rearranged in the immediately preceding frame can be performed in parallel for each time slot using one memory.

[0020]

When the above method is used, the time required to read data of all the time slots in the frame from the memory 1 is determined by the data of all the time slots in the frame. This is the same as the time required to write to memory 1. For this reason, the following problems occur when the conventional method is used. That is, in the conventional method, the data read operation and the write operation for the memory 1 are integrated for each time slot, and the timing at which the data DO is read from the memory 1 depends on the data transfer speed of the multiplexed signal output from the TSI unit. It will be fixed regardless. In other words, the data DO is always output from the memory 1 to the speed converter 6 at a constant speed.

For this reason, if the read timing of the data DO output from the memory 1 is not changed, the speed converter 6 converts the read speed of the data DO into a speed corresponding to a faster multiplexed signal. Become. However, if the speed at which data is read from the dual-port memory constituting the speed conversion unit 6 is too high, the read operation will not be performed on the data DO for the dual-port memory.
May overwrite the write operation of the data. Conversely, despite the fact that data reading from the dual port memory has not been completed, the frame pulse F
It is also conceivable that P is generated and switching between the areas A and B in the memory 1 occurs. Then, while the speed conversion unit 6 is reading the data DO output from, for example, the area A of the memory 1, the writing operation to the area A of the memory 1 is started. As a result, a situation occurs in which the speed conversion unit 6 cannot take in all the data of the time slot stored in the memory 1.

As described above, it is difficult to share the same TSI section for various multiplexed signals having various speeds by using the method employed in the conventional TSI section. Therefore, in order to cope with such multiplexed signals having various speeds, it becomes necessary to provide a plurality of types of TSI units that can cope only with a certain range of frame speeds. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to convert the rearranged time slot data into the speed of the frame to be converted irrespective of the speed of the frame input to the TSI unit. It is another object of the present invention to provide a transmission apparatus having a TSI unit that can easily cope with various multiplexed signals having different speeds.

[0023]

In order to solve the above-mentioned problems, the invention according to claim 1 is obtained by rearranging the time slots of the input frame in an order determined from each format of the input frame and the output frame. In a transmission device that converts the speed of a generated frame into the speed of the output frame and transmits the time, the operation of storing the time slots of the input frame in the order, and sequentially storing the time slots of the stored input frame. The operation of reading and generating the generated frame is performed independently of each other, and the time slots are rearranged for each frame. According to the second aspect of the present invention, the speed of the generated frame obtained by rearranging the time slots of the input frame in the order determined from the formats of the input frame and the output frame is converted to the speed of the output frame and transmitted. In the transmission device, first and second storage means for storing a time slot of the input frame, and reading from the second storage means during writing to the first storage means, While writing to the second storage means, a write instruction and a read instruction to the first storage means and the second storage means are issued for each frame so as to read from the first storage means. And control means for controlling. According to a third aspect of the present invention, in the second aspect of the present invention, the control means controls the first storage means and the second storage means by using a frame pulse which becomes valid at the beginning of each frame as a trigger. It is characterized in that the relationship between writing and reading is switched.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a TSI unit provided in the transmission apparatus according to the present embodiment. The same components and signals as those shown in FIG. It is. In FIG. 1, memories 11 to 12 are storage units having the same configuration as each other. That is, each of these memories writes the data DT supplied to the data input terminal DATA to the address specified by the address input terminal ADR if the signal input to the terminal W / R is at the “H” level. On the other hand, the signal input to the terminal W / R is "L".
Level, each of these memories has an address input terminal A
The data of the time slot stored at the address supplied to DR is output from the output terminal Q to the terminals A and B of the selector 15.

Each of the selectors 13 to 15 is a 2-1 selector, and the configuration of these selectors is the same as the selector 5 shown in FIG. In addition, reference numerals 16 to 18 denote inverters. Then, the selector 13 sets the MEN
If the SEL signal is at "H" level, the storage address SA is set to the address MA1 and the address input terminal A of the memory 11 is set.
DR, and outputs the read address RA as the address MA1 when the MENSEL signal is at the “L” level.
Conversely, if the MENSEL signal is at "L" level, the selector 14 sets the storage address SA to the address MA.
2 is supplied to the address input terminal ADR of the memory 12, and if the MENSEL signal is at "H" level, the read address RA is output as the address MA2.

In the selector 15, the output of the inverter 18 is at "H" level (the MENSEL signal is at "L" level).
Then, the data DO1 output from the memory 11 is selected and output as the data DO to the speed conversion unit 6, while the output of the inverter 18 is at the "L" level (ME
If the NSEL signal is at "H" level, the data DO2 output from the memory 12 is output to the speed converter 6 as data DO. The inverter 17 controls terminals W / R of the memories 11 and 12 so that the memories 11 and 12 alternately perform a write operation and a read operation. Therefore, when the memory 11 performs the write operation, the memory 12 performs the read operation, and when the memory 11 performs the read operation, the memory 12 performs the write operation.

Next, the operation of the TSI unit having the above configuration will be described with reference to the timing chart of FIG. In FIG. 2, the same signals as those shown in FIG. 1 are given the same names. In FIG. 2, the memory 1
1, an address input terminal AD for each of the memories 12
The signals input to R, the data input terminal DATA, and the terminal W / R are shown. Further, the storage address S
A, the value of the read address SA is not particularly shown, but the address MA1 or the address MA2 corresponding to the portion indicated by "write mode" in the figure is the storage address SA.
In addition, the address MA2 or MA1 corresponding to the portion indicated by "read mode" in the figure is the read address RA.

First, when the frame pulse FP is generated at time t31, the MENSEL signal switches from the "L" level to the "H" level in accordance with the fall of the frame pulse FP. Thus, the selector 13 selects the storage address SA and outputs it as the address MA1. Further, since the output of the inverter 16 is at the "L" level, the selector 14 selects the read address RA and outputs this as the address MA2. In line with these, memory 11
The "H" level is applied to the W / R terminal of the memory 12, and the memory 11 enters the write mode, and the "L" level is applied to the W / R terminal of the memory 12, and the memory 12 enters the read mode. Further, since the output of the inverter 18 becomes "L" level, the selector 15 converts the data DO2 output from the memory 12 in the read mode to the data DO.
Will be output.

By a series of these operations, data DT
The data of the time slot TS1 given above is written to the address x “00” of the memory 11 specified by the address MA1 equivalent to the storage address SA. Further, the data of the time slot TS1 is read from the address x “00” of the memory 12 specified by the address MA2 equivalent to the read address RA as the data DO2, and is supplied as it is to the speed conversion unit 6 as the data DO. From time t32 to time t41, time t31 to time t41
It operates as in 32. That is, at time t3
At 2, the value obtained by adding x "10" to the value of the storage address SA at time t31 is input, and the data of the time slot TS2 is written to the address in the memory 11.

At the same time, a value obtained by adding x "01" to the value of the read address RA at time t31 is input, and the data of the time slot TS17 is read from the address x "01" of the memory 12, and this is read. Selector 15
Is output to the speed conversion unit 6 via. Thereafter, similarly, the address MA1 is incremented by x "10" and the address MA2 is incremented by x "01". as a result,
From time t33 to time t36, x “2” in the memory 11
Data of the time slots TS3 to TS6 are written to addresses 0 ", x" 30 ", x" 40 ", and x" 50 ", respectively, and at the same time, x" 02 "to x" 05 "of the memory 12. "Time slot TS3 from address
3, TS49, TS65 and TS81 are read out.

Thereafter, at time t37, the address MA
X “01” is input as 1 and the data of the time slot TS7 is written to the address in the memory 11. On the other hand, the address MA2 has x “06” according to the above.
Is input, and the time slot TS2 is read as the data DO. Thereafter, at time t39 and time t40, x “4F” and x “5” are added to the address MA1.
F "are input, and the data of the time slots TS95 and TS96 are respectively written into the corresponding address of the memory 11. At these same times, x" 5E "and x" 5F "are added to the address MA2 according to the above. Given data of time slots TS80 and TS96 are data D
Read as O.

When a frame pulse FP is generated at time t42 and the next frame is generated, MENSEL
The signal switches from the “H” level to the “L” level, the data of the first time slot TS1 is input, and the address value is sequentially input to the storage address SA and the output address RA. As a result, the operation is the reverse of that at the time t31, and the selector 13 outputs the read address RA as the address MA1, and the selector 14 outputs the storage address SA as the address MA2. In addition, while the memory 11 is in the read mode, the memory 12 is in the write mode, and the selector 15 is the memory 11 in the read mode.
Is output as data DO.

By a series of these operations, address MA
The data of the time slot TS1 is read out from the address x “00” of the memory 11 designated by 1 as data DO1, and is supplied to the speed converter 6 as data DO as it is. The time slot T given on the data DT
The memory 12 in which the data of S1 is specified by the address MA2
At the address x “00”. Thereafter, the operation is the same as described above, and the operation from time t42 to time t43 is performed from time t43 to time t47. That is, during this period, x “01” of the memory 11 is used.
~ X "04" to time slots TS17, TS3
3, the data of TS49 and TS65 are read, and these data are supplied to the speed conversion unit 6 via the selector 15. At the same time, the address MA2 is sequentially incremented by x “10”, so that x
The data of the time slots TS2 to TS5 are written into the addresses “10”, x “20”, x “30”, and x “40”, respectively. And time t4 after this
The same applies to the subsequent frames, and the series of operations described above is repeatedly performed for each frame after the next frame. Note that the memory 2 described above (from time t31 to time t31)
In parallel with the data read operation from the memory 1 (until time 41) or the memory 1 (after time t42), the speed conversion processing by the speed conversion unit 6 is performed as in the conventional case.

As described above, in this embodiment, the MENS
Since the level of the EL signal is switched every frame,
While the MENSEL signal is at “H” level, the memory 1
1 is write-only, and the memory 12 is read-only, while the memory 11 is read-only and the memory 12 is write-only while the MENSEL signal is at the "L" level. During one specific frame period, data of time slots sequentially input as data DT at fixed time intervals is stored in the memory 11 designated by the storage address SA.
Alternatively, the addresses are sequentially stored in the addresses of the memory 12. On the other hand, during the same frame period, time slot data is sequentially read from the address of the memory 12 or the memory 11 specified by the read address RA, and the speed conversion unit 6 performs speed conversion processing.

As described above, physically two memories for rearranging time slots are provided, one of which is used for write processing and the other is used for read processing. Thus, the process of storing the data in the memory and the process of reading the rearranged time slot data from the memory can be performed at independent timings. Therefore, it becomes easy to calculate the read timing of the time slot data required for the speed conversion, and a plurality of TSI
It is possible to cope with a plurality of types of multiplexed signals having various speeds using only a single TSI unit without using any unit.

[0036]

As described above, according to the present invention, the time slots of the input frame are converted into the speeds of the output frame by rearranging the time slots of the input frame in the order determined from the formats of the input and output frames. The operation of storing in the order and the operation of sequentially reading the stored time slots of the input frame are performed independently of each other. Therefore, in the invention according to claim 2, two storage means are provided for storing a time slot of an input frame, and reading is performed from the other storage means during writing to one storage means. It is composed. In the invention according to claim 3,
The relationship between writing and reading with respect to the two storage units is switched using a frame pulse as a trigger. This eliminates the need to control the write operation and the read operation for one memory so as not to overlap each other as in the related art, and allows these operations to be performed in parallel. Can be done. Further, the rearranged time slot data can be read from the other storage unit independently of the write operation to one storage unit. Therefore, there is no problem such as when the read operation overtakes or overtakes the write operation as in the related art, and even if only a single circuit is provided for time slot rearrangement, Various multiplexed signals with different speeds can be handled.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a TSI unit provided in a transmission device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the TSI unit according to the embodiment.

FIG. 3 shows a TS provided in a transmission device according to the related art.
FIG. 3 is a block diagram illustrating a configuration of an I unit.

FIG. 4 is a timing chart showing an operation of a TSI unit according to a conventional technique.

FIG. 5 is an explanatory diagram showing an example of a frame format of a frame to be rearranged in a time slot, which is a format of a frame having a speed of 6.3 Mbit / sec.

FIG. 6 is an explanatory diagram showing an example of a frame format of a frame to be rearranged in a time slot, which is a frame format having a speed of 19.44 Mbit / sec.

[Explanation of symbols]

6 speed converter, 11, 12 memory, 13-15 selector, 16-18 inverter

Claims (3)

[Claims] 1. A transmission apparatus for converting the speed of a generated frame obtained by rearranging time slots of an input frame in an order determined from respective formats of an input frame and an output frame into a speed of the output frame, and transmitting the output frame. The operation of storing the time slots of the input frame in the order and the operation of sequentially reading out the stored time slots of the input frame to generate the generated frame are performed independently of each other. Wherein the rearrangement is performed for each frame. 2. A transmission apparatus for converting the speed of a generated frame obtained by rearranging time slots of the input frame in an order determined from each format of an input frame and an output frame into the speed of the output frame and transmitting the output frame, First and second storage means for storing a time slot of an input frame; and reading from the second storage means during writing to the first storage means, wherein the second storage means Control means for controlling a write instruction and a read instruction to the first storage means and the second storage means for each frame so that reading is performed from the first storage means during a period in which writing is performed. A transmission device comprising: 3. The method according to claim 2, wherein the control unit switches between writing and reading with respect to the first storage unit and the second storage unit by using a frame pulse that becomes valid at the beginning of each frame as a trigger. Item 3. The transmission device according to Item 2.