JP2000232109A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively and efficiently perform heat treatment of a semiconductor device for hydrogenation without exposing a semiconductor substrate newly after all layers are formed by arranging respective wiring layers on places other than the upper part of a gate of a long channel transistor. SOLUTION: A long channel transistor 120 and a first interlayer insulation layer 131 are provided on a semiconductor substrate 110. Next, a first wiring layer 141 is provided and the wiring pattern thereof is arranged on places other than the upper part of a gate 121 of the transistor 120. Further, a second interlayer insulation film 132, a second wiring layer 142 and a third interlayer insulation layer 133 are formed successively, and the wiring pattern of the second wiring layer 142 is also arranged on places other than the upper part of the gate 121 in the same way as the first wiring layer 141. Thus, a semiconductor device 100 laminated with respective layers is hydrogenated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer wiring layer and a method of manufacturing the same, and more particularly to a structure and a method of forming a wiring layer.

[0002]

2. Description of the Related Art Conventionally, in the manufacturing process of a semiconductor device having a multilayer wiring layer such as a MOS type semiconductor device, about 400
Generally, the hydrogenation heat treatment is performed in a hydrogen-containing atmosphere at about ° C. The purpose is to obtain an electrically stable gate oxide film by bonding hydrogen to unreacted silicon (for oxygen) generated at the interface between the semiconductor substrate and the gate oxide film in the semiconductor device manufacturing process. Yes.

Conventionally, such a hydrogenation heat treatment is generally performed after all the layers such as a wiring layer and an insulating layer have been stacked, and is insufficient for a short channel transistor having a gate length of about 1 μm or less. Effect was obtained. However, the effect decreases as the gate length increases, and in particular, the effect decreases remarkably in a transistor having a gate length of several tens μm or more. The reason will be described below.

When the gate length is short, the hydrogen is easily diffused and the gate oxide film is effectively improved because the gate area is small and the wiring area is small in the upper wiring layer. Becomes possible. On the other hand, the long channel transistor is arranged at the periphery of the semiconductor chip,
It is common to provide a large-area wiring layer for power supply or ground immediately above it, and such a wiring layer is made of Ti,
Generally, it is made of a material that is difficult to transmit hydrogen, such as a barrier metal such as TiN, TiW, and Mo, and Al. Therefore,
If the gate length is large, diffusion of hydrogen is hindered, and the gate oxide film cannot be sufficiently improved.

Therefore, various researches and developments have been made to solve such problems.

First, not after all layers have been formed,
As a method of performing hydrogenation heat treatment at a stage where hydrogen diffusion can be performed effectively, for example, Japanese Patent Application Laid-Open No. 1-2517
No. 39 discloses that a hydrogenation heat treatment is performed before forming a wiring layer. Japanese Patent Application Laid-Open No. 9-641
No. 94 discloses a method of performing a hydrogenation heat treatment at a stage where a wiring contact hole communicating with the surface of a semiconductor substrate is provided on an insulating layer.

As a method of effectively performing a hydrogenation heat treatment after forming all the layers,
A method of providing a hole communicating with the surface of a semiconductor substrate from outside a part of a semiconductor device and performing a hydrogenation heat treatment on the hole is disclosed in
No. 21424.

[0008]

However, each of the above methods has the following problems.

First, in each of the methods disclosed in Japanese Patent Application Laid-Open Nos. 1-251739 and 9-64194, a hydrogenation heat treatment is performed at an intermediate stage of the manufacturing process. Alternatively, since a plasma process such as a plasma CVD method is used, and the upper wiring layer and the gate oxide film are in electrical contact with each other, there is a problem that the gate oxide film is damaged by the plasma. Therefore,
It has been desired to develop a method for effectively performing the hydrogenation heat treatment after all the steps are completed.

The methods disclosed in JP-A-9-64194 and JP-B-48-21424 all enhance the effect of the hydrogenation heat treatment by diffusing hydrogen through holes communicating with the surface of the semiconductor substrate. On the other hand, there is a possibility that an insulating film may be formed at the bottom of the hole due to entrainment in the atmosphere during the hydrogenation heat treatment, and this insulating film needs to be removed again, which is not desirable in terms of manufacturing efficiency. Especially when the semiconductor device is a silicide product, a reduction reaction occurs when hydrogen comes into contact with the silicide layer, and as a result, ohmic contact may not be realized. could not. Therefore, it has been desired to develop a method for performing hydrogenation heat treatment effectively without forming such holes.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a structure capable of performing hydrogenation heat treatment effectively and efficiently after forming all layers and without exposing a new semiconductor substrate. , As well as a method for producing the same.

[0012]

According to the present invention, there is provided a semiconductor device having a multi-layer wiring, wherein each wiring layer has a structure arranged other than above a gate of a long channel transistor. It is characterized by.
As a result, since the wiring layer that inhibits the diffusion of hydrogen does not exist above the long channel gate in the hydrogenation heat treatment step, the hydrogen diffuses sufficiently into the gate oxide film even if the hydrogenation heat treatment is performed after all the layers are formed. As a result, the effect of improving the characteristics of the gate oxide film is improved.

Further, the semiconductor device of the present invention is characterized in that each wiring layer of the semiconductor device having a multilayer wiring has a structure in which a slit is provided at least above a gate of a long channel transistor. Thereby, even if the hydrogenation heat treatment is performed after all the layers are formed, the hydrogen is sufficiently diffused from the slit portion provided in the wiring layer into the long channel gate oxide film, and the effect of improving the characteristics of the gate oxide film is improved. .

Further, in the method of manufacturing a semiconductor device according to the present invention, in the process of manufacturing a semiconductor device having a multi-layered wiring layer, each wiring layer is arranged so as to avoid the upper part of the gate of the long channel transistor, and after all the laminating steps have been completed, It is characterized by performing heat treatment. Accordingly, in the hydrogenation heat treatment step, since the wiring layer that inhibits the diffusion of hydrogen does not exist above the long channel gate, hydrogen is sufficiently diffused into the gate oxide film, and the effect of improving the characteristics of the gate oxide film is improved. Further, by performing the hydrogenation heat treatment after completion of all the laminating steps, the damage of the gate oxide film due to the plasma is recovered, and the quality of the product is improved.

Further, in the method of manufacturing a semiconductor device according to the present invention, in the manufacturing process of a semiconductor device having a multi-layer wiring layer, a slit portion is provided in each wiring layer at least above the gate of the long channel transistor, and hydrogen is formed after all the laminating steps are completed. A chemical heat treatment. This allows
Hydrogen is sufficiently diffused from the slit portion provided in the wiring layer into the long channel gate oxide film, and the effect of improving the characteristics of the gate oxide film is improved. Further, by performing the hydrogenation heat treatment after completion of all the laminating steps, the damage of the gate oxide film due to the plasma is also recovered, and the quality of the product is improved.

Conventionally, a wiring pattern of a wiring layer formed above a gate oxide film has been designed from the viewpoint of a circuit configuration of a semiconductor device. However, in the present invention, a specific wiring pattern is designed from the viewpoint of improving the effect of the hydrogenation heat treatment performed later.

Specifically, in the hydrogenation heat treatment step, a region where no wiring layer exists is provided above the gate so that hydrogen can diffuse from the surface of the semiconductor device to the gate oxide film of the long channel transistor. It is.

More specifically, there is a method of designing a wiring pattern so that no wiring is arranged above the long channel gate. Further, there is a method of providing a slit portion at least in the wiring above the long channel gate. In the latter method, it is preferable that the restriction on the wiring pattern design, which is an inevitable problem in the former method, is relaxed and the degree of freedom of the wiring pattern is increased.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Regarding a first embodiment of the present invention,
This will be described below. FIG. 1 is a top view of one embodiment of the semiconductor device of the present invention, and FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. The structure of the semiconductor device 100 will be described along the manufacturing process.

On a semiconductor substrate 110, a long-channel transistor 120 and a first interlayer insulating layer 131 are provided by a process similar to the conventional one. Next, a first wiring layer 141 is provided. At this time, the wiring pattern of the first wiring layer 141 is arranged at a place other than above the gate 121 of the transistor 120. That is, no wiring exists above the gate 121.

Next, a second interlayer insulating layer 132, a second wiring layer 142, and a third interlayer insulating layer 133 are formed in this order. The wiring pattern of the second wiring layer 142 is the same as that of the first wiring layer 141. Are arranged in places other than the upper part of the gate 121.

The hydrogenation heat treatment is performed on the semiconductor device 100 on which the respective layers are stacked as described above. The hydrogenation heat treatment is performed in a hydrogen-containing atmosphere at about 400 ° C. as in the conventional case. As described above, since no wiring layer exists above the gate 121, hydrogen is sufficiently diffused from outside the semiconductor device 100 to the gate 121 in the hydrogenation heat treatment step,
The effect of improving the electrical characteristics of the semiconductor device 100 is enhanced.

Next, a second embodiment of the present invention will be described. FIG. 3 is a top view of one embodiment of the semiconductor device of the present invention.

The semiconductor device of the present embodiment has a structure in which a wiring is also present above the gate, unlike the first embodiment. Then, as shown in FIG. 3, a slit portion 310 is provided in the wiring above the gate. With such a structure, in the hydrogenation heat treatment performed after the lamination process of each layer, hydrogen is diffused from the slit portion 310, and the effect of improving the electrical characteristics of the semiconductor device is enhanced.

The slit section 130 may be provided not only above the gate but also over a wider area, but it is necessary to consider the effects of electromigration (hereinafter referred to as EM) and stress migration (hereinafter referred to as SM). . For example, the life is calculated in advance by using a simulation, or an EM test and an SM test are actually performed on a wiring pattern in which slits are actually provided.
Needs to be confirmed to be 10 years or more.

[0026]

(Embodiment 1) A first embodiment of the present invention will be described. In the present embodiment, a hydrogenation heat treatment is performed on the n-type semiconductor device 400 shown in FIG. An n-type transistor 420 having a gate length of 20 μm is formed on a silicon substrate 410, and then an insulating oxide film, that is, a first interlayer insulating layer 131 is formed by LPCVD. Next, an Al alloy layer is deposited by a sputtering method, and a first wiring layer 141 is formed by patterning by lithography and CF4 based etching. FIG. 5 shows a top view of the wiring pattern of the first wiring layer 141. This wiring pattern 500 is such that no Al alloy wiring is arranged above the gate 421 of the n-type transistor 420.

Next, an oxide film grown at a low temperature, that is, a second interlayer insulating layer 132 is formed by a plasma CVD method. Thereafter, an Al alloy layer is deposited by a sputtering method, and the second wiring layer 142 is patterned by lithography and CF ₄ -based etching. To form As for the second wiring layer, the wiring pattern shown in FIG. 5 is employed similarly to the first wiring layer. Further, the third interlayer insulating layer 133 is formed, and the step of laminating all the layers is completed.

After the stacking step, the n-type semiconductor device is subjected to a hydrogenation heat treatment for 10 to 20 minutes in a hydrogen atmosphere at a furnace treatment temperature of about 400 ° C. using a furnace furnace.

(Embodiment 2) A second embodiment of the present invention will be described. As in the first embodiment, an n-type transistor 420 having a gate length of 20 μm and a first interlayer insulating layer 131 are formed on a silicon substrate 410. Next, an Al alloy layer is deposited by a sputtering method, and the first wiring layer 141 is formed by patterning by lithography and etching of CF ₄ system. The first wiring layer 141 has a structure in which a slit is provided above the gate. The slit portion was arranged in a direction perpendicular to the direction of current flow as shown in FIG. 6 in consideration of the effects of EM and SM. Considering that the wiring width including the space between the slits 310 sufficiently satisfies the wiring reference width through which the power supply current flows, here, the slit 3 having a width of 0.8 μm
10 were provided in six places.

Next, an Al alloy layer is deposited by a sputtering method, and a second wiring layer 142 is formed by lithography patterning and CF ₄ -based etching. As with the first wiring layer 141, the second wiring layer 142 is provided with a slit portion 310 as shown in FIG. Further, the third interlayer insulating layer 133 is formed, and the step of laminating all the layers is completed.

After the completion of the laminating step, the same hydrogenation heat treatment as in the first embodiment is performed.

(Comparative Example) Next, as a comparative example with respect to each of the above embodiments, a conventional n-type semiconductor device having a wiring above a gate was manufactured.

As in the first embodiment, an n-type transistor 420 having a gate length of 20 μm and a first interlayer insulating layer 131 are formed on a silicon substrate 410, and then an Al alloy layer is deposited by a sputtering method and lithography is performed. The first wiring layer 141 is formed by patterning and CF ₄ -based etching. At this time, there is no restriction on the wiring pattern of the first wiring layer 141, and no slit portion as in the second embodiment is provided. Therefore, as shown in FIG. 7, the wiring exists over the entire surface of the gate.

Next, an Al alloy layer is deposited by a sputtering method, and a second wiring layer 142 is formed by lithography patterning and CF ₄ -based etching. The second wiring layer 142 is not particularly limited as in the first wiring layer 141. Further, a third interlayer insulating layer 133 is formed,
The stacking process of all layers is completed.

After the lamination step, the same hydrogenation heat treatment as in the first embodiment is performed.

With respect to each of the N-type semiconductor devices obtained in Example 1, Example 2 and Comparative Example, IOH and IP
The current values in the U and IPD circuits were measured by a tester, and the results are shown in the table of FIG. Example 1
In this case, the current value is significantly increased as compared with the comparative example, and the effect of improving the electrical characteristics by the hydrogenation heat treatment is remarkable. Further, also in Example 2, the current value increases, and an effect of improving the electrical characteristics is observed. The effect of the second embodiment is smaller than that of the first embodiment, but is superior to the first embodiment in that the restriction on the wiring pattern can be minimized.

[0037]

As described above, according to the present invention, it is possible to carry out the hydrogenation heat treatment effectively and efficiently after forming all the layers and without exposing the semiconductor substrate newly. .

[Brief description of the drawings]

FIG. 1 is a top view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a side view of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a top view of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view of the n-type semiconductor device obtained according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram of a wiring pattern according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram of a wiring pattern according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view of an n-type semiconductor device according to a comparative example.

FIG. 8 is a table showing measurement results of electrical characteristics of N-type semiconductor devices in each of Examples and Comparative Examples.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 semiconductor device 110 semiconductor substrate 120 transistor 121 gate 131-133 interlayer insulating layer 141-142 wiring layer 310 slit portion 400 n-type semiconductor device 410 silicon substrate 420 n-type transistor

Claims (4)

[Claims] In a semiconductor device having a multilayer wiring,
A semiconductor device having a structure in which each wiring layer is arranged other than above a gate of a long channel transistor. 2. The semiconductor device according to claim 1, wherein each wiring layer of the semiconductor device having a multi-layer wiring has a structure in which a slit is provided at least above a gate of a long channel transistor. 3. In a manufacturing process of a semiconductor device having a multi-layered wiring layer, each wiring layer is arranged so as to avoid an upper part of a gate of a long-channel transistor, and hydrogenation heat treatment is performed after completion of all the laminating steps. Semiconductor device manufacturing method. 4. In a manufacturing process of a semiconductor device having a multilayer wiring layer, a slit portion is provided in each wiring layer at least above a gate of a long channel transistor, and a hydrogenation heat treatment is performed after all the laminating steps are completed. Semiconductor device manufacturing method.