JP2000232171A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be improved in durability by reducing damages to a tunnel oxide film and a method for manufacturing the device. SOLUTION: A semiconductor device has a P-type semiconductor substrate 1, an N-type diffusion layer 2 for programming formed on the substrate 1, and N-type source and drain diffusion layers 3 and 4 formed on one side of the diffusion layer 2 on the substrate 1. The device also has a lower N-type diffusion layer 5 formed in the middle section of the substrate 1 so that the layer 5 may be positioned below the diffusion layer 2, a tunnel oxide film 6 and a channel-section gate oxide film 7 respectively formed on the diffusion layer 2 and N-type source and drain diffusion layers 3 and 4, and floating gates 8 and 9 respectively formed on the oxide films 6 and 7. The electrons which pass through the tunnel oxide film 6 from the floating gate 8 due to a tunnel phenomenon drop onto the lower-layer N-type diffusion layer 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device such as an electrically erasable nonvolatile recording device (EEPROM) and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as this type of semiconductor device,
There is a method in which electrons injected into a floating gate are injected from a buried diffusion layer into a semiconductor substrate, and the electrons are accelerated by a high electric field depletion layer between the substrate and the source / drain diffusion layers to increase the energy to be injected into the floating gate for writing. In the conventional semiconductor device, when electrons are extracted from the floating gate to the N-type diffusion layer for programming, electrons that have tunneled through the tunnel oxide film due to a tunneling phenomenon from the floating gate as shown in FIG. Into the N-type diffusion layer for programming, and the energy of the electrons dropped at this time generates holes in the N-type diffusion layer for programming. Holes generated in (1) of FIG. 10 and not recombined in the N-type diffusion layer for programming are depleted between the N-type diffusion layer for programming and the P-type semiconductor substrate as shown in (2) of FIG. It is accelerated toward the P-type semiconductor substrate by the electric field of the layer.
The holes accelerated by the strong electric field cause impact ionization in the depletion layer to generate electrons in the conduction band. The generated electrons are also accelerated in the depletion layer toward the tunnel gate oxide film. The accelerated electrons cause impact ionization, holes are generated in the valence band, the holes are accelerated again, electrons are further generated in the conduction band, and electrons and holes are generated in an avalanche method.

[0003]

However, in the conventional semiconductor device, the tunnel oxide film is damaged by the accelerated high-energy electrons and the interface state is generated, thereby deteriorating the programming characteristics and the durability. There is a problem of deterioration.

An object of the present invention is to provide a semiconductor device capable of improving the durability by reducing damage to a tunnel oxide film and a method of manufacturing the same.

[0005]

According to a first aspect of the present invention, there is provided a P-type semiconductor substrate, a tunnel oxide film formed on the P-type semiconductor substrate, and a tunnel oxide film. , A programming N-type diffusion layer formed above a P-type semiconductor substrate at a predetermined distance from a tunnel oxide film, and a programming gate N-type diffusion layer. And a lower N-type diffusion layer formed at an intermediate portion of the P-type semiconductor substrate, and electrons passing through the tunnel oxide film from the floating gate due to a tunnel phenomenon fall into the lower N-type diffusion layer. And

According to a second aspect of the present invention, a P-type semiconductor substrate, an N-type diffusion layer for programming formed on the P-type semiconductor substrate, and one side of the N-type diffusion layer for programming are provided. And an N-type drain diffusion layer formed above the P-type semiconductor substrate and a lower N-type diffusion layer formed in the middle of the P-type semiconductor substrate so as to be located below the N-type diffusion layer for programming. A diffusion layer; a tunnel oxide film and a channel portion gate oxide film formed on the programming N-type diffusion layer and the N-type drain diffusion layer, respectively; And two floating gates.

According to a third aspect of the present invention, there is provided a P-type semiconductor substrate, a programming N-type diffusion layer and a cell N-type source diffusion layer formed at predetermined intervals above the P-type semiconductor substrate, A lower N-type diffusion layer formed in the middle of the P-type semiconductor substrate so as to be located below the N-type diffusion layer; a tunnel oxide film formed on the N-type diffusion layer for programming; A first gate oxide film formed on the N-type diffusion layer for programming and the P-type semiconductor substrate so as to surround the film; a floating gate formed on the gate oxide film and the tunnel oxide film; An insulating film formed on the gate; a control gate formed on the insulating film; and a cell N of an N-type diffusion layer for programming.
A second gate oxide film formed on the top of the P-type semiconductor substrate so as to be located on the side opposite to the type source diffusion layer;
An N-type source diffusion layer formed on the P-type semiconductor substrate so as to be located between the gate oxide film and the N-type diffusion layer for programming, and formed on the second gate oxide film And a gate.

According to a fourth aspect of the present invention, a step of forming a tunnel oxide film on a P-type semiconductor substrate, a step of forming a floating gate on the tunnel oxide film, and a step of forming a lower layer in an intermediate portion of the P-type semiconductor substrate Forming an N-type diffusion layer; and forming a programming N-type diffusion layer above the P-type semiconductor substrate at a predetermined distance from the tunnel oxide film so as to be located above the lower N-type diffusion layer. It is characterized by having.

According to a fifth aspect of the present invention, a step of forming a lower N-type diffusion layer in an intermediate portion of a P-type semiconductor substrate, and a step of programming the upper part of the P-type semiconductor substrate so as to be located above the lower N-type diffusion layer Forming an N-type diffusion layer for programming, forming two N-type drain diffusion layers on the P-type semiconductor substrate so as to be located on one side of the N-type diffusion layer for programming, Forming a tunnel oxide film and a channel portion gate oxide film on the diffusion layer and the N-type drain diffusion layer, respectively; and forming a floating gate on the tunnel oxide film and the channel portion gate oxide film, respectively. It is characterized by.

According to a sixth aspect of the present invention, a step of forming a lower N-type diffusion layer in an intermediate portion of a P-type semiconductor substrate, and a step of forming a P-type diffusion layer such that a programming N-type diffusion layer is positioned on the lower N-type diffusion layer. Forming a programming N-type diffusion layer and a cell N-type source diffusion layer at predetermined intervals above a type semiconductor substrate; and forming a first gate oxide film on the programming N-type diffusion layer and the P-type semiconductor substrate. Forming a second gate oxide film on the P-type semiconductor substrate so as to be located on the side of the N-type diffusion layer for programming opposite to the cell N-type source diffusion layer; Forming a tunnel oxide film in the hole so as to be located on the N-type diffusion layer for programming after forming the hole; and forming a floating gate on the first gate oxide film and the tunnel oxide film. Forming a gate on the second gate oxide film; forming an insulating film on the floating gate; forming a control gate on the insulating film; N
Forming an N-type source diffusion layer on the P-type semiconductor substrate so as to be located between the N-type source diffusion layer and the P-type semiconductor substrate.

[0011]

Next, embodiments of the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, a semiconductor device according to a first embodiment of the present invention includes a P-type semiconductor substrate 1, a programming N-type diffusion layer 2 formed on the P-type semiconductor substrate 1, Two N-type drain diffusion layers 3 and 4 formed on the P-type semiconductor substrate 1 so as to be located on one side of the N-type diffusion layer 2 for programming, and below the N-type diffusion layer 2 for programming. Are formed on the lower N-type diffusion layer 5 formed in the middle part of the P-type semiconductor substrate 1 so as to be located on the N-type diffusion layer 2 for programming and the N-type drain diffusion layers 3 and 4, respectively. Tunnel oxide film 6 and channel portion gate oxide film 7, and two floating gates 8 and 9 formed on tunnel oxide film 6 and channel portion gate oxide film 7, respectively.

Further, the semiconductor device has a programming N
An N-type diffusion layer 10 for connection to the N-type diffusion layer 2 and the lower N-type diffusion layer 5, an element isolation film 11 formed on the P-type semiconductor substrate 1, and N-type drain diffusion layers 3, 4. An interlayer insulating film 12 formed on the floating gates 8 and 9 and the element isolation film 11, and a contact hole 13 formed in the interlayer insulating film 12 so as to be located on the N-type diffusion layer 2 for programming. have.

Next, the operation of the semiconductor device of FIG. 1 will be described. To extract electrons from the floating gates 8, 9, the N-type source / drain diffusion layer 3 and the P-type semiconductor substrate 1 are grounded, a high voltage (Vpp) is applied to the N-type diffusion layer 2 for programming, and Electrons are extracted from 8 and 9 into the programming N-type diffusion layer 2 by the FN tunnel phenomenon, and the threshold value of the channel region is set to a depletion state. When electrons are injected into the floating gates 8 and 9, the N-type diffusion layer 2 for programming and the P-type semiconductor substrate 1 are grounded, and the N-type
Is applied with a high voltage (Vpp). Due to the capacitive coupling between the floating gates 8, 9 and the N-type drain diffusion layer 3, the potential of the floating gates 8, 9 rises to near Vpp, and the floating gates 8, 9 and the programming N
Electrons are injected into the floating gates 8 and 9 due to the tunnel phenomenon between the diffusion layers 2 and the threshold value of the channel region increases. In this way, a binary state is created in one cell, and information is programmed.

Next, a method of manufacturing the semiconductor device of FIG. 1 will be described with reference to the drawings. First, as shown in FIG. 2, a plurality of element isolation films 11 are formed on a P-type semiconductor substrate 1.
Next, as shown in FIG. 3, a lower N-type diffusion layer 5 is formed in an intermediate portion of the P-type semiconductor substrate 1 by an ion implantation method. Next, as shown in FIG. 3, a programming N is formed on the P-type semiconductor substrate 1 so as to be located on the lower N-type diffusion layer 5.
The N type diffusion layer 2 is formed by ion implantation, and two N type drain diffusion layers 3 and 4 are formed on the P type semiconductor substrate 1 so as to be located on one side of the N type diffusion layer 2 for programming. Is formed. Next, as shown in FIG.
A tunnel oxide film 6 and a channel gate oxide film 7 are formed on the programming N-type diffusion layer 2 and the N-type drain diffusion layers 3 and 4, respectively. Next, as shown in FIG. 4, the tunnel oxide film 6 and the channel portion gate oxide film 7 are formed.
Floating gates 8 and 9 are formed respectively. Next, as shown in FIG.
4, floating gates 8, 9 and element isolation film 11
An interlayer separation film 12 is formed thereon. Next, as shown in FIG. 1, a contact hole 13 is formed in the interlayer isolation film 12 so as to be located on the N-type diffusion layer 2 for programming. Next, as shown in FIG. 1, a connection N-type diffusion layer 10 for connecting the programming N-type diffusion layer 2 and the lower N-type diffusion layer 5 through a contact hole 13 by ion implantation.
To form

Next, a second embodiment of the present invention will be described. As shown in FIG. 5, a semiconductor device according to a second embodiment of the present invention includes a P-type semiconductor substrate 21 and a programming N-type substrate formed at a predetermined interval above the P-type semiconductor substrate 21. A diffusion layer 22 and a cell N-type source diffusion layer 23; and a lower N-type diffusion layer 24 formed in an intermediate portion of the P-type semiconductor substrate 21 so as to be located below the first N-type diffusion layer 22 for programming. , N for programming
Oxide film 25 formed on type diffusion layer 22
And a first gate oxide film 26 formed on the N-type diffusion layer 22 for programming and the P-type semiconductor substrate 1 so as to surround the tunnel oxide film 25, and the first gate oxide film 26 and the tunnel Floating gate 27 formed on oxide film 25 and ONO film (insulating film) formed on floating gate 27
28, a control gate 29 formed on the ONO film 28, and an N-type diffusion layer 22 for programming.
A second gate oxide film 30 formed on the upper portion of the P-type semiconductor substrate 21 so as to be located on the opposite side of the cell N-type source diffusion layer 23, and the second gate oxide film 30 and the N-type It has an N-type source diffusion layer 31 formed on the P-type semiconductor substrate 21 so as to be located between the diffusion layer 22 and a gate 32 formed on the second gate oxide film 30. .

The semiconductor device includes an N-type drain diffusion layer 33 formed on the P-type semiconductor substrate 21 so as to be located on the side of the second gate oxide film 30 opposite to the N-type source diffusion layer 31. The N-type drain diffusion layer 33 and the lower N
N-type diffusion layer 34 for connection to type diffusion layer 24 and element isolation film 35 formed on P-type semiconductor substrate 21
A second programming N-type diffusion layer 23, a control gate 29, an N-type source diffusion layer 31, an N-type drain diffusion layer 33, and an interlayer insulating film 36 formed on an element isolation film 35; And a contact hole 37 formed in the interlayer insulating film 36 so as to be located on the N-type drain diffusion layer 33.

Next, a method of manufacturing the semiconductor device of FIG. 6 will be described with reference to the drawings. First, as shown in FIG. 6, a lower N-type diffusion layer 24 is formed in an intermediate portion of a P-type semiconductor substrate 21 by an ion implantation method. Next, as shown in FIG.
The programming N-type diffusion layer 22 and the cell N-type diffusion layer 23 are arranged at a predetermined interval above the P-type semiconductor substrate 21 so that the first programming N-type diffusion layer 22 is located on the type diffusion layer 24. It is formed by an ion implantation method. Next, as shown in FIG.
A gate oxide film 26 is formed on the P-type semiconductor substrate 21 and the P-type semiconductor substrate 21 so that a gate oxide film 26 is formed on the P-type semiconductor substrate 21 so as to be located on the opposite side of the cell N-type diffusion layer 23 of the programming N-type diffusion layer 22. A gate oxide film 30 is formed. Next, FIG.
As shown in FIG. 7, after forming a hole in the first gate oxide film 26, a tunnel oxide film 25 is formed in the hole so as to be located on the first N-type diffusion layer 22 for programming. Next, as shown in FIG. 7, the first gate oxide film 2
6 and tunnel oxide film 25, a floating gate 27 is formed, and a gate 3 is formed on second gate oxide film 30.
Form 2 Next, an ONO film (insulating film) 28 is formed on the floating gate 27, as shown in FIG. Next, a control gate 29 is formed on the ONO film 28 as shown in FIG. Next, as shown in FIG. 8, an N-type source diffusion layer 31 is ion-implanted above the P-type semiconductor substrate 21 so as to be located between the second gate oxide film 30 and the N-type diffusion layer 22 for programming. An N-type drain diffusion layer 33 is formed on the P-type semiconductor substrate 21 so as to be formed by the method and to be located on the side of the second gate oxide film 30 opposite to the N-type source diffusion layer 31. Next, FIG.
As shown in FIG. 7, an interlayer insulating film 36 is formed on the cell N-type source diffusion layer 23, the control gate 29, the N-type source diffusion layer 31, the N-type drain diffusion layer 33, and the element isolation film 35.
To form Next, as shown in FIG. 5, a contact hole 37 is formed in the interlayer insulating film 36 so as to be located on the N-type drain diffusion layer 33. Next, as shown in FIG.
An N-type diffusion layer for connection 34 connecting the N-type drain diffusion layer 33 and the lower N-type diffusion layer 24 is formed through a contact hole 37 by an ion implantation method.

Next, the operation of the semiconductor device according to the first and second embodiments of the present invention will be described. Holes are generated in the N-type diffusion layer for programming 2 (22) by electrons tunneled from the tunnel oxide film 6 (25), and between the N-type diffusion layer for programming 2 (22) and the P-type semiconductor substrate 1 (21). Is accelerated by the depletion layer. However, by providing the lower N-type diffusion layer 5 (24) and making the potential the same as that of the programming N-type diffusion layer 2 (22), the band is bent as shown in FIG. 9 and the holes are accelerated until impact ionization occurs. It is hard to be done. Thereby, since no electrons are generated in the conduction band, damage to tunnel oxide film 6 (25) can be suppressed. In addition, even when holes pass through the depletion layer between the N-type diffusion layer for programming 2 (22) and the P-type semiconductor substrate 1 (21), the lower N-type diffusion layer 5 (2
The number of holes is reduced due to recombination in 4). Further, the holes remaining without being recombined even in the lower N-type diffusion layer 5 (24) are accelerated by the depletion layer between the lower N-type diffusion layer 5 (24) and the P-type semiconductor substrate 1 (21), and have an impact as before. Although ionization occurs and electrons are generated in the conduction band, they are generated in a portion farther than the tunnel oxide film 6 (25), so that the tunnel oxide film 6 (25) is not damaged.

The present invention can be applied to a semiconductor device in which electrons tunneling through an oxide film from a floating gate using a tunnel phenomenon fall into a lower N-type diffusion layer 5 (24).

[0020]

According to the present invention, the damage to the tunnel oxide film can be reduced by providing the lower N-type diffusion layer below the N-type diffusion layer for programming, so that the durability can be improved. That is, according to the present invention, the number of repetitions of data writing and erasing can be increased.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view showing a main part of a semiconductor device as a first embodiment of the present invention.

FIG. 2 is a view illustrating a step of manufacturing the semiconductor device of FIG. 1;

FIG. 3 is a diagram for explaining another process for manufacturing the semiconductor device of FIG. 1;

FIG. 4 is a view for explaining another step of manufacturing the semiconductor device of FIG. 1;

FIG. 5 is a partial cross-sectional view showing a main part of a semiconductor device as a second embodiment of the present invention.

FIG. 6 is a view illustrating a step of manufacturing the semiconductor device of FIG. 5;

FIG. 7 is a view illustrating another step of manufacturing the semiconductor device of FIG. 5;

FIG. 8 is a diagram for explaining another process for manufacturing the semiconductor device of FIG. 5;

FIG. 9 is a diagram for explaining an operation of the semiconductor device of FIGS. 1 and 5;

FIG. 10 is a diagram illustrating an operation of a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 P-type semiconductor substrate 2 N-type diffusion layer for programming 3 N-type drain diffusion layer 4 N-type drain diffusion layer 5 Lower N-type diffusion layer 6 Tunnel oxide film 7 Channel gate oxide film 8, 9 Floating gate 10 N-type for connection Diffusion layer 11 Element isolation film 12 Interlayer insulating film 13 Contact hole 21 P-type semiconductor substrate 22 N-type diffusion layer for programming 23 Cell N-type source diffusion layer 24 Lower N-type diffusion layer 25 Tunnel oxide film 26 First gate oxide film 27 Floating gate 28 ONO film (insulating film) 29 Control gate 30 Second gate oxide film 31 N-type source diffusion layer 32 Gate 33 N-type drain diffusion layer 34 N-type diffusion layer for connection 35 Element isolation film 36 Interlayer insulation film 37 Contact hole

[Procedure amendment]

[Submission date] November 8, 1999 (1999.11.
8)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

Patent application title: Semiconductor device and method of manufacturing the same

[Claims]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device such as an electrically erasable nonvolatile recording device (EEPROM) and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as this type of semiconductor device,
There is a method in which electrons injected into a floating gate are injected from a buried diffusion layer into a semiconductor substrate, and the electrons are accelerated by a high electric field depletion layer between the substrate and the source / drain diffusion layers to increase the energy to be injected into the floating gate for writing. In the conventional semiconductor device, when electrons are extracted from the floating gate to the N-type diffusion layer for programming, electrons that have tunneled through the tunnel oxide film due to a tunneling phenomenon from the floating gate as shown in FIG. Into the N-type diffusion layer for programming, and the energy of the electrons dropped at this time generates holes in the N-type diffusion layer for programming. Holes generated in (1) of FIG. 10 and not recombined in the N-type diffusion layer for programming are depleted between the N-type diffusion layer for programming and the P-type semiconductor substrate as shown in (2) of FIG. It is accelerated toward the P-type semiconductor substrate by the electric field of the layer.
The holes accelerated by the strong electric field cause impact ionization in the depletion layer to generate electrons in the conduction band. The generated electrons are also accelerated in the depletion layer toward the tunnel gate oxide film. The accelerated electrons cause impact ionization, holes are generated in the valence band, the holes are accelerated again, electrons are further generated in the conduction band, and electrons and holes are generated in an avalanche method.

[0003]

However, in the conventional semiconductor device, the tunnel oxide film is damaged by the accelerated high-energy electrons and the interface state is generated, thereby deteriorating the programming characteristics and the durability. There is a problem of deterioration.

An object of the present invention is to provide a semiconductor device capable of improving the durability by reducing damage to a tunnel oxide film and a method of manufacturing the same.

[0005]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a P-type semiconductor substrate; a tunnel oxide film formed on the P-type semiconductor substrate; A floating gate formed on the film, an N-type diffusion layer for programming formed on the P-type semiconductor substrate below the floating gate, and a layer located below the N-type diffusion layer for programming. The lower layer N formed in the middle part of the P-type semiconductor substrate
And an N-type diffusion layer for programming and the lower N-type diffusion layer having the same potential.

According to a second aspect of the present invention, a step of forming a tunnel oxide film on a P-type semiconductor substrate, a step of forming a floating gate on the tunnel oxide film, and a step of forming a lower layer in an intermediate portion of the P-type semiconductor substrate Forming an n-type diffusion layer; forming an n-type diffusion layer for programming on the p-type semiconductor substrate below the floating gate so as to be located above the lower n-type diffusion layer; And a step of connecting the mold spreading layer and the lower N-type diffusion layer directly or via a transistor.

[0007]

Next, embodiments of the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, a semiconductor device according to a first embodiment of the present invention includes a P-type semiconductor substrate 1, a programming N-type diffusion layer 2 formed on the P-type semiconductor substrate 1, Two N-type drain diffusion layers 3 and 4 formed on the P-type semiconductor substrate 1 so as to be located on one side of the N-type diffusion layer 2 for programming, and below the N-type diffusion layer 2 for programming. Are formed on the lower N-type diffusion layer 5 formed in the middle part of the P-type semiconductor substrate 1 so as to be located on the N-type diffusion layer 2 for programming and the N-type drain diffusion layers 3 and 4, respectively. Tunnel oxide film 6 and channel portion gate oxide film 7, and two floating gates 8 and 9 formed on tunnel oxide film 6 and channel portion gate oxide film 7, respectively.

Further, the semiconductor device has a programming N
An N-type diffusion layer 10 for connection to the N-type diffusion layer 2 and the lower N-type diffusion layer 5, an element isolation film 11 formed on the P-type semiconductor substrate 1, and N-type drain diffusion layers 3, 4. An interlayer insulating film 12 formed on the floating gates 8 and 9 and the element isolation film 11, and a contact hole 13 formed in the interlayer insulating film 12 so as to be located on the N-type diffusion layer 2 for programming. have.

Next, the operation of the semiconductor device of FIG. 1 will be described. To extract electrons from the floating gates 8, 9, the N-type source / drain diffusion layer 3 and the P-type semiconductor substrate 1 are grounded, a high voltage (Vpp) is applied to the N-type diffusion layer 2 for programming, and Electrons are extracted from 8 and 9 into the programming N-type diffusion layer 2 by the FN tunnel phenomenon, and the threshold value of the channel region is set to a depletion state. When electrons are injected into the floating gates 8 and 9, the N-type diffusion layer 2 for programming and the P-type semiconductor substrate 1 are grounded, and the N-type
Is applied with a high voltage (Vpp). Due to the capacitive coupling between the floating gates 8, 9 and the N-type drain diffusion layer 3, the potential of the floating gates 8, 9 rises to near Vpp, and the floating gates 8, 9 and the programming N
Electrons are injected into the floating gates 8 and 9 due to the tunnel phenomenon between the diffusion layers 2 and the threshold value of the channel region increases. In this way, a binary state is created in one cell, and information is programmed.

Next, a method of manufacturing the semiconductor device of FIG. 1 will be described with reference to the drawings. First, as shown in FIG. 2, a plurality of element isolation films 11 are formed on a P-type semiconductor substrate 1.
Next, as shown in FIG. 3, a lower N-type diffusion layer 5 is formed in an intermediate portion of the P-type semiconductor substrate 1 by an ion implantation method. Next, as shown in FIG. 3, a programming N is formed on the P-type semiconductor substrate 1 so as to be located on the lower N-type diffusion layer 5.
The N type diffusion layer 2 is formed by ion implantation, and two N type drain diffusion layers 3 and 4 are formed on the P type semiconductor substrate 1 so as to be located on one side of the N type diffusion layer 2 for programming. Is formed. Next, as shown in FIG.
A tunnel oxide film 6 and a channel gate oxide film 7 are formed on the programming N-type diffusion layer 2 and the N-type drain diffusion layers 3 and 4, respectively. Next, as shown in FIG. 4, the tunnel oxide film 6 and the channel portion gate oxide film 7 are formed.
Floating gates 8 and 9 are formed respectively. Next, as shown in FIG.
4, floating gates 8, 9 and element isolation film 11
An interlayer separation film 12 is formed thereon. Next, as shown in FIG. 1, a contact hole 13 is formed in the interlayer isolation film 12 so as to be located on the N-type diffusion layer 2 for programming. Next, as shown in FIG. 1, a connection N-type diffusion layer 10 for connecting the programming N-type diffusion layer 2 and the lower N-type diffusion layer 5 through a contact hole 13 by ion implantation.
To form

Next, a second embodiment of the present invention will be described. As shown in FIG. 5, a semiconductor device according to a second embodiment of the present invention includes a P-type semiconductor substrate 21 and a programming N-type substrate formed at a predetermined interval above the P-type semiconductor substrate 21. A diffusion layer 22 and a cell N-type source diffusion layer 23; and a lower N-type diffusion layer 24 formed in an intermediate portion of the P-type semiconductor substrate 21 so as to be located below the first N-type diffusion layer 22 for programming. , N for programming
Oxide film 25 formed on type diffusion layer 22
And a first gate oxide film 26 formed on the N-type diffusion layer 22 for programming and the P-type semiconductor substrate 1 so as to surround the tunnel oxide film 25, and the first gate oxide film 26 and the tunnel Floating gate 27 formed on oxide film 25 and ONO film (insulating film) formed on floating gate 27
28, a control gate 29 formed on the ONO film 28, and an N-type diffusion layer 22 for programming.
A second gate oxide film 30 formed on the upper portion of the P-type semiconductor substrate 21 so as to be located on the opposite side of the cell N-type source diffusion layer 23, and the second gate oxide film 30 and the N-type It has an N-type source diffusion layer 31 formed on the P-type semiconductor substrate 21 so as to be located between the diffusion layer 22 and a gate 32 formed on the second gate oxide film 30. .

Further, the semiconductor device includes an N-type drain diffusion layer 33 formed on the P-type semiconductor substrate 21 so as to be located on the side of the second gate oxide film 30 opposite to the N-type source diffusion layer 31. The N-type drain diffusion layer 33 and the lower N
N-type diffusion layer 34 for connection to type diffusion layer 24 and element isolation film 35 formed on P-type semiconductor substrate 21
A second programming N-type diffusion layer 23, a control gate 29, an N-type source diffusion layer 31, an N-type drain diffusion layer 33, and an interlayer insulating film 36 formed on an element isolation film 35; And a contact hole 37 formed in the interlayer insulating film 36 so as to be located on the N-type drain diffusion layer 33.

Next, a method of manufacturing the semiconductor device of FIG. 6 will be described with reference to the drawings. First, as shown in FIG. 6, a lower N-type diffusion layer 24 is formed in an intermediate portion of a P-type semiconductor substrate 21 by an ion implantation method. Next, as shown in FIG.
The programming N-type diffusion layer 22 and the cell N-type diffusion layer 23 are arranged at a predetermined interval above the P-type semiconductor substrate 21 so that the first programming N-type diffusion layer 22 is located on the type diffusion layer 24. It is formed by an ion implantation method. Next, as shown in FIG.
A gate oxide film 26 is formed on the P-type semiconductor substrate 21 and the P-type semiconductor substrate 21 so that a gate oxide film 26 is formed on the P-type semiconductor substrate 21 so as to be located on the opposite side of the cell N-type diffusion layer 23 of the programming N-type diffusion layer 22. A gate oxide film 30 is formed. Next, FIG.
As shown in FIG. 7, after forming a hole in the first gate oxide film 26, a tunnel oxide film 25 is formed in the hole so as to be located on the first N-type diffusion layer 22 for programming. Next, as shown in FIG. 7, the first gate oxide film 2
6 and tunnel oxide film 25, a floating gate 27 is formed, and a gate 3 is formed on second gate oxide film 30.
Form 2 Next, an ONO film (insulating film) 28 is formed on the floating gate 27, as shown in FIG. Next, a control gate 29 is formed on the ONO film 28 as shown in FIG. Next, as shown in FIG. 8, an N-type source diffusion layer 31 is ion-implanted above the P-type semiconductor substrate 21 so as to be located between the second gate oxide film 30 and the N-type diffusion layer 22 for programming. An N-type drain diffusion layer 33 is formed on the P-type semiconductor substrate 21 so as to be formed by the method and to be located on the side of the second gate oxide film 30 opposite to the N-type source diffusion layer 31. Next, FIG.
As shown in FIG. 7, an interlayer insulating film 36 is formed on the cell N-type source diffusion layer 23, the control gate 29, the N-type source diffusion layer 31, the N-type drain diffusion layer 33, and the element isolation film 35.
To form Next, as shown in FIG. 5, a contact hole 37 is formed in the interlayer insulating film 36 so as to be located on the N-type drain diffusion layer 33. Next, as shown in FIG.
An N-type diffusion layer for connection 34 connecting the N-type drain diffusion layer 33 and the lower N-type diffusion layer 24 is formed through a contact hole 37 by an ion implantation method.

Next, the operation of the semiconductor device according to the first and second embodiments of the present invention will be described. Holes are generated in the N-type diffusion layer for programming 2 (22) by electrons tunneled from the tunnel oxide film 6 (25), and between the N-type diffusion layer for programming 2 (22) and the P-type semiconductor substrate 1 (21). Is accelerated by the depletion layer. However, by providing the lower N-type diffusion layer 5 (24) and making the potential the same as that of the programming N-type diffusion layer 2 (22), the band is bent as shown in FIG. 9 and the holes are accelerated until impact ionization occurs. It is hard to be done. Thereby, since no electrons are generated in the conduction band, damage to tunnel oxide film 6 (25) can be suppressed. In addition, even when holes pass through the depletion layer between the N-type diffusion layer for programming 2 (22) and the P-type semiconductor substrate 1 (21), the lower N-type diffusion layer 5 (2
The number of holes is reduced due to recombination in 4). Further, the holes remaining without being recombined even in the lower N-type diffusion layer 5 (24) are accelerated by the depletion layer between the lower N-type diffusion layer 5 (24) and the P-type semiconductor substrate 1 (21), and have an impact as before. Although ionization occurs and electrons are generated in the conduction band, they are generated in a portion farther than the tunnel oxide film 6 (25), so that the tunnel oxide film 6 (25) is not damaged.

The present invention can be applied to a semiconductor device in which electrons tunneling through an oxide film from a floating gate using a tunnel phenomenon fall into a lower N-type diffusion layer 5 (24).

[0016]

According to the present invention, the damage to the tunnel oxide film can be reduced by providing the lower N-type diffusion layer below the N-type diffusion layer for programming, so that the durability can be improved. That is, according to the present invention, the number of repetitions of data writing and erasing can be increased.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view showing a main part of a semiconductor device as a first embodiment of the present invention.

FIG. 2 is a view illustrating a step of manufacturing the semiconductor device of FIG. 1;

FIG. 3 is a diagram for explaining another process for manufacturing the semiconductor device of FIG. 1;

FIG. 4 is a view for explaining another step of manufacturing the semiconductor device of FIG. 1;

FIG. 5 is a partial cross-sectional view showing a main part of a semiconductor device as a second embodiment of the present invention.

FIG. 6 is a view illustrating a step of manufacturing the semiconductor device of FIG. 5;

FIG. 7 is a view illustrating another step of manufacturing the semiconductor device of FIG. 5;

FIG. 8 is a diagram for explaining another process for manufacturing the semiconductor device of FIG. 5;

FIG. 9 is a diagram for explaining an operation of the semiconductor device of FIGS. 1 and 5;

FIG. 10 is a diagram illustrating an operation of a conventional semiconductor device.

[Description of Signs] 1 P-type semiconductor substrate 2 N-type diffusion layer for programming 3 N-type drain diffusion layer 4 N-type drain diffusion layer 5 Lower N-type diffusion layer 6 Tunnel oxide film 7 Channel gate oxide film 8, 9 Floating gate DESCRIPTION OF SYMBOLS 10 N-type diffusion layer for connection 11 Element isolation film 12 Interlayer insulating film 13 Contact hole 21 P-type semiconductor substrate 22 N-type diffusion layer for programming 23 Cell N-type source diffusion layer 24 Lower N-type diffusion layer 25 Tunnel oxide film 26 First Oxide film 27 floating gate 28 ONO film (insulating film) 29 control gate 30 second gate oxide film 31 N-type source diffusion layer 32 Gate 33 N-type drain diffusion layer 34 N-type diffusion layer for connection 35 Element isolation film 36 Interlayer insulating film 37 Contact hole

Claims (6)

[Claims] 1. A P-type semiconductor substrate, a tunnel oxide film formed on the P-type semiconductor substrate, a floating gate formed on the tunnel oxide film, and a predetermined distance from the tunnel oxide film And an N-type diffusion layer for programming formed above the P-type semiconductor substrate, and an intermediate portion of the P-type semiconductor substrate located below the N-type diffusion layer for programming. And a lower N-type diffusion layer, wherein electrons passing through the tunnel oxide film from the floating gate due to a tunnel phenomenon fall into the lower N-type diffusion layer. 2. A P-type semiconductor substrate, an N-type diffusion layer for programming formed on the P-type semiconductor substrate, and the P-type semiconductor layer located on one side of the N-type diffusion layer for programming. Two N-type drain diffusion layers formed above a semiconductor substrate; and a lower N-type diffusion layer formed in an intermediate portion of the P-type semiconductor substrate so as to be located below the N-type diffusion layer for programming. And a tunnel oxide film and a channel portion gate oxide film formed on the programming N-type diffusion layer and the N-type drain diffusion layer, respectively, and on the tunnel oxide film and the channel portion gate oxide film, respectively. A semiconductor device comprising: two floating gates formed. 3. A P-type semiconductor substrate; a programming N-type diffusion layer and a cell N-type source diffusion layer formed at predetermined intervals above the P-type semiconductor substrate; A lower N-type diffusion layer formed at an intermediate portion of the P-type semiconductor substrate so as to be located below the tunnel oxide film; a tunnel oxide film formed on the N-type diffusion layer for programming; Surrounding the programming N
A first gate oxide film formed on the type diffusion layer and the P-type semiconductor substrate; a floating gate formed on the gate oxide film and the tunnel oxide film; An insulating film formed; a control gate formed on the insulating film; and the P-type semiconductor substrate so as to be located on a side of the programming N-type diffusion layer opposite to the cell N-type source diffusion layer. A second gate oxide film formed on the P-type semiconductor substrate and located between the second gate oxide film and the programming N-type diffusion layer. A semiconductor device comprising: an N-type source diffusion layer; and a gate formed on the second gate oxide film. 4. A step of forming a tunnel oxide film on a P-type semiconductor substrate, a step of forming a floating gate on the tunnel oxide film, and a lower N-type diffusion layer in an intermediate portion of the P-type semiconductor substrate. And forming a programming N-type diffusion layer on the P-type semiconductor substrate at a predetermined distance from the tunnel oxide film so as to be located on the lower N-type diffusion layer. A method for manufacturing a semiconductor device, comprising: 5. A step of forming a lower N-type diffusion layer in an intermediate portion of a P-type semiconductor substrate; and forming an N-type diffusion for programming on the P-type semiconductor substrate so as to be located on the lower N-type diffusion layer. Forming a layer; forming two N-type drain diffusion layers on the P-type semiconductor substrate so as to be positioned on one side of the programming N-type diffusion layer; Forming a tunnel oxide film and a channel portion gate oxide film on the layer and the N-type drain diffusion layer, respectively; and forming a floating gate on the tunnel oxide film and the channel portion gate oxide film, respectively. A method for manufacturing a semiconductor device, comprising: 6. A step of forming a lower N-type diffusion layer in an intermediate portion of the P-type semiconductor substrate; and forming the lower P-type semiconductor substrate such that a programming N-type diffusion layer is positioned on the lower N-type diffusion layer. The programming N-type diffusion layer and the cell N
Forming a type source diffusion layer; forming a first gate oxide film on the programming N-type diffusion layer and the P-type semiconductor substrate; and forming the cell N-type source diffusion layer of the programming N-type diffusion layer. Forming a second gate oxide film on the P-type semiconductor substrate so as to be located on the opposite side of the P-type semiconductor substrate; and forming a hole in the first gate oxide film on the N-type diffusion layer for programming. Forming a tunnel oxide film in the hole such that the floating gate is formed on the first gate oxide film and the tunnel oxide film, and forming a gate on the second gate oxide film. Forming an insulating film on the floating gate; forming a control gate on the insulating film; and forming a control gate on the floating gate. The method of manufacturing a semiconductor device characterized by a step of forming an N-type source diffusion layer on the P-type semiconductor substrate so as to be located between the programming N-type diffusion layer.