JP2000236332A - Packet switching device and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform an adjusting process by using a processor which has relatively low processing capability by performing an arbitrating process in a time longer than the unit time needed to transfer a single block and holding the right for the connection of an output port until the result of the arbitrating process becomes effective. SOLUTION: Execution time intervals of the process of an arbiter part are set twice as long as the unit time and arbitrating processes B, C, and D are started when time slots S2, S4, and S6 obtained by sectioning the time base with the unit time start. The arbitrating process B performed when the time slot S2 starts only needs to end before the arbitrating process C starts and the time from the start to the end of arbitration may be twice as long as the unit time. Then the arbitrating process B gives the right of connection to output ports 2, 4, 1, and 3 for input ports 1, 2, 3, and 4, the respective input ports send corresponding packets out to the output port having obtained the connection right in the arbitrating process B in the time slot S4, and the output port, connection right obtained in the last process is held until a next arbitrating process becomes effective.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet switching apparatus, and more particularly to, for example, ATM (Asynchronous Transfer).
The present invention relates to a control method and an apparatus suitable for being applied to a packet switching apparatus that switches a packet between a specific input port and an output port using a packet communication technique such as an asynchronous transfer mode.

[0002]

2. Description of the Related Art Control of a conventional packet switch of this type will be described. FIG. 6 is a block diagram showing the overall system configuration of a conventional packet switch. Referring to FIG. 6, the packet switch includes a switch exchange unit 22 for exchanging packets, and input buffer units 10-1 to 10-n for storing packets arriving at input ports (however, in FIG. -3 to 10-n are not shown) and an arbiter unit 21. The switch exchange unit 22 is provided with a specific input highway 2
3 and the output highway 24.

Here, a plurality of input ports 100-1 to 100-1
00-n is a specific output port 101-1 to 101-n
When packets are transmitted simultaneously, packet collision occurs and the data carried by the packet is destroyed. Therefore, at the same timing, the number of input ports that transmit packets to a specific output port is limited to at most one. There is a need.

[0004] The arbiter unit 21 receives a connection request from an input port (input buffer unit), and performs an arbitration process for determining which input port should be given the connection right of each output port so that packet collision does not occur. Execute.

The input buffer units 10-1 to 10-n prepared for each input port are provided with a FIFO for each destination output port.
(First In First Out; first in first out) logical queues 11-1 to 11-n are provided.

The packet input section 12 has an input port 100
-1 to 100-n to identify a destination output port of a packet arriving at the corresponding FIFO logical queue 11-1 to 11-1
1-n.

[0007] When the arbiter 21 has been given the connection right of a certain output port, the packet output unit 13 provides FIFO logical queues 11-1 to 11-1 corresponding to the output port.
1-n, and sends the packet to the input highway 23.

Next, the operation of the conventional packet switch will be described.

Packets arriving at the input ports 100-1 to 100-n are stored at the end of the FIFO logical queues 11-1 to 11-n corresponding to the destination output ports. The request unit 14 of each of the input buffer units 10-1 to 10-n has F
If packets are stored in the IFO logical queue,
The connection request to the corresponding output port is sent to the arbiter unit 21.

The arbiter unit 21 is provided for each input buffer unit 10.
After integrating the connection request signals 30 from -1 to 10-n,
If there is a connection request from a plurality of input ports 100-1 to 100-n to the same output port 101-1 to 101-n (when a conflict occurs), any one of the input ports 100-1 to 100-n Arbitrate to grant connection rights to -n;

After performing the above arbitration for all the output ports, the arbitration result, that is, whether or not the connection right is acquired, is determined by using the contention arbitration signal 31 in each input buffer unit 10.
Notify to -1 to 10-n.

The input buffer unit that has acquired the connection right among the input buffer units 10-1 to 10-n sends a desired packet to the input highway 23, and the switch exchange unit 22 is notified from the arbiter unit 21. Based on the arbitration result, the packet on the input highway 23 is transferred to a predetermined output highway 24.

[0013]

However, the above-mentioned conventional packet switch has the following problems. FIG. 7 is a diagram illustrating the timing for executing the arbitration process and the timing for transmitting the packet from the input buffer unit, with the time required to transfer a single packet as the unit time T. In FIG. 7, in the arbitration process B executed at the beginning of the time slot S2 divided on the time axis by the unit time T and completed at the end of the time slot S2, the input ports # 1, # 2, # 3, # 4 On the other hand, it is determined that the connection right of the output ports # 2, # 4, # 1, and # 3 is given.

In response to this result, the next time slot S
In 3, each input port operates to transmit a packet corresponding to the output port that has acquired the connection right in the arbitration process B. In FIG. 7, PKT (n) indicates that a packet addressed to output port #n is sent.

For example, in time slot S3, input port # 1 is PKT (2), that is, output port # 2.
The packet addressed to is sent.

At the same time, the arbiter 21 starts arbitration processing C at the beginning of the time slot S3 for a packet to be transmitted in the time slot S4.

In the time slot S4, the result of the arbitration process C completed at the end of the time slot S3 (output ports # 1 to # 4, # 2, # 3, and # 4 respectively)
3, # 1, # 2, and # 4).
Each input port operates to transmit a packet corresponding to the output port that has acquired the connection right.

As described above, in the conventional packet switch, the arbitration process is executed for each unit time T required to transfer a single packet. Transmits a packet corresponding to the output port that has acquired the connection right as a result of the arbitration process executed in step (1).

That is, in the conventional packet switch, the arbitration process is completed within the transfer time T of a single packet. In a packet switch that handles fixed-length packets, as the port speed increases, the absolute time required to transfer a single packet becomes shorter. Arbitration processing must be completed. For this reason, it is necessary to use a high-speed and high-performance processor with extremely large processing capacity for the arbiter unit 21 that performs arbitration processing.

In order to reduce the amount of circuit by reducing the buffer of the packet switch, for example, Japanese Unexamined Patent Application Publication No.
Japanese Patent Application No. -292124 discloses a configuration in which a single associative memory manages the arrival level of packets for each output line.

[0021] Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a packet switch having an arbitration process for determining which input port is to be given a connection right to an output port. An object of the present invention is to provide a packet switching device and a control method thereof, which can realize the adjustment process even using a processor having a relatively small processing capacity.

[0022]

According to the present invention, there is provided a method for controlling a packet switch for switching a packet between an input port and an output port, the unit being required to transfer a single packet. It is assumed that the arbitration process is executed at a predetermined time equal to or longer than the time, and the connection right of the output port acquired as a result of the arbitration process is maintained until the result of the next arbitration process becomes valid. As a result, the arbitration process may be completed within a long time equal to or longer than the unit time required to transfer a single packet, and the arbiter unit may be configured using a processor having a small processing capacity.

In the present invention, the input buffer unit provided for each input port is configured to assemble a block from a plurality of packets destined for the same output port, and to execute arbitration processing for each block. Is also good.

With this configuration, the time required to transfer a single block is longer than the unit time required to transfer a single packet, so that it is possible to increase the time required to complete the arbitration process. is there.

Further, the arbitration process is executed at predetermined intervals equal to or longer than the unit time required for transferring a single block, and the connection right of the output port acquired as a result of the arbitration process is determined by the next time. Holds until the result of the arbitration process becomes valid. As a result, the arbitration process may be completed within a long time equal to or longer than the unit time required to transfer a single block, and the arbiter unit may be configured using a processor having a small processing capacity.

[0026]

Embodiments of the present invention will be described. In a preferred embodiment of the present invention, a switch means (22 in FIG. 6) for switching a packet input from an input port (100 in FIG. 6) to an output port (101 in FIG. 6), and a connection to the output port Arbitration means (21 in FIG. 6) for performing arbitration processing for deciding which input port is given the right.
The arbitration means (21 in FIG. 6) executes arbitration processing at every predetermined time which is equal to or longer than the unit time required for transferring one packet or one block composed of a plurality of packets (FIG. 6). 1), the connection right of the output port acquired as a result of the arbitration is retained until the result of the next arbitration process becomes valid.

The arbitration process may be completed within a long time equal to or longer than the unit time required to transfer a single packet (single block), and the arbiter unit may be configured using a processor having a relatively small processing capacity. Can be.

[0028]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; In the embodiment of the present invention, the basic configuration of the packet switch is the same as that shown in FIG.

In one embodiment of the present invention, the arbitration process is executed at intervals of time equal to twice the unit time T, with the time required to transfer a single packet as the unit time T. FIG. 1 is a diagram showing the operation timing of executing the arbitration process in one embodiment of the present invention.

Referring to FIG. 1, in one embodiment of the present invention, in the arbiter 21 of FIG. 6, the time interval for executing the arbitration process is set to twice the unit time T, and the unit time T on the time axis. Delimited time slots S2, S4, S
At the beginning of 6, arbitration processes B, C, and D are started, respectively.

The arbitration process B executed at the beginning of the time slot S2 may be completed before the start of the next arbitration process C. That is, the arbiter unit is allowed to spend up to twice the unit time T from the start to the completion of the arbitration process.

That is, in one embodiment of the present invention,
For example, as the processor used in the arbiter unit 21 shown in FIG. 6, a processor having a processing capacity half that of the conventional system can be used as the arbiter unit.

The arbitration process B includes input ports # 1, # 2, #
Output ports # 2, # 4, and # 4 for # 3 and # 4, respectively.
It is determined that the connection right of # 1, # 3 is given.

In response to the arbitration result, the time slot S
In 4, each input port operates to transmit a packet corresponding to the output port that has acquired the connection right in the arbitration process B. In FIG. 1, PKT (n) indicates that a packet addressed to output port #n is transmitted. For example, in time slot S4, input port # 1
Transmits a PKT (2), that is, a packet addressed to output port # 2.

At the same time, the arbitration process C starts at the beginning of the time slot S4.

At the beginning of time slot S5,
Since the arbitration process C has not been completed, each input port operates so as to transmit a packet corresponding to the output port that has acquired the connection right in the previous arbitration process B.

The arbitration process C completed at the end of the time slot S5 includes input ports # 1, # 2, # 3, #
4, output ports # 3, # 1, # 2, #
4 and the time slots S6 and S
At 7, each input port operates to transmit a packet corresponding to the output port that has acquired the connection right in the arbitration process C.

As described above, the time interval for executing the arbitration process is set to twice the unit time T, and the connection right of the output port acquired in the previous arbitration process is held until the result of the next arbitration process becomes valid. Thus, the time from the start to the completion of the arbitration process can be allowed to be twice as long as the unit time T.

Therefore, the arbiter can be configured even if a processor having a low processing capability is used. Note that the time interval for executing the arbitration process is not limited to twice the unit time T, and can be set to an arbitrary length, and the same effect as in the above-described embodiment can be expected.

Next, a second embodiment of the present invention will be described.
In the second embodiment of the present invention, when a block is composed of two packets, the arbitration process is executed for each block. FIG. 2 is a diagram showing the execution timing of the arbitration process for explaining the second embodiment of the present invention. In the second embodiment of the present invention, a single block is formed from a plurality of packets destined for the same output port.

FIGS. 3 and 4 show the frame format of a block. A plurality of packets are stored in the payload of the frame.

In the example shown in FIG. 3, the same block is composed of only packets belonging to the same service class and having the same output port as the destination.

FIG. 4 shows a case where packets destined for the same output port constitute the same block even if the service class is different.
Here, it is also possible to configure so that the service class ratio of the packets constituting the same block is close to a predetermined ratio based on a required bandwidth or the like.

Referring to FIG. 2, in the second embodiment of the present invention, when a block is composed of two packets, the arbitration process is executed in block units. Here, V represents a unit time required to transfer a single block. As a matter of course, the unit time V is twice the unit time T required to transfer a single packet.

In the second embodiment of the present invention, arbitration processing is executed in units of blocks. Therefore, arbitration processing B, C, and C are respectively performed at the beginning of time slots U1, U2, and U3 divided on the time axis by a unit time V. Start D.

The arbitration process B executed at the beginning of the time slot U1 may be completed before the start of the next arbitration process C. That is, it is allowed to spend up to the unit time V (twice the unit time T) until the processing is completed.

In the second embodiment of the present invention, the arbiter 21 can be constructed using a processor having half the processing capacity as compared with the conventional one.

In the arbitration process B, the input ports # 1, # 2, #
Output ports # 2, # 4, and # 4 for # 3 and # 4, respectively.
1, the connection right of # 3 is determined. In response to this result, in the time slot U2, each input port operates to transmit a block corresponding to the output port whose connection right has been acquired in the arbitration process B.

BLK (n) in FIG. 2 indicates that a block addressed to output port #n is sent. For example, in time slot U2, input port # 1 is BLK
(2) That is, the block addressed to the output port # 2 is transmitted.

At the same time, the arbitration process C is started at the beginning of the time slot U2 for the block transmitted in the time slot U3. In the time slot U3, the result of the arbitration processing C completed at the end of the time slot U2 (the output ports # 3, # 1, # 2, and # 4 respectively correspond to the input ports # 1, # 2, # 3, and # 4). Each of the input ports operates to transmit a block corresponding to the output port that has acquired the connection right.

As described above, by forming a block from two packets and executing the arbitration process in block units, the time that can be spent from the start to the completion of the arbitration process can be transferred to the block. The required unit time V, that is, up to twice the transfer time T of a single packet can be tolerated.
Therefore, it is possible to configure the arbiter unit using a processor having a low processing capability.

It should be noted that the block is not limited to two and can be composed of an arbitrary number of packets, and similar effects can be expected.

FIG. 5 is a diagram showing the execution timing of the arbitration process for explaining the third embodiment of the present invention. FIG.
In the third embodiment of the present invention, when a block is composed of two packets, arbitration is performed every time corresponding to twice the unit time V required to transfer a single block. Execute the process. Naturally, the unit time V is the unit time T required to transfer a single packet.
It is twice as large as

In the third embodiment of the present invention, the time interval for executing the arbitration process is set to twice the unit time V (4 times the unit time T).
The arbitration processes B, C, and D are started at the beginning of the time slots U1, U3, and U5 on the time axis divided by the unit time V. The arbitration process B executed at the beginning of the time slot U1 may be completed by the start of the next arbitration process C.

That is, a unit time U of 2
It is allowed to spend up to twice (4 times the unit time T).

Therefore, it is possible to configure the arbiter unit using a processor having a quarter of the processing capability as compared with the prior art shown in FIG.

In the arbitration process B, the input ports # 1, # 2,
Output ports # 2, # 4, # for # 3, # 4 respectively
A decision has been made to grant the connection right of # 1, # 3.
In response to this arbitration result, in the time slot U3, each input port operates so as to transmit a packet corresponding to the output port that has acquired the connection right in the arbitration process B. In FIG. 5, BLK (n) means that a block addressed to output port #n is sent. For example, in the time slot U3, the input port # 1 sends out a block addressed to the output port # 2.

At the same time, the arbitration process C is started at the beginning of the time slot U3. In time slot U4,
Since the arbitration process C has not been completed, each input port operates to transmit a packet corresponding to the output port whose connection right has been acquired in the previous arbitration process B.

The arbitration process C completed at the end of the time slot U4 includes the input ports # 1, # 2, # 3, #
4 for output ports # 3, # 1, # 2, # 4
And the time slots U5 and U5
In 6, each input port operates to transmit a packet corresponding to the output port that has acquired the connection right in the arbitration process C.

As described above, by forming a block from two packets and setting the time interval for executing the arbitration process to be twice the unit time V required to transfer the block, the arbitration process is completed. Can be allowed to be twice as long as the transfer time V of a single block, that is, four times as long as the transfer time T of a single packet, so that the arbiter unit can be configured even with a processor having a low processing capacity. Is possible.

The time interval for executing the arbitration process is not limited to twice the unit time V, but can be set to any length, and the same effect can be expected.

Similarly, similar effects can be achieved using a larger transfer solid composed of a plurality of blocks.

The present invention relates to an A for exchanging fixed length ATM cells.
The present invention is applicable not only to the TM exchange but also to a packet exchange for exchanging packets of variable length, and similar effects can be expected.

The present invention is not limited to the above-described embodiment, but includes various modifications in accordance with the principle of the present invention.

[0065]

As described above, according to the present invention,
The following effects are obtained.

The first effect of the present invention is that, in a packet switch which switches a packet between an input port and an output port, an arbitration process is performed for a long time equal to or longer than a unit time required to transfer a single packet. It only needs to be completed,
This means that the arbiter unit can be configured using a processor having a small processing capacity.

The reason is that, in the present invention, the arbitration process is executed at predetermined time intervals equal to or longer than the unit time required to transfer a single packet, and the output port acquired as a result of the arbitration process is processed. This is because the connection right is maintained until the result of the next arbitration process becomes valid.

A second effect of the present invention is that it is possible to lengthen the time required for completing the arbitration process.

The reason is that, in the present invention, the input buffer unit provided for each input port assembles a block composed of a plurality of packets destined for the same output port, and performs arbitration processing for each block. Is running. Since the time required to transfer a single block is longer than the unit time required to transfer a single packet, it is possible to increase the time required to complete the arbitration process.

A third effect of the present invention is that the arbitration process may be completed within a long time equal to or longer than the unit time required to transfer a single block, and the arbiter unit may be implemented using a processor having a small processing capacity. It can be configured.

The reason is that the arbitration process is executed at predetermined time intervals equal to or longer than the unit time required to transfer a single block, and the connection right of the output port acquired as a result of the arbitration process is: This is because it is held until the result of the next arbitration process becomes valid.

[Brief description of the drawings]

FIG. 1 is a diagram showing operation timings for executing an arbitration process according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an operation timing of execution of an arbitration process according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of a frame format of a block according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating another example of a frame format of a block according to an embodiment of the present invention.

FIG. 5 is a diagram showing operation timings of executing an arbitration process in a third embodiment of the present invention.

FIG. 6 is a block diagram showing the overall configuration of a conventional packet switch.

FIG. 7 is a diagram showing operation processing timing in a conventional packet switch.

[Explanation of symbols]

 10-1 to 10-n Input buffer unit 11-1 to 11-n Logical queue 12 Packet input unit 13 Packet output unit 14 Request unit 21 Arbiter unit 22 Switch exchange unit 23 Input highway 24 Output highway 30 Connection request signal 31 Contention arbitration Signal 100-1 to 100-n input port 101-1 to 101-n output port

[Procedure amendment]

[Submission date] June 5, 2000 (2006.5.5)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 1

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claim 2

[Correction method] Change

[Correction contents]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] Claim 3

[Correction method] Change

[Correction contents]

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] Claim 4

[Correction method] Change

[Correction contents]

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] Claim 6

[Correction method] Change

[Correction contents]

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] Claim 7

[Correction method] Change

[Correction contents]

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0022

[Correction method] Change

[Correction contents]

[0022]

According to the present invention, there is provided a method of controlling a packet switch for switching a packet between an input port and an output port.
The arbitration process is executed at a predetermined time equal to or longer than the unit time required for transferring the block, and the connection right of the output port obtained as a result of the arbitration process is valid for the result of the next arbitration process. And keep it until As a result, the arbitration process may be completed within a long time equal to or longer than the unit time required to transfer a single block , and the arbiter unit may be configured using a processor having a small processing capacity.

Claims (7)

[Claims] 1. A packet switching apparatus comprising: switch means for switching a packet input from an input port to an output port; and arbitration means for performing arbitration processing for deciding to which input port the connection right to the output port is given. In the above, the arbitration means performs arbitration processing every predetermined time, which is equal to or longer than a unit time required for transferring a single packet, and is given to the input port as a result of the arbitration processing. The packet switching device, wherein the connection right of the output port is retained until the result of the next arbitration process becomes valid. 2. An input buffer unit provided for each input port, assembles one block from a plurality of packets destined for the same output port, and the arbitration means executes the arbitration processing in block units. 2. The packet switching device according to claim 1, wherein 3. The packet switching device according to claim 2, wherein said block is composed of a plurality of packets destined for the same output port and belonging to the same service class. 4. The apparatus according to claim 1, wherein said block comprises a plurality of service classes and comprises a plurality of packets addressed to the same output port. Packet switching equipment. 5. A packet switching apparatus comprising: switch means for switching a packet input from an input port to an output port; and arbitration means for performing arbitration processing for deciding which input port is given a connection right to the output port. In the above, the arbitration means performs arbitration processing at predetermined time intervals, which is equal to or longer than a unit time required for transferring a single block, and is given to the input port as a result of the arbitration processing. The connection right of the output port is retained until the result of the next arbitration process becomes valid. 6. A method for controlling a packet switching device for switching a packet between an input port and an output port and performing an arbitration process for determining which input port is given a right to connect to an output port, wherein a single packet is transferred. Arbitration processing is performed at predetermined time intervals, which is equal to or longer than the unit time required to perform the arbitration processing. A method for controlling a packet switching apparatus, wherein the result is held until the result of the packet switching becomes valid. 7. A control method for a packet switching device for switching a packet between an input port and an output port and performing an arbitration process for determining which input port is given a right to connect to an output port, wherein a single block is transferred. Arbitration processing is performed at predetermined time intervals, which is equal to or longer than the unit time required to perform the arbitration processing. A method for controlling a packet switching apparatus, wherein the result is held until the result of the packet switching becomes valid.