JP2000242517A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] (with correction) [PROBLEMS] To provide a semiconductor memory device capable of suppressing an increase in circuit area and reducing test time. SOLUTION: When writing data to an E ² PROM 4, C
The PU 1 is connected to the bus 10 to supply a signal for writing a predetermined number of bytes, and the timing generation circuit 6 is brought into a non-operation state. E
^{2 When the} PROM 4 starts writing, the connection of the CPU 1 to the bus 10 is released, and the timing generation circuit 6 is connected. While the E ² PROM 4 is writing predetermined bytes,
The timing generation circuit 6 reads the ROM 2 or the RAM 3
A signal necessary for writing and reading of data is given to perform a test. The data read from the ROM 2 and the RAM 3 is stored in the data compressor 7. When the writing of the E ² PROM 4 is completed, the timing generation circuit 6 is deactivated, the CPU 1 is connected to the bus 10, and a signal necessary for writing the next predetermined byte is given.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a circuit necessary for a test.

[0002]

2. Description of the Related Art A central processing unit (hereinafter referred to as C) is mounted on one chip.
MCU (Micro Controller) including PU and memory
Unit) has a configuration as shown in FIG. The MCU 20 includes a CPU 2 on the same chip.
1. ROM (Read Only Memory) 22, RAM (Random)
Access Memory) 23, E ² PROM (Electrical Era)
A sable programmable read only memory (27) and a peripheral circuit 24 are arranged and connected to each other by a bus 25. The bus 25 is generally provided with only one system due to restrictions on the chip area. A large number of terminals 26 are provided on the periphery of the chip. The terminal 26 includes a power terminal VDD, a ground terminal GND, and a clock terminal CL.
K, reset terminal / RST, input / output terminal I / O,
A control terminal is included so that the ROM 22, RAM 23, and E ² PROM can be accessed from outside.

In such an MCU 20, data in the ROM 22 is read out via a control terminal, and furthermore, E ² PRO
A test can be performed by writing and reading data to and from the M27 and the RAM 23.

However, some MCUs, such as a card type MCU, cannot access a memory from the outside, for example. The MCU 30 shown in FIG. 4 has only a power supply terminal VDD, a ground terminal GND, a clock terminal CLK, a reset terminal / RST, and an input / output terminal I / O as terminals 37, and is used to access the ROM 32 and the RAM 33 from outside. No control terminal is provided.

In such a case, a ROM 32 or a RAM
33. It is not possible to access and test the E ² PROM 38 from outside. Therefore, as a first method, ROM
A test program is stored in a part of the ROM 32, and software processing is performed by using an external CPU.
It is conceivable to test the RAM 33 and the E ² PROM 38. According to this method, it is not necessary to add a new circuit, but there is a problem that the test time is long.

[0006] Alternatively, as a second method, as shown in FIG. 5, a CPU 31, a ROM 32, an R
In addition to the AM 33, the E ² PROM 38, and the peripheral circuit 34, there is also a countermeasure by adding hardware such as incorporating a timing generator 36 for generating a test address and data. According to this method, the test time is shorter than in the first method.

However, using the timing generator 36,
Even write to ² PROM38, time required for the writing is very long compared to the ROM32 and RAM33 access time. Therefore, even if the second method was used, the test time could not be sufficiently reduced.

[0008] As a third method, a process of writing data to the E ² PROM38, is also conceivable to carry out in parallel writing and reading of data to read or RAM33 data from ROM 32. But,
In this method, two systems are required for the bus 35, and the circuits added for the test are also used for the E ² PROM 38 and the ROM.
32 and the RAM 33 are required independently. Therefore, an increase in chip area and an increase in cost cannot be avoided.

[0009]

As described above, conventionally,
MCU closed in one chip without external control terminal
, There is a trade-off between the reduction of the test time and the increase of the circuit area, and there is a problem that the circuit area must be increased in order to reduce the test time.

In view of the above circumstances, it is an object of the present invention to provide a semiconductor memory device capable of suppressing an increase in circuit area and reducing a test time.

[0011]

According to the present invention, there is provided a semiconductor memory device which is connected to a bus of one system and outputs a write start signal when writing is started and outputs a write end signal when writing is completed. A read-only memory connected to the bus, a read-only memory connected to the bus, and a bus connected to the bus when given a connection request signal, and necessary for writing to the electrically-erasable and programmable read-only memory. An arithmetic processing unit that transfers the data and transfers the connection to the bus when a disconnection request signal is given; and the arithmetic processing unit when the electrically erasable and programmable read-only memory outputs the write start signal. And an enable signal is output to the electrical erasure and program When the read-only memory outputs the write end signal, the control circuit supplies the connection request signal to the arithmetic processing unit and outputs a disable signal, and the control circuit outputs an enable signal to enter an operation state. A timing generator that is connected to the bus, provides a signal necessary for reading to the read-only memory, and becomes inactive when the control circuit outputs the disable signal and is disconnected from the bus. It is characterized by:

A program necessary for a test may be stored in the read-only memory in advance, and the program may be read by the arithmetic processing unit.

[0013] The electronic erasure and programmable read only memory may further include a data compressor for receiving, compressing and storing data read from the read only memory.

[0014] Further, a write and read memory connected to the bus and receiving and writing signals required for writing and reading from the timing generator may be provided.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

The semiconductor memory device according to the present embodiment has a configuration as shown in FIG. This device is C
A PU 1, a ROM 2, a RAM 3, an E ² PROM 4 and a bus 10 are provided on the same chip, and a control circuit 5, a timing generator 6, a buffer 8 and a data compressor 7 are provided as test circuits.

The bus 10 is provided with only one system to prevent an increase in chip area, and one of the CPU 1 and the timing generator 6 is connected to the bus 10 and the other is disconnected according to a procedure described later.

[0018] CPU1 while it is connected to the bus 10, the test address required to E ² PROM 4, write data, write or read control signal, the timing signal or the like, gives the E ² PROM 4 via the bus 10.

The ROM 2 includes a test ROM 2a in which a test program is stored, and the test program is read by the CPU 1 during a test. Then, data stored in an area of the ROM 2 other than the test ROM 2a is read from the timing generator 6 in accordance with various control signals necessary for reading.

The RAM 3 is supplied with data necessary for the test from the timing generator 6, performs writing, and is read by the timing generator 6.

The E ² PROM 4 is supplied with data necessary for writing from the CPU 1 and writes data in predetermined blocks such as one byte.
1 is read.

The control circuit 5 performs various controls necessary for conducting a test. For example, one of the CPU 1 and the timing generator 6 is connected to the bus 10 and the other is disconnected. Control is performed to set an operation state or a non-operation state.

The buffer 8 operates under the control of the control circuit 5 and transfers the output from the timing generator 6 to the bus 10.

The data compressor 7 receives the data read from the ROM 2, RAM 3, and E ² PROM 4 and compresses and stores the data.

In the semiconductor memory device according to the present embodiment having such a configuration, the CPU 1 and the timing generator 6
By switching the connection to the bus 10, the ROM 2 and the RAM 3 are tested while the E ² PROM 4 having a long writing time is performing writing, and the test processing of a plurality of memories is performed in parallel. There is. The procedure of the processing will be described below.

(1) First, at the start of the test, the CPU 1
Is connected to the bus 10, the timing generator 6 is in a non-operating state, and is not connected to the bus 10. Test RO
The test program stored in M2a
Reads out and starts a test process. And E ² PR
Address required for writing in units of predetermined blocks such as 1-byte OM4, write data, timing signals, various control signals such as write signal, CPU 1 is E ²
Give to PROM4.

(2) The E2 PROM 4 outputs a Ready / Busy (hereinafter referred to as R / B) signal to the control circuit 5 at the same time as entering the write state, and starts the write processing for a predetermined block.

(3) Upon receiving the R / B signal, the control circuit 5 outputs a / Bus Request (hereinafter referred to as / BUSREQ) signal requesting the CPU 1 to release the bus 10.

(4) Upon receiving the / BUSREQ signal, the CPU 1 disconnects and opens the connection to the bus 10,
/ Bus Acknoledge (hereinafter / BUS)
ACK) is output to the control circuit 5.

(5) The control circuit 5 is supplied with the / BUSACK signal, outputs an enable signal EN to the timing generator 6 and the buffer 8, and puts both into an operating state. Thereby, the timing generator 6 is connected to the bus 10.

(6) From the timing generator 6 to the ROM 2
Various control signals such as timing signals necessary for reading the data are supplied to the ROM 2, and the stored data is read and transferred to the bus 10. The read data is supplied to the data compressor 7 and stored in a compressed state.

(7) Various control signals such as write data, a write control signal, and a timing signal required for testing the RAM 3 are generated by the timing generator 6 and supplied to the RAM 3. As a result, data is written to the RAM 3. After the writing is completed, various signals necessary for reading are read from the timing generator 6 to the RAM.
3, and the written data is read. This data is compressed by the data compressor 7 and stored. Here, while the writing of a predetermined block into the E2 PROM 4 is being performed, only one of the ROM 2 and the RAM 3 may be tested, or both may be tested sequentially.

(8) When the data writing for the predetermined block of the E ² PROM 4 is completed, the E ² PROM 4
The level of the B signal is returned to the original level, and the completion of the writing is notified to the control circuit 5.

(9) In response to the return of the R / B signal, the control circuit 5 supplies a disable signal to the timing generator 6 and the buffer 8 to deactivate the bus, and the bus 10
Disconnect from Thereby, the ROM 2 and / or the RAM
The test process of No. 3 is temporarily suspended.

(10) The control circuit 5 returns the / BUSREQ signal to the original level, and requests the CPU 1 to connect to the bus 10.

(11) The CPU 1 connects to the bus 10,
The / BUSACK signal is returned to the original level and this is transmitted to the control circuit 5. Then, various data necessary for writing the next predetermined block is transferred to the E ² PROM 4 at a time.

(12) The E2 PROM 4 restarts the write operation using the given data.

Hereinafter, the operations of (2) to (12) are described as E
² Repeat until writing to PROM 4 is completed. Here, reading of data from ROM 2 and / or RAM 3
The operation of writing data to and reading data from the memory are resumed from the point where the operation was interrupted.

(13) The CPU 1 reads out the data written in the E ² PROM 4, compares it with the expected value for every bit, determines whether or not the product is non-defective, and outputs the result. The reason why all bits are compared is that the time required for reading is extremely shorter than the writing time.

(14) R stored in the data compressor 7
The CPU 1 compares the data in the OM 2 and the RAM 3 with expected values to determine whether or not the data is non-defective, and outputs the result.

FIG. 2 shows R / B signals, / BUSREQ,
4 shows a time chart of the BUSACK and EN signals. E ²
When the PROM 4 starts the write operation, the R / B signal falls from the high level to the low level. The control circuit 5 requests the CPU 1 to release the bus 10 / BUSR
The EQ signal falls from the high level to the low level.
When the CPU 1 releases the connection to the bus 10, the / BUSACK signal indicating that the connection has been released falls from the high level to the low level at time t1. The control circuit 5 generates an enable signal E rising from a low level to a high level.
When N is given to the timing generator 6 and the buffer 8, the timing generator 6 is connected to the bus 10.

Next, the E ² PROM 4 ends the write operation, and the R / B signal returns from the low level to the high level.
The control circuit 5 receiving the return of the R / B signal supplies the enable signal EN, which falls from the high level to the low level, to the timing generator 6 and the buffer 8. As a result, the timing generator 6 is disconnected from the bus 10.
The level of the / BUSREQ signal requesting the control circuit 5 to connect the CPU 1 to the bus 10 returns from low to high. When the CPU 1 connects to the bus 10, the / BUSACK signal indicating the connection returns from the low level to the high level at time t2. At time t3, the same operation as at time t1 is started again.

Here, from time t1 to time t2,
The timing generator 6 is connected to the bus 10 and
2 While the writing of a predetermined block into the PROM 4 is being performed, another ROM 2 and / or RAM 3 is tested.

Between the time point t2 and the time point t3, the bus 1
0 CPU1 is connected to, E ² PROM from CPU1
Data necessary for writing is transferred to No. 4.

As described above, according to the present embodiment, E ²
The write operation to the PROM 4 and the read operation to the ROM 2 and / or the write and read operation to the RAM 3 can proceed in parallel. Therefore, it is possible to shorten the test time as compared with the related art. In addition, bus 10
The parallel processing can be performed with one system without adding additional test and additional circuits to two systems, so that an increase in circuit area can be prevented.

The above-described embodiment is an example, and does not limit the present invention. For example, in the above embodiment, the E ² PROM 4 and the ROM storing the test program are used.
2 and a RAM 3. However, the present invention can be applied to a device that does not include a RAM.

[0047]

As described above, according to the semiconductor memory device of the present invention, the electrical erasure using the arithmetic processing unit is switched by switching the connection between the arithmetic processing unit and the timing generation circuit for the primary system bus. In addition, by performing the write operation to the programmable read-only memory and the read operation to the read-only memory using the timing generation circuit in parallel, the test time can be reduced without increasing the circuit area.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a time chart showing waveforms of control signals in the semiconductor memory device.

FIG. 3 is a block diagram showing a schematic configuration of a conventional MCU.

FIG. 4 is a block diagram showing a schematic configuration of another conventional MCU.

FIG. 5 is a block diagram showing a schematic configuration of another conventional MCU.

[Explanation of symbols]

1 CPU 2 ROM 2a test ROM 3 RAM 4 E ² PROM 5 control circuit 6 timing generator 7 data compressor

Claims (3)

[Claims] An electrically erasable and programmable read-only memory connected to the bus and outputting a write start signal when writing is started and outputting a write end signal when writing is completed; and A read-only memory connected to the bus, receiving the connection request signal, connecting to the bus, transferring data necessary for writing to the electrically erasable and programmable read-only memory, and providing a disconnection request signal An operation processing unit that disconnects the connection to the bus when the electrical erasing and programmable read-only memory outputs the write start signal, and provides the operation processing unit with the disconnection request signal and an enable signal. Output and the electrically erasable and programmable read only memory completes the write. A control circuit that supplies the connection request signal to the arithmetic processing unit and outputs a disable signal when the signal is output; and a control circuit that is activated when the control circuit outputs the enable signal, is connected to the bus, and is connected to the bus. A timing generator which supplies a signal necessary for reading to a dedicated memory, and which is inactivated when the control circuit outputs the disable signal and is disconnected from the bus. apparatus. 2. The system of claim 1, further comprising: a read only memory that is electrically erasable and programmable; and a data compressor that receives, compresses, and stores data read from the read only memory. 13. The semiconductor memory device according to claim 1. 3. The memory according to claim 1, further comprising a write and read memory connected to said bus and receiving and writing signals required for writing and reading from said timing generator to perform writing and reading. Semiconductor storage device.