JP2000243727A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [PROBLEMS] To form a plurality of semiconductor elements on a semiconductor wafer and to cut out each semiconductor element by dicing, cooling water and shavings float from the semiconductor wafer on the front side of the semiconductor wafer. Between the bent portion and the surface of the semiconductor wafer. SOLUTION: The semiconductor element 20 has a vibrator 21 floating from the bottom surface of a concave portion 20a, and a bank 23 is formed along the outer periphery of the element 20 at the periphery of the upper surface. The bank 23 is set to be at least the height of the highest part on the semiconductor element 20. When the semiconductor element 20 is cut out, the adhesive tape is attached to the upper surface of the bank 23 to cover the semiconductor element 20, so that the semiconductor element 20 can be sealed with the adhesive tape. In addition, semiconductor wafers are embanked 2
Since the dicing is performed along 3, the adhesive tape remains in close contact with the upper surface of the bank 23 even after dicing, so that the semiconductor element 20 can be maintained in a sealed state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a plurality of semiconductor elements are formed on a semiconductor wafer and each semiconductor element is cut out by dicing.

[0002]

2. Description of the Related Art Conventionally, when a plurality of semiconductor elements formed on a semiconductor wafer as disclosed in JP-A-7-113707 are cut out from the semiconductor wafer, a semiconductor wafer having no semiconductor elements formed thereon is cut off. After fixing the covering member over the entire rear surface, the semiconductor wafer is cut from the front surface side of the semiconductor wafer with a diamond blade while cooling water is applied, and the semiconductor wafer is divided into semiconductor elements. Has been implemented.

[0003]

However, in the above-mentioned conventional method, when a semiconductor device having a portion floating from the semiconductor wafer is formed on the front surface side of the semiconductor wafer, the floating portion and the surface of the semiconductor wafer are not connected to each other. During this time, water for cooling and shavings entered and sometimes remained. In order to prevent the infiltration of cooling water and shavings, the covering member is fixed over the entire surface of the semiconductor wafer. A method for manufacturing a semiconductor element that is cut and divided into semiconductor elements is considered. At this time, the covering member is easily fixed only to a high portion (for example, an electrode) of the semiconductor element which is scattered on the semiconductor element and cannot cover the surface of the semiconductor element in a liquid-tight manner. At the time, through a gap between the semiconductor element and the covering member where the covering member is not firmly fixed, water for cooling or shavings enters between the floating portion and the surface of the semiconductor wafer, There is a problem that the semiconductor element itself is destroyed by the intrusion of the cooling water. In addition, a portion other than the portion where the covering member is fixed, that is, a portion having a gap between the semiconductor element and the covering member is cut, and this gap appears outside, so that cooling water and shavings pass through the gap. There is a problem that the semiconductor element itself is destroyed due to intrusion between the floating portion and the surface of the semiconductor wafer and intrusion of the cooling water.

[0004]

SUMMARY OF THE INVENTION The present invention has been made to address the above problems, and an object of the present invention is to provide cooling water and shavings floating on the surface of a semiconductor wafer during dicing. It is an object of the present invention to provide a method of manufacturing a semiconductor device in which the semiconductor element does not enter between the portion and the surface of the semiconductor wafer.

The present invention relates to a method of manufacturing a semiconductor device in which a plurality of semiconductor elements are formed on a semiconductor wafer and each semiconductor element is cut out by dicing. A bank surrounding each element is formed, and a covering member is provided on the upper surface of the bank in a liquid-tight manner to cover each semiconductor element. That is, each semiconductor element is cut out by dicing the wafer. Preferably, the covering member may have adhesiveness.

According to such a manufacturing method, since the covering member is provided in a liquid-tight manner on the upper surface of the bank surrounding each semiconductor element to cover the semiconductor element, the semiconductor element can be hermetically sealed by the covering member. . Also, since the semiconductor wafer is diced along the bank, even after dicing, since the covering member is in close contact with the upper surface of the bank, a portion floating from the semiconductor wafer on the front side of the semiconductor wafer. Even if there is, it is possible to prevent cooling water and shavings from entering between the floating portion and the surface of the semiconductor wafer and to prevent the semiconductor element itself from being destroyed by the cooling water. it can. In particular, by using the covering member having adhesiveness, the covering member can be adhered to the upper surface of the bank, so that the semiconductor element can be prevented from coming off the covering member during dicing.

Another feature of the present invention is that an alignment mark for specifying a dicing position is provided on the back surface of the semiconductor wafer by making the roughness different from that of another adjacent portion. According to this, for example, since the alignment mark is optically different in roughness from other portions, the dicing apparatus can easily recognize the alignment mark, and can cut out the semiconductor element with high precision along the bank.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to a semiconductor device having a vibrator capable of vibrating on the upper surface of a semiconductor wafer. FIG. 1A is a schematic top view of a semiconductor wafer on which the semiconductor element according to the embodiment is formed, and FIG. 1B is a schematic bottom view of the semiconductor wafer.

The semiconductor wafer 10 has a multi-layer structure composed of a silicon layer and a silicon oxide film layer and is formed in a disk shape. Have been. As shown in FIGS. 2A and 2B, the semiconductor element 20 is formed in a square shape, and has a recess 20a at the center of the upper surface. A vibrator 21 is provided in the concave portion 20a so as to float from the bottom surface by a small predetermined distance d. The vibrator 21 is formed in a square shape, and the left end thereof is
Oa is connected to the inner peripheral surface so as to be able to vibrate. Semiconductor element 2
On the upper surface, an electrode 22 formed of a conductive metal (for example, aluminum) in a square shape is provided.
Is electrically connected to the vibrator 21 via a connecting portion (not shown). A bank 23 having a predetermined width and a predetermined height is formed along the outer periphery of the semiconductor element 20 at the periphery of the upper surface of the semiconductor element 20. The bank 23 is formed of a conductive metal (for example, aluminum) similarly to the electrode 22, and the height thereof is set to be equal to or higher than the height of the electrode 22. The predetermined width of the bank 23 is determined in consideration of the adhesive strength of the adhesive tape described later, the size of the semiconductor element, and the pressure of the cooling water used when cutting the semiconductor wafer.

As shown in FIGS. 1B and 3A, a cross-shaped alignment mark 11 is integrally formed on the lower surface of the semiconductor wafer 10 at a position corresponding to each corner of the semiconductor element 20. In addition to being provided so as to protrude, a cross-shaped portion is also provided at a predetermined location (for example, at a predetermined distance inside the semiconductor element 20 from a midpoint of a predetermined side) within a range corresponding to the semiconductor element 20. The alignment marks 12 are provided so as to protrude integrally. The alignment mark 11 is formed relatively large in order to roughly recognize the position of the semiconductor element 20, and its width is set to a large value (for example, 140 μm). The alignment mark 12 is formed to be relatively small in order to precisely specify the position of the semiconductor element 20 and to specify the dicing position, and has a small width (for example, 20).
μm). These alignment marks 11 and 12 are set at the same height, and as shown in FIG. 3B, the upper surface thereof is formed in a rough surface shape, for example, in a wavy cross section. The lower surface of the semiconductor wafer 10 is mirror-finished.

Next, the semiconductor elements 20 are placed on the semiconductor wafer 10.
A method for forming the alignment marks 11 and 12 will be described with reference to FIG.

(1) First Step As a substrate material, a monocrystalline silicon layer having a thickness of about 10 μm is formed on an upper surface of a lower layer a composed of single crystal silicon via an intermediate layer b formed of a silicon oxide film having a thickness of about 1 μm. An SOI (Silicon-On-Insulator) substrate provided with an upper layer c is prepared. Note that both sides of this substrate are mirror-finished.
Then, an aluminum film is formed on the upper surface of the upper layer c at a position corresponding to the electrode 22 and the bank 23 by a sputtering method or the like, thereby forming the electrode 22 and the bank 23, respectively.

(2) Second Step A resist film 30 having a predetermined thickness d 1 (for example, 2 μm) is formed on the lower surface of the lower layer a, that is, on the back surface of the semiconductor wafer 10 and at a portion corresponding to the alignment marks 11 and 12. . At this time, the resist film 30 has a selectivity of 1 with respect to the silicon of the lower layer a, that is, has the same etching rate as that of silicon, and its upper surface is formed in a wavy shape (see FIG. 4A). Then, the back surface of the semiconductor wafer 10 not covered with the resist film 30 and the resist film 30 are removed.
Dry etching is performed by RIE (reactive ion etching) or the like until the resist film 30 is completely removed. As a result, alignment marks 11 and 12 having a height d1 are formed on the back surface of the semiconductor wafer 10, the upper surfaces of the alignment marks 11 and 12 are formed in a wavy shape, and the alignment marks 11 and 12 are formed on the back surface of the semiconductor wafer 10.
Portions other than 12 are maintained in a mirror state (see FIG. 4B).

(3) Third Step After a portion corresponding to the upper surface of the upper layer c outside the recess 20a and a portion corresponding to the vibrator 21 is masked with a resist film, the upper layer c is subjected to RIE (reactive ion etching). ) To form a portion corresponding to the outside of the concave portion 20a on the intermediate layer b and leave a portion corresponding to the vibrator 21.

(4) Fourth Step Intermediate layer b sandwiched between oscillator 21 (upper layer c) and lower layer a
Is removed by wet etching with a hydrofluoric acid aqueous solution or the like, and the vibrator 21 is formed so as to float from the bottom surface of the concave portion 20a.

Next, the semiconductor device 20 is formed from the semiconductor wafer 10 on which the semiconductor device 20 is formed by the above-described manufacturing method.
A method for cutting out is described with reference to FIG.

(1) First Step The semiconductor wafer 10 is brought into close contact with the surface of the semiconductor wafer 10 on the adhesive tape 40 placed with the adhesive side up, so that the adhesive tape covers the entire surface of the semiconductor wafer 10. 4
0 (FIG. 5A). At this time, the adhesive tape 4
0 is to be attached to the upper surface of the bank 23 which is the highest part on the semiconductor wafer 10. That is, since the adhesive tape is attached to the upper surface of the bank 23 surrounding each semiconductor element 20 to cover the semiconductor element 20, the semiconductor element 20 can be sealed with the adhesive tape 40.

(2) Second Step First, the alignment mark 1 on the back surface of the semiconductor wafer 10
The dicing position is specified by recognizing 1, 12. At this time, since the upper surfaces of the alignment marks 11 and 12 are formed in a rough surface shape, and the portions other than the alignment marks 11 and 12 are formed in a mirror-like shape, the alignment marks 11 and 12 can be easily recognized. Therefore, the dicing position can be easily specified. Next, the semiconductor wafer 10 is cut by the diamond blade 50 from the back side of the semiconductor wafer along the specified dicing position, that is, along the bank 23 of the semiconductor element 20 while applying cooling water (FIG. 5B). , The semiconductor wafer 10 is divided into each semiconductor element 20, and each semiconductor element 20 is
And remains on the tape 40 while being adhered to the tape. That is, since the adhesive tape 40 is in close contact with the upper surface of the bank 23, it prevents cooling water and shavings from entering between the vibrator 23 and the concave portion 20 a of the semiconductor element 20, and also cools the cooling water. Accordingly, the semiconductor element itself can be prevented from being destroyed.

(3) Third Step Each of the divided semiconductor elements 20 is detached from the adhesive tape 40 (FIG. 5C), and is carried out by a carrier.

According to the above-described manufacturing method, the adhesive tape 40 is attached to the upper surface of the bank 23 surrounding each semiconductor element 20 so as to cover the semiconductor element 20. Can be sealed. In addition, since the semiconductor wafer 10 is diced along the bank 23, the adhesive tape 40 is in close contact with the upper surface of the bank 23 even after dicing, so that the semiconductor wafer 10 1
Even if there is a portion floating from zero, it is possible to prevent cooling water or shavings from entering between the floating portion and the surface of the semiconductor wafer 10.

In the above embodiment, the bank 23
Is formed of the same material as the electrode 22, the bank 23 can be formed simultaneously with the electrode 22 in the first step, thereby simplifying the manufacturing process. However, the bank 23 is formed of a non-conductive material (for example, silicon nitride). (SiN), silicon oxide (SiO
₂ ), silicon oxynitride (SiON)). In this case, the bank 23 is formed before and after the first step.

Further, in the above-described embodiment and the modified example, the adhesive tape 40 is attached to the upper surface of the bank 23 to cover the semiconductor element 20 in a liquid-tight manner, but a wax layer is formed on the upper surface of the bank 23. Alternatively, the semiconductor element 20 may be covered in a liquid-tight manner. This wax layer is a resin-based material and has tackiness when heated. In this case, in the first step of cutting the semiconductor element 20 from the semiconductor wafer 10 described above, a wax is applied by a predetermined thickness over the entire upper surface of the metal plate larger than the semiconductor wafer to form a wax layer. After heating, the semiconductor wafer 10 is adhered to the wax layer with its surface down, and then cooled, whereby the wax layer is fixed over the entire surface of the semiconductor wafer 10. At this time, the wax layer is fixed to the upper surface of the bank 23 which is the highest portion on the semiconductor wafer 10. That is, since the wax layer is fixed to the upper surface of the bank 23 surrounding each semiconductor element 20 to cover the semiconductor element 20, the semiconductor element 20 can be sealed with the wax layer.
In the second step, each divided semiconductor element 2
0 remains on the wax layer while being fixed to the wax layer. That is, since the wax layer is in close contact with the upper surface of the bank 23, the vibrator 23 and the concave portion 20 of the semiconductor element 20 are formed.
The cooling water and the shavings can be prevented from entering the space between the semiconductor element and a, and the semiconductor element itself can be prevented from being destroyed by the cooling water. Further, in the third step, each of the divided semiconductor elements 20 is removed from the wax layer, and is carried out by a carrier. Also according to this, the same operation and effect as the above embodiment can be expected.

Although the alignment marks 11 and 12 are formed by the convex portions in the above embodiment and the modified example, they may be formed by the concave portions. In this case, the alignment marks are set to the same size and width as the alignment marks 11 and 12 described above. In the method of manufacturing the alignment mark, a portion other than the portion corresponding to the alignment mark is masked, and a resist film having a cross-sectional wavy shape thinner than the mask portion is formed at the portion corresponding to the alignment mark, and then dry-etched to form a cross-section. An alignment mark having a wavy bottom surface is formed. Also in this case, since the alignment mark can be easily recognized, the dicing position can be easily specified.

In the above-described embodiment and the modification, the alignment marks 11 are provided at positions corresponding to the respective corners of the semiconductor element 20 in order to roughly recognize the position of each semiconductor element 20. It may be provided at a position corresponding to the midpoint of each side of the semiconductor element 20, within a range corresponding to the semiconductor element 20, at a predetermined position (for example, a center position of the semiconductor element 20).

In the above-described embodiment and the modified example, in the second step of cutting the semiconductor element 20 from the semiconductor wafer 10, the selectivity with respect to the silicon of the lower layer a is 1 in order to form the resist film 30. Although resist material was used,
The resist film may be formed using a resist material having a selectivity other than 1, for example, a resist material having a higher etching rate than the silicon. In this case, since the amount of etching of the resist film is larger than that of the portion (silicon) where the resist film is not formed, when the resist film is completely removed, the etching amount of the portion where no resist film is formed Is smaller than the thickness of the resist film formed on the lower layer, so that an alignment mark having a height smaller than the thickness of the resist film is formed at the position where the resist film was.

[Brief description of the drawings]

FIG. 1A is a schematic top view of a semiconductor wafer on which a semiconductor element according to one embodiment of the present invention is formed, and FIG. 1B is a schematic bottom view of the semiconductor wafer.

FIG. 2A is a schematic top view of the semiconductor device of FIG. 1A, and FIG. 2B is a cross-sectional view of the same device taken along line B2-B2.

FIG. 3 (A) is a cross-sectional view of the semiconductor wafer shown in FIG. 1 (B).
FIG. 3B is a partial cross-sectional view along the line -3, and FIG.
3 is a partially enlarged view of the semiconductor wafer shown in FIG.

FIGS. 4A and 4B are cross-sectional views showing a process of manufacturing the alignment mark of FIG.

5 (A) to 5 (C) are cross-sectional views showing steps of cutting out the semiconductor device of FIG. 2;

[Explanation of symbols]

Reference Signs List 10: semiconductor wafer, 11, 12: alignment mark, 20: semiconductor element, 20a: concave portion, 21: vibrator,
Reference numeral 22: electrode, 23: embankment, 30: resist film, 40: adhesive tape, 50: diamond blade, a: lower layer, b: intermediate layer, c: upper layer.

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a plurality of semiconductor elements are formed on a semiconductor wafer, and each semiconductor element is cut out by dicing, wherein each of the semiconductor elements is formed in a process of forming the semiconductor element on the semiconductor wafer. A bank surrounding each semiconductor element is formed, and a covering member is provided on an upper surface of the bank in a liquid-tight manner to cover each semiconductor element. Then, the position of the formed bank from the opposite side of the surface on the side of each semiconductor element. Wherein each semiconductor element is cut out by dicing the semiconductor wafer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the covering member has an adhesive property. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the dicing position is specified by differentiating the roughness of the back surface of the semiconductor wafer from other adjacent portions. A method for manufacturing a semiconductor device, wherein an alignment mark is provided.