JP2000250072A - Liquid crystal image display device and method of manufacturing semiconductor device for image display device - Google Patents

Abstract

(57) [Problem] To prevent image burning and afterimage from occurring in an IPS type liquid crystal panel capable of displaying a wide viewing angle. SOLUTION: As shown in FIG. 1D, a passivation insulating layer 37, an AL layer 35, a refractory metal layer 34, a second amorphous silicon layer 33 and a first amorphous silicon layer 3 are provided.
1 is selectively removed to expose the gate insulating layer 30, the source / drain electrodes 12 and 21 are formed including the formed silicon oxide layer 63, and the drain electrode 21 and the source electrode 12 also serving as a signal line are formed. An insulating layer (silicon oxide layer 63, alumina layer 65) is formed on any of the electrodes.

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal image display device and a semiconductor device for an image display device, and more particularly to a liquid crystal panel having a color image display function, in particular, capable of displaying a wide viewing angle. It relates to a liquid crystal panel.

[0002]

2. Description of the Related Art Recent advances in microfabrication technology, liquid crystal material technology and high-density packaging technology have led to the practical use of television images or various types of image display devices using 5 to 50 cm diagonal liquid crystal panels. It is provided on a commercial basis.

Further, a color display is realized by forming an RGB colored layer on one of two glass substrates constituting a liquid crystal panel. In particular, in a so-called active type liquid crystal panel in which a switching element is incorporated for each picture element, an image having little crosstalk, high speed response, and high contrast ratio is guaranteed.

[0004] These liquid crystal panels have 20 scanning lines.
Generally, a matrix organization of about 0 to 1000 lines and about 200 to 2000 lines for signal lines is used, but recently, a large screen and a high definition have been simultaneously developed to cope with an increase in display capacity.

FIG. 7 is a perspective view showing a mounting state of the liquid crystal panel. A driving signal is applied to the electrode terminal group 6 of the scanning line formed on one of the transparent insulating substrates constituting the liquid crystal panel 1, for example, the glass substrate 2. Integrated circuit chip 3 that supplies
Is connected directly to a COG (Chip-On-Glass) method or, for example, a TCP film 4 based on a polyimide resin thin film and having gold-plated copper foil terminals (not shown) is connected to a signal line electrode terminal group 5. (Tape-Carrier-P) which is fixed by pressing with a suitable adhesive containing a conductive medium
An electric signal is supplied to the image display unit by mounting means such as an ackage method. Here, for the sake of convenience, the two mounting methods are illustrated simultaneously, but in practice, any one of the methods is appropriately selected.

[0006] 7 and 8 are signal lines and scanning lines,
The wiring path connects between the image display unit located at the center of the liquid crystal panel 1 and the electrode terminal groups 5 and 6. Absent. Reference numeral 9 denotes a glass substrate which is another transparent insulating substrate having a transparent conductive counter electrode common to all liquid crystal cells.

FIG. 8 is an equivalent circuit diagram of an active type liquid crystal panel in which insulated gate transistors 10 are arranged as switching elements for each picture element. (Signal lines 7 shown in FIG. 7) and 13 are liquid crystal cells, and the liquid crystal cell 13 is electrically treated as a capacitive element. The elements drawn by solid lines are formed on one glass substrate 2 constituting the liquid crystal panel, and the counter electrode 14 common to all the liquid crystal cells 13 drawn by broken lines is formed on the other glass substrate 9. I have.

When the OFF resistance of the insulated gate transistor 10 or the resistance of the liquid crystal cell 13 is low, or when importance is placed on the gradation of a displayed image, an auxiliary for increasing the time constant of the liquid crystal cell 13 as a load. Storage capacity of 15
Are added to the liquid crystal cell 13 in parallel. Reference numeral 16 is a common bus of the storage capacitance lines.

FIG. 9 is a sectional view of a main part of an image display section of the liquid crystal panel. Two glass substrates 2 and 9 constituting the liquid crystal panel 1 are made of a spacer material such as resin fiber or beads (not shown). Is formed at a predetermined distance of about several μm, and the gap (gap) is
The periphery of 9 is a closed space sealed with a sealing material made of an organic resin and a sealing material (both not shown), and the closed space is filled with liquid crystal 17.

In order to realize color display, an organic thin film (referred to as a colored layer) 18 having a thickness of about 1 to 2 μm containing at least one of a dye and a pigment is provided on the closed space side of the glass substrate 9. When attached, a color display (RGB) function is provided. In this case, the other glass substrate 9 is also called a color filter. Depending on the properties of the liquid crystal material, the polarizing plate 19 is provided on at least one of the upper surface of the other glass substrate 9 and the lower surface of the glass substrate 2.
Is adhered, and the liquid crystal panel 1 functions as an electro-optical element.

At present, most liquid crystal panels use a TN (twisted nematic) type liquid crystal material, and usually require two polarizing plates 19. Note that description of a back light source as a light source is omitted.

The two glass substrates 2 and 9 are in contact with the liquid crystal 17.
The polyimide resin thin film 20 having a thickness of, for example, about 0.1 μm formed thereon is an alignment film for aligning liquid crystal molecules in a predetermined direction. Reference numeral 21 denotes a drain electrode (wiring) connecting the drain of the insulated gate transistor 10 and the transparent conductive picture element electrode 22, and a signal line (source line).
It is often formed simultaneously with 12. Drain electrode 21
The semiconductor layer 23 is provided between the semiconductor layer 23 and the signal line 12.
The details will be described later. The Cr thin film layer 24 having a thickness of about 0.1 μm formed at the boundary between the adjacent colored layers 18 on the color filter (the other glass substrate) 9
And light shielding for preventing external light from entering the scanning lines 11 and the signal lines 12, which are fixed as a so-called black matrix (BM).

Here, the structure and manufacturing method of an insulated gate transistor as a switching element will be described. Two types of insulated gate transistors are currently in heavy use, and one of them will be described as a conventional example (referred to as an etch stop type).

FIG. 10 is a plan view of a unit picture element of an active substrate constituting a conventional liquid crystal panel, and FIG. 11 is a sectional view taken along line AA in FIG.
The manufacturing process will be described with reference to FIG. In this example, the projection 50 formed on the scanning line 11 and the pixel electrode 22
Are overlapped with a gate insulating layer to form the storage capacitor 15, but the details thereof are omitted here.

First, as shown in FIG. 11A, a glass substrate 2 having a thickness of about 0.5 to 1.1 mm (for example, a trade name of 173 manufactured by Corning Incorporated) is used as an insulating substrate having high heat resistance and high transparency.
7) On one main surface, as a first metal layer having a thickness of about 0.1 to 0.3 μm using a vacuum film forming apparatus in which a film forming process such as SPT (sputtering) is performed, for example, Cr, Ta, Mo, etc. Alternatively, a gate electrode 11 serving also as a scanning line is selectively formed by a fine processing technique by depositing an alloy thereof.

In order to reduce the resistance of the scanning line corresponding to the enlargement of the screen, Al (aluminum) is used as the material of the scanning line. However, since Al has low heat resistance, the heat-resistant metals Cr, Ta, Mo are used. Or, it is also a general technique to laminate with those silicides or to add an oxide layer (Al ₂ O ₃ ) to the surface of Al by anodic oxidation.

Next, as shown in FIG. 11B, a first SiNx (silicon nitride) layer 30 serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 by using a PCVD (plasma seed) device, Of the first amorphous silicon (a-Si) layer 31 and the second SiNx layer 32
The different types of thin film layers are sequentially deposited in a thickness of, for example, about 0.3-0.05-0.05 μm.

As a know-how technique, when forming a gate insulating layer, another type of insulating layer (for example, TaOx or SiO ₂ ) is laminated, or a SiNx layer is formed in two steps. In many cases, yield improvement measures such as providing a cleaning step in the middle are performed, and the gate insulating layer is not limited to one type or a single layer.

The gate electrode 1 is formed by a fine processing technique.
The first amorphous silicon layer 31 is exposed by selectively leaving the second SiNx layer 32 on the first electrode thinner than the gate electrode 11 and the entire surface is also formed as an impurity using a PCVD apparatus.
For example, the second amorphous silicon layer 33 containing phosphorus
It is deposited with a thickness of about 05 μm.

Next, as shown in FIG. 11C, the first amorphous silicon layer 31 and the second amorphous silicon layer 33 are left only in the vicinity of the gate electrode 11 in an island shape. After the gate insulating layer 30 is exposed, as shown in FIG. 11D, a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm is formed using a vacuum film forming apparatus such as SPT, for example, ITO (Indium-Tin- Oxid
e), and the pixel electrodes 22 are selectively formed by a fine processing technique.

Next, although not shown, the scanning lines 1 in the peripheral portion of the image display unit necessary for electrical connection to the scanning lines 11 are provided.
After a selective opening is formed in the gate insulating layer 30 on the substrate 1, as shown in FIG. 11E, a heat-resistant metal layer having a thickness of about 0.1 μm is formed using a vacuum film forming apparatus such as SPT. For example, a thin film 34 of Ti, Cr, Mo or the like, and an Al thin film 35 having a thickness of about 0.3 μm as a low-resistance wiring layer are sequentially deposited, and the heat-resistant metal layer 34 and the low-resistance wiring layer 35 are laminated by a fine processing technique. The drain electrode 21 of the insulated gate transistor and the source electrode 12 also serving as a signal line are selectively formed. Using the photosensitive resin pattern used at this time as a mask, the second amorphous silicon layer 33 on the second SiNx layer 32 between the source and drain electrodes is removed to expose the second SiNx layer 32. At the same time, in other regions, the first amorphous silicon layer 31 is also removed to expose the gate insulating layer 30 and the pixel electrodes 22.

The source / drain electrodes 12 and 21 are formed so as to partially overlap the gate electrode 11 so that the insulated gate transistor does not have an offset structure. It should be noted that the signal electrode (source electrode) 12 including the opening on the scanning line (gate electrode) 11 and the terminal electrode group 6 on the scanning line side, or the scanning line 11 and the scanning line side Forming a wiring path 8 for connecting to the terminal electrode group 6 is also generally performed.

Finally, a SiNx layer having a thickness of about 0.3 μm is applied as a transparent insulating layer on the entire surface of the glass substrate 2 using a PCVD apparatus in the same manner as the gate insulating layer to form a passivation insulating layer 37. As shown in FIG. 11F, an opening 38 is formed on the picture element electrode 22 to expose most of the picture element electrode 22 and, at the same time, although not shown, is formed on the terminal electrode groups 5 and 6 in the peripheral part. An opening is also formed to expose most of the terminal electrode groups 5 and 6 to complete the active substrate 2.

When the wiring resistance of the signal line 12 does not matter, the low-resistance wiring layer 35 made of Al is unnecessary.
In that case, if a heat-resistant metal material such as Cr, Ta, or Mo is selected, the source / drain electrodes 12 and 21 can be made into a single layer. The details of the heat resistance of the insulated gate transistor are described in JP-A-7-74368.

The passivation insulating layer 3 on the picture element electrode 22
The reason for removing 7 is that one is to prevent the reduction of the effective voltage applied to the liquid crystal cell and the other is that the film quality of the passivation insulating layer 37 is generally inferior and charges are accumulated in the film. This is to prevent the display image from being burned. This is because the film formation temperature of the passivation insulating layer 37 is lower by several tens degrees Celsius or more than that of the gate insulating layer 30 because of the heat resistance of the insulated gate transistor.
This is because it is inevitable to form a film at a low temperature of not more than ℃.

Here, a liquid crystal panel of the IPS (In-Plain-Switching) type, which can be displayed at a wide viewing angle and has been commercialized recently, will be described. FIG. 12 is a cross-sectional view of a main part of an image display unit in an IPS type liquid crystal panel.
Is different from the conventional one shown in FIG. 1 in that the liquid crystal cell is formed at a predetermined distance from the conductive counter electrode 40 and the pixel electrode 4.
1 (the drain electrode 21 in FIG. 9) and the liquid crystal 17, and the liquid crystal 17 is switched by a horizontal electric field acting between the counter electrode 40 and the pixel electrode 41.

Therefore, in the configuration shown in FIG.
The transparent conductive counter electrode 14 is not required on the color filter (one glass substrate) 9, and the transparent conductive pixel electrode 22 is not required on the active substrate (the other glass substrate) 2. . That is, the number of steps for manufacturing the active substrate 2 can be reduced.

FIG. 13 is a plan view of a unit picture element of an active substrate constituting an IPS type liquid crystal panel, and FIG.
14 is a cross-sectional view taken along the line AA in FIG.
The manufacturing process will be described with reference to (a) to (e). TFT
In the following, a description will be given of a case where another conventional one (referred to as a channel etch type) is adopted.

First, as in the conventional example, FIG.
As shown in FIG. 1, Cr, Ta, Mo, or the like is deposited as a first metal layer having a thickness of about 0.1 to 0.3 μm on one main surface of the glass substrate 2 using a vacuum film forming apparatus such as SPT. And
The gate electrode 11 also serving as a scanning line and the counter electrode 40 are selectively formed by fine processing technology.

Next, as shown in FIG. 14 (b), an SiNx (silicon nitride) layer 30 serving as a gate insulating layer and almost all impurities are contained on the entire surface of the glass substrate 2 by using a PCVD (plasma seed) apparatus. First, three types of thin film layers, that is, a first amorphous silicon (a-Si) layer 31 serving as a channel of an insulated gate transistor and a second amorphous silicon layer 32 containing impurities are formed by, for example, 0.3-0.2 −0.
Deposit sequentially with a thickness of about 05 μm.

Next, as shown in FIG. 14C, a semiconductor layer composed of a first amorphous silicon layer and a second amorphous silicon layer is left on the gate electrode 11 in the form of islands 31 and 33. To expose the gate insulating layer 30.

Next, although not shown, after selectively forming openings in the gate insulating layer 30 on the scanning lines 11 around the image display section necessary for electrical connection to the scanning lines 11, ,
As shown in FIG. 14D, using a vacuum film forming apparatus such as SPT, for example, a Ti thin film 34 as a heat-resistant metal layer having a thickness of about 0.1 μm and an A-layer having a thickness of about 0.3 μm as a low-resistance wiring layer.
The L thin film 35 is sequentially deposited, and the drain electrode 21 of the insulated gate transistor also serving as the picture element electrode 41 and the source electrode 12 also serving as the signal line are selectively formed by a fine processing technique. In this selective pattern formation, the AL thin film 35, the Ti thin film 34, and the second amorphous silicon layer 33 are sequentially etched using the photosensitive resin pattern 50 used for forming the source / drain electrodes 12, 21 as a mask. . Since the first amorphous silicon layer 31 is formed leaving about 0.05 to 0.1 μm, it is called a channel etch.

Finally, after the photosensitive resin pattern 50 is removed, as shown in FIG. 14 (e), a transparent insulating layer is formed on the entire surface of the glass substrate 2 in the same manner as the gate insulating layer by PCV.
Using a D apparatus, a passivation insulating layer 37 is formed by depositing a SiNx layer having a thickness of about 0.3 μm, and openings (not shown) are formed on the peripheral terminal electrode groups 5 and 6 to form , 6 are exposed to complete an active substrate.

As is clear from the above description, the counter electrode 40 is formed at the same time as the scanning line 11 and the pixel electrode 41 is formed at the same time as the source / drain electrodes 12 and 21. It is unnecessary and the number of manufacturing steps is reduced as compared with the conventional one.

The channel-etch type TFT has a larger thickness of the first amorphous silicon layer containing no impurity than the etch-stop type from the viewpoint of uniformity of a film forming process and an etching process. There is a problem to be solved regarding the operation of the PCVD apparatus and the generation of particles.

[0036]

There is a trend that active screen type liquid crystal panels have a larger screen and higher definition, and an increase in the viewing angle is also an important technical solution.

The IPS type liquid crystal panel has a good viewing angle symmetry because the movement of liquid crystal molecules is rotation in the same plane, and the viewing angle can be enlarged. Since the electrode 41 and the counter electrode 40 themselves do not contribute to display, there is a problem that the aperture ratio decreases and the transmittance of the liquid crystal panel decreases.

The decrease in transmittance can maintain brightness by increasing the illuminance of the backside light source. Therefore, in a use as a monitor that uses an AC power supply as a power supply, it cannot be said that it is a practical problem. In the manufacturing process, it has been found that since the passivation insulating layer 37 is included as a constituent factor of the liquid crystal cell, afterimages due to charge accumulation or printing of a display image cannot be avoided. Although measures have been taken to increase the resistance component of the alignment film 20 or the liquid crystal 17 to alleviate burning, if the resistance value is excessively reduced, the retention of the liquid crystal cell is reduced and flicker is likely to occur. It is also necessary to consider the occurrence of the side effect of the IPS type liquid crystal panel.

The present invention has been made in view of the above-mentioned situation, and in an IPS type liquid crystal panel capable of displaying a wide viewing angle, an image is prevented from being printed or an afterimage is generated. It is an object of the present invention to provide a liquid crystal image display device and a method of manufacturing a semiconductor device for an image display device, which can simultaneously solve the above problems.

[0040]

According to one aspect of the present invention, there is provided a liquid crystal image display device, comprising: an insulated gate transistor on one main surface; and a picture connected to a drain of the insulated gate transistor. A first transparent insulating substrate in which unit pixel elements each having at least one element electrode and a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix; A liquid crystal image display device having a liquid crystal filled between a first transparent insulating substrate and a second transparent insulating substrate or a color filter, wherein a gate of the insulated gate transistor and the counter electrode are connected to each other. Forming a silicon oxide layer containing impurities on a channel of an insulated gate transistor formed on the first transparent insulating substrate via a gate insulating layer, formed on the first transparent insulating substrate; A source / drain wiring formed on an amorphous silicon layer which does not contain impurities serving as a channel through an amorphous silicon layer containing impurities and which is in contact with the silicon oxide layer of Or one or more metal layers including the silicide layer thereof, and an insulating layer formed on the source / drain wirings. With this configuration, a lateral direction acting between a picture element electrode and a counter electrode is formed. Since the passivation insulating layer can be excluded from the electric field of the device and the passivation insulating layer is formed on the source / drain electrodes, the burn-in of the display image is suppressed and the reliability of the liquid crystal panel is secured. .

According to a second aspect of the present invention, there is provided a liquid crystal image display device, comprising: an insulated gate transistor on one main surface; a pixel electrode connected to a drain of the insulated gate transistor; A first transparent insulating substrate in which at least one unit pixel having at least one counter electrode formed therebetween is arranged in a two-dimensional matrix, and the first transparent insulating substrate and the second transparent insulating substrate In a liquid crystal image display device in which liquid crystal is filled between a transparent insulating substrate or a color filter, a gate of the insulated gate transistor and the counter electrode are formed on the first transparent insulating substrate, Forming a silicon oxide layer containing an impurity on a channel of an insulated gate transistor formed on the first transparent insulating substrate via a gate insulating layer, in contact with the silicon oxide layer and containing the impurity; The source / drain wiring formed on the amorphous silicon layer which does not contain impurities serving as a channel via the amorphous silicon layer is formed of at least a heat-resistant metal layer capable of anodic oxidation or at least one metal including a silicide layer thereof. Characterized in that an insulating layer is formed on the source / drain wiring, and an anodic oxide layer is formed on each of the side surfaces of the source / drain wiring. The passivation insulating layer can be excluded from the lateral electric field between them,
In addition, a passivation insulating layer is formed on the source / drain electrodes, and an insulating layer, which is an oxide layer thereof, is formed on the side surfaces of the source / drain electrodes. Reliability is further ensured.

According to a third aspect of the present invention, there is provided a liquid crystal image display device, comprising: an insulated gate transistor on one main surface; a pixel electrode connected to a drain of the insulated gate transistor; A first transparent insulating substrate in which unit pixels having at least one counter electrode formed at a distance from each other are arranged in a two-dimensional matrix, a first transparent insulating substrate, and a second transparent insulating substrate. In a liquid crystal image display device filled with liquid crystal between the conductive insulating substrate or the color filter,
The gate of the insulated gate transistor and the counter electrode are formed on the first transparent insulating substrate, and the channel of the insulated gate transistor formed on the first transparent insulating substrate via a gate insulating layer A silicon oxide layer containing an impurity is formed thereon, and a source and an impurity are formed on the amorphous silicon layer which does not contain an impurity and which is in contact with the silicon oxide layer and serves as a channel via the amorphous silicon layer containing the impurity. The drain wiring is formed of at least one heat-resistant metal layer capable of being anodized or at least one metal layer including a silicide layer thereof, and an anodic oxide layer is formed on the surface of the source / drain wiring, respectively. The configuration eliminates the need for the conventional passivation insulating layer formation step, and allows the passivation insulating layer to passivate from the lateral electric field acting between the pixel electrode and the counter electrode. Can be excluded ® down the insulating layer,
Since the burn-in of the display image is suppressed and the insulating layer, which is an oxide layer thereof, is formed on the entire surface of the source / drain electrodes, the reliability of the liquid crystal panel is further secured.

According to a fourth aspect of the present invention, in the liquid crystal image display device, an insulated gate transistor on one main surface, a pixel electrode connected to a drain of the insulated gate transistor, and a predetermined distance from the pixel electrode. A first transparent insulating substrate in which unit picture elements each having at least one counter electrode formed at a distance from each other are arranged in a two-dimensional matrix, and wherein the first transparent insulating substrate and the second transparent insulating substrate In a liquid crystal image display device in which liquid crystal is filled between a transparent insulating substrate or a color filter, a gate of the insulated gate transistor and the counter electrode are formed on a first transparent insulating substrate, Forming a silicon oxide layer containing an impurity on a channel of an insulated gate transistor formed on the first transparent insulating substrate via an insulating layer; The source / drain wiring formed on the amorphous silicon layer which does not contain impurities serving as a channel via the porous silicon layer is formed by using at least an anodically oxidizable heat-resistant metal layer or one or more metal layers including the silicide layer thereof. And a photosensitive polyimide resin layer is formed on the source / drain wiring. With this configuration, the conventional passivation insulating layer forming step becomes unnecessary, and works between the pixel electrode and the counter electrode. Since the passivation insulating layer can be excluded from the lateral electric field, the burn-in of the displayed image is suppressed, and the insulating layer made of organic resin is formed on the source / drain electrodes. Is secured.

According to a fifth aspect of the present invention, in the liquid crystal image display device, the insulated gate transistor, the picture element electrode connected to the drain of the insulated gate transistor on one main surface, and a predetermined distance from the picture element electrode. A first transparent insulating substrate in which unit picture elements each having at least one counter electrode formed at a distance from each other are arranged in a two-dimensional matrix, and wherein the first transparent insulating substrate and the second transparent insulating substrate In a liquid crystal image display device in which liquid crystal is filled between a transparent insulating substrate or a color filter, a gate of the insulated gate transistor and the counter electrode are formed on a first transparent insulating substrate, Forming a silicon oxide layer containing an impurity on a channel of an insulated gate transistor formed on the first transparent insulating substrate via an insulating layer; The source / drain wiring formed on the amorphous silicon layer which does not contain impurities serving as a channel via the porous silicon layer is formed by using at least an anodically oxidizable heat-resistant metal layer or one or more metal layers including the silicide layer thereof. And a photosensitive polyimide resin layer is formed on the surface of the source / drain wiring. With this configuration, the conventional passivation insulating layer forming step becomes unnecessary, and the gap between the pixel electrode and the counter electrode is eliminated. Since the passivation insulating layer can be excluded from the lateral electric field acting on the surface, the burn-in of the displayed image is suppressed, and the insulating layer made of organic resin is formed on the entire surface of the source / drain electrodes. The reliability of the liquid crystal panel is further ensured.

According to a sixth aspect of the present invention, in the liquid crystal image display device, the insulated gate transistor, the picture element electrode connected to the drain of the insulated gate transistor on one main surface, and a predetermined distance from the picture element electrode. A first transparent insulating substrate in which at least one unit pixel having at least one counter electrode formed therebetween is arranged in a two-dimensional matrix, and the first transparent insulating substrate and the second transparent insulating substrate In a liquid crystal image display device in which liquid crystal is filled between a transparent insulating substrate or a color filter, a gate of the insulated gate transistor and the counter electrode are formed on a first transparent insulating substrate, Forming a tantalum oxide layer and a silicon oxide layer containing impurities on a channel of an insulated gate transistor formed on the first transparent insulating substrate via an insulating layer, and contacting the tantalum oxide layer; A source / drain wiring formed on an amorphous silicon layer which does not contain an impurity serving as a channel through an amorphous silicon layer containing an impurity can be made of a tantalum layer or a silicide layer thereof, or a combination thereof with aluminum as a main component. A passivation insulating layer formed by laminating a metal layer and forming an insulating layer on the source / drain wiring. Can be excluded, and the burn-in of the displayed image can be suppressed. In addition, since the passivation insulating layer is formed on the source / drain electrodes, the reliability of the liquid crystal panel can be ensured. In addition, since the insulating layer on the channel is thick, it is resistant to external contamination and damage.

According to a seventh aspect of the present invention, in the liquid crystal image display device, an insulated gate transistor on one main surface, a pixel electrode connected to a drain of the insulated gate transistor, and a predetermined distance from the pixel electrode. A first transparent insulating substrate in which unit picture elements each having at least one counter electrode formed at a distance from each other are arranged in a two-dimensional matrix, and wherein the first transparent insulating substrate and the second transparent insulating substrate In a liquid crystal image display device in which liquid crystal is filled between a transparent insulating substrate or a color filter, a gate of the insulated gate transistor and the counter electrode are formed on the first transparent insulating substrate, Forming a tantalum oxide layer and a silicon oxide layer containing impurities on a channel of the insulated gate transistor formed on the first transparent insulating substrate via a gate insulating layer, and contacting the tantalum oxide layer; In addition, the source / drain wiring formed on the amorphous silicon layer which does not contain an impurity serving as a channel through the amorphous silicon layer containing an impurity can be made of a tantalum layer or a silicide layer thereof, or a combination of these with aluminum as a main component. A metal layer formed on the source / drain wiring, and an anodic oxide layer formed on each of the side surfaces of the source / drain wiring. The passivation insulating layer can be excluded from the lateral electric field acting between the electrode and the counter electrode, thereby suppressing the burn-in of the displayed image. The passivation insulating layer is formed on the source / drain electrodes, An insulating layer that is an oxide layer of these layers is formed on the side of the drain electrode, further ensuring the reliability of the liquid crystal panel. It is. In addition, since the insulating layer on the channel is thick, it is resistant to external contamination and damage.

In the liquid crystal image display device according to the present invention, an insulated gate transistor, a picture element electrode connected to a drain of the insulated gate transistor, and a predetermined distance from the picture element electrode are formed on one main surface. A first transparent insulating substrate in which at least one unit pixel having at least one counter electrode formed therebetween is arranged in a two-dimensional matrix, and the first transparent insulating substrate and the second transparent insulating substrate In a liquid crystal image display device in which liquid crystal is filled between a transparent insulating substrate or a color filter, a gate of the insulated gate transistor and the counter electrode are formed on the first transparent insulating substrate, Forming a tantalum oxide layer and a silicon oxide layer containing impurities on a channel of the insulated gate transistor formed on the first transparent insulating substrate via a gate insulating layer, and contacting the tantalum oxide layer; In addition, the source / drain wiring formed on the amorphous silicon layer which does not contain an impurity serving as a channel through the amorphous silicon layer containing an impurity can be made of a tantalum layer or a silicide layer thereof, or a material containing aluminum as a main component. And a anodic oxide layer formed on the surface of each of the source and drain wirings. With this configuration, the conventional passivation insulating layer forming step becomes unnecessary, and the pixel electrode and the The passivation insulating layer can be excluded from the lateral electric field acting between the opposing electrodes, suppressing the burn-in of the displayed image, and forming an insulating layer that is an oxide layer of these oxide layers on the entire surface of the source / drain electrodes. Is formed,
The reliability of the liquid crystal panel is further ensured. In addition, since the insulating layer on the channel is thick, it is resistant to external contamination and damage.

According to a ninth aspect of the present invention, there is provided a liquid crystal image display device, comprising: an insulated gate transistor on one main surface; a pixel electrode connected to a drain of the insulated gate transistor; A first transparent insulating substrate in which at least one unit pixel having at least one counter electrode formed therebetween is arranged in a two-dimensional matrix, and the first transparent insulating substrate and the second transparent insulating substrate In a liquid crystal image display device in which liquid crystal is filled between a transparent insulating substrate or a color filter, a gate of the insulated gate transistor and the counter electrode are formed on the first transparent insulating substrate, Forming a tantalum oxide layer and a silicon oxide layer containing impurities on a channel of the insulated gate transistor formed on the first transparent insulating substrate via a gate insulating layer, and contacting the tantalum oxide layer; In addition, the source / drain wiring formed on the amorphous silicon layer which does not contain an impurity serving as a channel through the amorphous silicon layer containing an impurity can be made of a tantalum layer or a silicide layer thereof, or a material containing aluminum as a main component. And a photosensitive polyimide resin layer is formed on the source / drain wiring. With this configuration, the conventional passivation insulating layer forming step becomes unnecessary, and a pixel electrode and The passivation insulating layer can be excluded from the lateral electric field acting between the opposing electrodes, suppressing the burning of the displayed image, and forming the insulating layer made of an organic resin on the source / drain electrodes. Therefore, the reliability of the liquid crystal panel is ensured. In addition, since the insulating layer on the channel is thick, it is resistant to external contamination and damage.

The liquid crystal image display device according to claim 10 is
At least one insulated gate transistor, a pixel electrode connected to the drain of the insulated gate transistor, and a counter electrode formed at a predetermined distance from the pixel electrode on one main surface. Having a first transparent insulating substrate in which unit pixels provided are arranged in a two-dimensional matrix, and filling a liquid crystal between the first transparent insulating substrate and the second transparent insulating substrate or the color filter In the liquid crystal image display device, the gate of the insulated gate transistor and the counter electrode are formed on a first transparent insulating substrate, and formed on the first transparent insulating substrate via a gate insulating layer. A tantalum oxide layer and a silicon oxide layer containing impurities are formed on the channel of the insulated gate transistor, and the channel is in contact with the tantalum oxide layer and through the amorphous silicon layer containing impurities. Forming a source / drain wiring formed on an amorphous silicon layer containing no impurities by a tantalum layer or a silicide layer thereof or a lamination of them with a metal layer containing aluminum as a main component; A photosensitive polyimide resin layer is formed on the surface of the wiring.This configuration eliminates the need for a conventional passivation insulating layer forming step, and eliminates the need for a horizontal electric field acting between the pixel electrode and the counter electrode. Since the passivation insulating layer can be excluded from the above, the burn-in of the display image is suppressed, and the insulating layer made of organic resin is formed on the entire surface of the source / drain electrodes,
The reliability of the liquid crystal panel is further ensured. In addition, since the insulating layer on the channel is thick, it is resistant to external contamination and damage.

The method of manufacturing a semiconductor device for an image display device according to claim 11 is the method for manufacturing a liquid crystal image display device according to claim 1, wherein at least one layer is provided on one main surface of the insulating substrate. Selectively forming a scanning line and a counter electrode, which are made of a first metal layer and also serves as a gate of an insulated gate transistor; and forming at least one gate insulating layer and a first amorphous layer containing no impurities. After sequentially depositing a porous silicon layer and a second amorphous silicon layer containing impurities, one or more second metal layers including an anodically oxidizable heat-resistant metal layer or its silicide layer and an insulating layer are formed. Successively depositing, selectively removing the insulating layer and the second metal layer on the gate to expose the second amorphous silicon layer, and then anodizing the second amorphous silicon layer.
Converting the amorphous silicon layer into a silicon oxide layer; and selectively removing the insulating layer, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer. Exposing the gate insulating layer and forming source / drain wiring having an insulating layer thereon.
Since a silicon oxide layer containing impurities is formed on the channel by this method, a highly reliable and non-burning IPS can be obtained by using a conventional passivation insulating layer.
Type liquid crystal panel is obtained.

According to a twelfth aspect of the present invention, there is provided a method of manufacturing a semiconductor device for an image display device according to the second aspect, wherein at least one layer is formed on one main surface of the insulating substrate. Selectively forming a scanning line and a counter electrode, which are made of a first metal layer and also serves as a gate of an insulated gate transistor; and forming at least one gate insulating layer and a first amorphous layer containing no impurities. After successively depositing a porous silicon layer and a second amorphous silicon layer containing impurities, one or more second metal layers including an anodically oxidizable heat-resistant metal layer or a silicide layer thereof and an insulating layer are formed. Successively depositing, selectively removing the insulating layer and the second metal layer on the gate to expose a second amorphous silicon layer, and then anodizing the second amorphous silicon layer.
Converting the amorphous silicon layer into a silicon oxide layer; and selectively removing the insulating layer, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer. Forming a source / drain wiring having an insulating layer thereon by exposing the gate insulating layer;
12. The method according to claim 11, further comprising a step of forming an oxide layer on each of the side surfaces of the drain wiring and the side surfaces of the first and second amorphous silicon layers. Since the insulating oxide layer is also formed on the side surface of the wiring, the reliability is further improved.

According to a thirteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device for an image display device according to the third aspect, wherein at least one layer is provided on one main surface of the insulating substrate. Selectively forming a scanning line and a counter electrode, which are made of a first metal layer and also serves as a gate of an insulated gate transistor; and forming at least one gate insulating layer and a first amorphous layer containing no impurities. Of sequentially depositing a porous silicon layer and a second amorphous silicon layer containing impurities, and then depositing one or more second metal layers including an anodizable heat-resistant metal layer or a silicide layer thereof. And selectively removing the second metal layer on the gate to expose the second amorphous silicon layer, and then convert the second amorphous silicon layer to a silicon oxide layer by anodic oxidation. Process, a second metal layer, a second amorphous silicon layer and Forming a source / drain wiring by selectively removing the first amorphous silicon layer and the first amorphous silicon layer to expose the gate insulating layer; and anodizing the surface of the source / drain wiring and the first amorphous silicon layer. 12. The method according to claim 11, further comprising the step of forming an oxide layer on each of the silicon layer and the side surface of the second amorphous silicon layer. In addition, since an insulating oxide layer is formed on the surface of the source / drain wiring, the reliability is further improved.

According to a fourteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device for an image display device according to the fourth aspect, wherein at least one layer is provided on one main surface of the insulating substrate. Selectively forming a scanning line and a counter electrode, which are made of a first metal layer and also serves as a gate of an insulated gate transistor; and forming at least one gate insulating layer and a first amorphous layer containing no impurities. Depositing a porous silicon layer and a second amorphous silicon layer containing impurities sequentially, and then depositing one or more second metal layers including an anodizable heat-resistant metal layer or a silicide layer thereof. And selectively removing the second metal layer on the gate to expose the second amorphous silicon layer, and then convert the second amorphous silicon layer to a silicon oxide layer by anodic oxidation. Process and the second gold layer using the photosensitive polyimide resin layer. Source by selectively removing the layer and the second amorphous silicon layer and the first amorphous silicon layer,
12. A method of forming a drain wiring, and a step of leaving the patterned photosensitive polyimide resin layer as it is. In this method, in addition to the function of claim 11, a conventional passivation insulating layer is used. In addition, since an insulating layer made of an organic resin is formed on the source / drain wiring, reliability is improved.

According to a fifteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device for an image display device according to the fifth aspect, wherein the patterned photosensitive polyimide resin layer is heated. This method is characterized in that the insulating layer made of an organic resin is formed on the surface of the source / drain wiring without using the conventional passivation insulating layer, in addition to the function of claim 11. Therefore, the reliability is improved.

According to a sixteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device for an image display device according to the sixteenth aspect of the present invention, wherein the semiconductor device is provided on one main surface of the insulating substrate.
A step of selectively forming a scan line and a counter electrode, each of which is composed of one or more first metal layers and also serves as a gate of an insulated gate transistor, and one or more gate insulating layers and a first impurity-free layer. After sequentially depositing an amorphous silicon layer and a second amorphous silicon layer containing impurities, an anodizable tantalum layer or a silicide layer thereof, or a second metal layer mainly composed of aluminum Stacking and sequentially depositing an insulating layer, and selectively removing the insulating layer and the second metal layer on the gate to expose the tantalum layer, and then anodizing the tantalum layer and the second metal layer. Converting the two amorphous silicon layers into a tantalum oxide layer and a silicon oxide layer, respectively, and selecting the insulating layer, the lamination, the second amorphous silicon layer and the first amorphous silicon layer. Gate insulation Forming a source / drain wiring having an insulating layer thereon, thereby forming a tantalum oxide layer and a silicon oxide layer containing impurities on the channel. By using a conventional passivation insulating layer, an IPS type liquid crystal panel having high reliability and no burn-in can be obtained. In addition, since the insulating layer on the channel is thick, it is resistant to external contamination and damage.

A method for manufacturing a semiconductor device for an image display device according to claim 17 is the method for manufacturing a liquid crystal image display device according to claim 7, wherein one or more layers are formed on one main surface of the insulating substrate. Selectively forming a scanning line and a counter electrode, which are made of a first metal layer and also serves as a gate of an insulated gate transistor; and forming at least one gate insulating layer and a first amorphous layer containing no impurities. After sequentially depositing a porous silicon layer and a second amorphous silicon layer containing impurities, an anodically oxidizable tantalum layer or a silicide layer thereof or a combination thereof with a second metal layer mainly containing aluminum is used. Sequentially depositing a stack and an insulating layer;
After selectively removing the metal layer to expose the tantalum layer,
Converting the tantalum layer and the second amorphous silicon layer into a tantalum oxide layer and a silicon oxide layer, respectively, by anodic oxidation; and stacking the insulating layer and the second amorphous silicon layer and the first amorphous silicon layer. Selectively removing the amorphous silicon layer and exposing the gate insulating layer to form a source / drain wiring having an insulating layer thereon; and anodizing the side surfaces and the first side of the source / drain wiring. 17. A method of forming an oxide layer on the side surfaces of an amorphous silicon layer and a second amorphous silicon layer, the method comprising the steps of: Since the insulating oxide layer is formed on the side surface of the source / drain wiring in combination with the layers, the reliability is further improved.

According to a eighteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device for an image display device according to the eighteenth aspect, wherein at least one layer is formed on one main surface of the insulating substrate. Selectively forming a scanning line and a counter electrode, which are made of a first metal layer and also serves as a gate of an insulated gate transistor; and forming at least one gate insulating layer and a first amorphous layer containing no impurities. After sequentially depositing a porous silicon layer and a second amorphous silicon layer containing impurities, a tantalum layer or a silicide layer thereof, or a lamination of them with a second metal layer containing aluminum as a main component is deposited. And selectively removing the second metal layer on the gate to expose the tantalum layer, and then anodizing the tantalum layer and the second amorphous silicon layer with the tantalum oxide layer and the second amorphous silicon layer, respectively. Convert to silicon layer Forming the source / drain wiring by exposing the gate insulating layer by selectively removing the stack and the second amorphous silicon layer and the first amorphous silicon layer; Forming an oxide layer on the surface of the source / drain wiring and on the side surfaces of the first amorphous silicon layer and the second amorphous silicon layer by oxidation, respectively. 16
In addition to the above operation, since the insulating oxide layer is formed on the surface of the source / drain wiring without using the conventional passivation insulating layer, the reliability is further improved.

According to a nineteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device for an image display device according to the ninth aspect, wherein at least one layer is formed on one main surface of the insulating substrate. Selectively forming a scanning line and a counter electrode, which are made of a first metal layer and also serves as a gate of an insulated gate transistor; and forming at least one gate insulating layer and a first amorphous layer containing no impurities. After sequentially depositing a porous silicon layer and a second amorphous silicon layer containing impurities, a tantalum layer or a silicide layer thereof, or a lamination thereof with a second metal layer containing aluminum as a main component is deposited. And selectively removing the second metal layer on the gate to expose the tantalum layer, and then anodizing the tantalum layer and the second amorphous silicon layer with the tantalum oxide layer and the second amorphous silicon layer, respectively. Convert to silicon layer That step a photosensitive polyimide resin layer and the laminate and the second amorphous silicon layer and the first with
Forming a source / drain wiring by selectively removing the amorphous silicon layer and leaving the patterned photosensitive polyimide resin layer as it is. In addition to the function of Item 16, reliability is improved because an insulating layer made of an organic resin is formed on the source / drain wiring without using a conventional passivation insulating layer.

According to a twentieth aspect of the present invention, there is provided a method for manufacturing a semiconductor device for an image display device according to the tenth aspect, wherein the patterned photosensitive polyimide resin layer is heated. This structure is characterized in that the structure is left as it is. With this structure, in addition to the function of claim 16, without using a conventional passivation insulating layer,
Since the insulating layer made of the organic resin is formed on the surface of the source / drain wiring, the reliability is further improved.

[0060]

1 to 6 show an embodiment of the present invention.
It will be described based on. Members corresponding to those described in FIGS. 7 to 14 are denoted by the same reference numerals, and detailed description is omitted.

FIGS. 1 to 6 are cross-sectional views for explaining a process of manufacturing a unit picture element in a semiconductor device for an image display device according to the first to tenth embodiments of the present invention. Note that the planar arrangement configuration of the unit picture elements of the semiconductor device for an image display device according to the present embodiment is the same as that of the conventional example shown in FIG.

The first embodiment will be described with reference to FIGS. 1 (a) to 1 (d). In the first embodiment, similarly to the above-described conventional example, first, as shown in FIG. Using a film forming apparatus, one or more first metal layers having a thickness of about 0.1 to 0.3 μm may be formed of, for example, Cr, Ta,
Mo or the like is deposited, and the gate electrode 11 also serving as a scanning line and the counter electrode 40 are selectively formed by a fine processing technique.

Next, an SiNx (silicon nitride) layer 30 serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 by using a PCVD (plasma seed) device, and a second layer serving as a channel of an insulated gate transistor containing almost no impurities. The three types of thin film layers, one amorphous silicon layer 31 and the second amorphous silicon layer 33 containing impurities,
The layers are sequentially deposited with a film thickness of about −0.06 to 0.05 μm.

Then, as shown in FIG. 1B, a metal layer 34 made of anodically oxidizable Ta, Ti or a silicide thin film thereof as an heat-resistant metal layer, and an Al layer 35 as a low-resistance wiring layer, respectively. 0.05 ~ 0.1μm, 0.1 ~
A SiNx film having a thickness of about 0.3 μm is deposited thereon by using a PCVD apparatus in the same manner as before.
A passivation insulating layer 37 made of a layer is applied.

Next, as shown in FIG. 1C, an opening 61 narrower than the gate electrode 11 is formed on the gate electrode 11 using the photosensitive resin pattern 60, and a passivation insulating layer 37 is formed. The Al layer 35 and the heat-resistant metal layer 34 are selectively removed to partially expose the second amorphous silicon layer 33. Then, using the photosensitive resin pattern 60 (or the passivation insulating layer 37) as a mask, the second amorphous silicon layer 33 is partially anodized to be converted into the silicon oxide layer 63 containing impurities.

The second amorphous silicon layer 33 needs to be completely insulated. For this purpose, a part (thickness) of the first amorphous silicon layer 31 in contact with the second amorphous silicon layer 33 is required. It is important to anodize to about 0.01 μm), and a formation voltage corresponding to this is desirable.

Since the first amorphous silicon layer 31 has a very high resistance, it is necessary to devise light irradiation during anodic oxidation to reduce the resistance. At this time, the exposed A
Alumina (Al ₂ O ₃ ), which is an oxide layer,
Layer 65 is formed. Although not illustrated, the active substrate (glass substrate) 2 is immersed in a chemical solution containing, for example, ethylene glycol as a main component. In a region where the Al layer 35 is not attached and the Al layer 35 is partially exposed, anodization is performed by applying a positive potential using a connecting device such as a clip.

Further, as shown in FIG. 1D, the passivation insulating layer 37, the Al layer 35, the heat-resistant metal layer 34, and the second amorphous silicon layer 33 and the first amorphous silicon layer 31 are formed. By selectively removing the gate insulating layer 30 to expose it and forming the source / drain electrodes 12 and 21 and the pixel electrode 41 including the formed silicon oxide layer 63, the image display of the first embodiment is performed. The device semiconductor device is completed.

When the resistance of the signal line 12 does not matter, the source / drain electrodes 12 and 21 may be formed of a single layer of Ti or Ta which is an anodizable metal layer.

In the first embodiment, as can be seen from FIG. 1D, the drain electrode 21 of the insulated gate transistor, the source electrode 12 also serving as a signal line, and the pixel electrode 41 are formed on any of the electrodes. Although the insulating layer 37 exists, the outer surface is exposed, and the passivation of the wiring is not complete.

Therefore, in the second embodiment of the present invention, the reliability is further improved by adding a technique of forming an insulating layer on the side surface. That is, although not shown, the active substrate (glass substrate) 2 is immersed in a chemical conversion solution to form a conductive pattern in which the patterns 12 of the source electrodes 12 are connected in parallel or in series in an appropriate region on the outer periphery of the active substrate 2. ,
When a positive potential is applied by using a connection device such as a clip to perform anodic oxidation, as shown in FIG. 1E, all the conductive material not covered by the passivation insulating layer 37 is oxidized, and the oxide layer 38 is formed. It is formed.

That is, the silicon oxide layer 62 is formed on the side surface of the first amorphous silicon layer 31 containing no impurity constituting the channel, and the second amorphous silicon layer 33 containing the impurity which is a source / drain. A silicon oxide layer 63 containing impurity phosphorus is provided on the side surface of Ti and Ti (or T
a) and a source / drain electrode 12 made of a laminate of Al,
TiO ₂ (or Ta ₂ O ₅ )
A layer 64 and an Al ₂ O ₃ layer 65 are formed. The film thickness of various oxide layers is 0.1 to 0.2 μm when the formation voltage is 100 V, and a sufficient film thickness for the insulating layer 38 can be provided.

At the time of anodic oxidation of the side surfaces of source / drain electrodes 12 and 21, silicon oxide layer 63 containing impurity phosphorus is used.
If the formation voltage is lower than in the case of forming the silicon oxide layer, the thickness of the silicon oxide layer 63 does not increase. Also in the second embodiment, when the resistance value of the signal line does not matter, the source / drain wirings 12 and 21 can be formed of a single layer of Ti or Ta which is a metal layer capable of being anodized.

In the second anodic oxidation step, the drain side is anodized through the first amorphous silicon layer 31 which does not contain impurities and has a very high resistance. It is inevitable that the thickness of the oxide layer on the side is smaller than that on the source side.
Raise the electrical conductivity of the amorphous silicon layer 31 as much as possible,
A desirable result can be obtained by making the formation time as long as possible.

In the first and second embodiments, a passivation insulating layer is applied on the source / drain electrodes 12 and 21 by PCVD as in the conventional case. Therefore, an embodiment will be described in which a new passivation manufacturing method is applied to streamline the process or reduce the cost of production equipment. In addition, about those technologies,
JP-B-8-6964 and JP-B-8-16758
A part thereof is disclosed in Japanese Patent Publication No.

The third embodiment will be described with reference to FIG.
As shown in (a) and (b), a second amorphous silicon layer 33 containing phosphorus is deposited on the entire surface to a thickness of, for example, about 0.05 μm, and furthermore, anodically oxidizable Ta is formed as a heat-resistant metal layer. , T
i or a metal layer 34 of a silicide thin film thereof
And the AL layer 35 as a low resistance wiring layer
Through the same manufacturing process as in the first and second embodiments, until the film is deposited in a thickness of about μm or 0.3 μm, FIG.
As shown in (c), an opening 61 narrower than the gate electrode 11 is formed on the gate electrode 11 using the photosensitive resin pattern 60, and the heat-resistant metal layer 34 and the Al layer 35 are selectively removed. Thus, the second amorphous silicon layer 33 is partially exposed. Then, using the photosensitive resin pattern 60 (or the passivation insulating layer 37) as a mask, the second amorphous silicon layer 33 is partially anodized to be converted into a silicon oxide layer 63 containing impurities.

After the removal of the photosensitive resin pattern 60, FIG.
As shown in (d), the Al layer 35, the heat-resistant metal layer 34, and the second amorphous silicon layer 33 and the first amorphous silicon layer 31 are selectively removed to expose the gate insulating layer 30. Then, the source / drain electrodes 12, 21 and the pixel electrode 41 are formed including the formed silicon oxide layer 63.

Next, as shown in FIG. 2E, an Al ₂ O ₃ layer 65 as an insulating layer is formed again over the entire surface of the Al thin film 35 by anodic oxidation, thereby displaying an image according to the third embodiment. The device semiconductor device is completed.

In the third embodiment, TiO ₂ (or Ta) is formed on the side surfaces of the Ti (or Ta) layer 34 on the side surfaces of the source / drain electrodes 12 and 21 in the same manner as in the first and second embodiments. A Ta ₂ O ₅ ) layer 64, a silicon oxide layer 63 containing phosphorus as an impurity on the side surface of the second amorphous silicon layer 33 containing an impurity, and a first amorphous silicon layer containing no impurity A silicon oxide layer 62 is formed on each of the side surfaces of 31.

Also in the third embodiment, if the resistance value of the signal line does not matter, the source / drain electrodes 12 and 21 may be made of a single layer of Ti or Ta which is an anodizable metal layer. In the possible fourth embodiment, as shown in FIGS. 3A to 3C, the same manufacturing steps as in the third embodiment are performed until the silicon oxide layer 63 is selectively formed. As shown in FIG. 4D, a photosensitive polyimide resin pattern 70 corresponding to the pattern of the source / drain electrodes 12 and 21 including the silicon oxide layer 63 is formed on the Al layer 35 by a photolithography technique. The AL layer 35, the heat-resistant metal layer 34, the second amorphous silicon layer 33, and the first amorphous silicon layer 31 are selectively removed by using the system resin pattern 70 as a mask to expose the gate insulating layer 30. , It is to send directly to the panel assembly process to complete the revertive substrate.

In the fourth embodiment, if the resistance of the signal line does not matter, the source / drain electrodes 12 and 21 may be formed of a metal layer Ti or T
Further, in the fourth embodiment, the side surfaces of the source / drain electrodes 12 and 21 are exposed to provide more complete passivation as in the first embodiment. Similarly to the second embodiment and the third embodiment, the source / drain electrode 1 is formed by an appropriate technique.
It is necessary to form an insulating layer on the side surfaces of 2, 21. This is the fifth embodiment.

Specifically, after the selective formation of the source / drain electrodes 12 and 21 shown in FIG. 3 (d), the photosensitive polyimide resin pattern 70 used as an etching mask is heated to a temperature higher than post-baking, for example, It is fluidized by heating at 200 to 300 ° C. for several minutes, and as shown in FIG. Achieved by: Fluidization by heating is a unique feature of negative photosensitive resins.

In the structure shown in FIG. 3E, the source / drain electrodes 12 and 21 are connected to the heat-resistant barrier metal layer 34 and
Although it is formed by lamination with the AL layer 35 having a low resistance, when the resistance value of the signal line does not matter, the source / drain electrodes 12 and 21 are made of a heat-resistant barrier metal layer of Ti or Ta, or There is no problem in forming a single layer of these silicide thin films.

The silicon oxide layer 63 containing impurities on the channel of the insulated gate transistor has a function of protecting the channel, and is a constituent factor greatly affecting the electrical characteristics of the insulated gate transistor. Thickness has a significant effect. In each of the first to fifth embodiments, if the thickness of the silicon oxide layer 63 containing impurities is to be increased, the first amorphous silicon layer not containing impurities, which is the original composition, is increased in thickness. It is necessary to form a film, and the purpose of improving the productivity of PCVD, which is the initial goal, cannot be achieved. Therefore, in the following embodiments, the function is shared by the heat-resistant barrier metal layer.

In the sixth embodiment, as shown in FIGS. 4A and 4B, anodization is possible as a heat-resistant metal layer on one main surface of the active substrate 2, and the oxide layer is insulated. Metal layer 34 made of Ta (tantalum) or a silicide thin film having excellent resistance, and Al layer 3 as a low resistance wiring layer.
And 5 with a film thickness of about 0.1 μm and 0.3 μm, respectively.
Further, steps similar to those in the first embodiment are performed until a passivation insulating layer 37 made of a SiNx layer having a thickness of about 0.3 μm is deposited thereon using a PCVD apparatus.

Further, as shown in FIG. 4C, an opening 61 narrower than the gate electrode 11 is formed on the gate electrode 11 using the photosensitive resin pattern 60, and the passivation insulating layer 37 and the Al The layer 35 is selectively removed and T
The a layer 34 is partially exposed. Then, using the photosensitive resin pattern 60 as a mask or the passivation insulating layer 37 as a mask, the Ta layer 34 and the second amorphous silicon layer 33 are partially anodized to form a tantalum oxide layer 6.
4 and a silicon oxide layer 63 containing impurities. In this case, as compared with the first embodiment to the fifth embodiment, the formation voltage of the anodic oxidation needs to be set higher by the amount necessary for forming the tantalum oxide layer 64.

Thereafter, as shown in FIG. 4D, the passivation insulating layer 37, the Al layer 35, the Ta layer 34, and the second amorphous silicon layer 33 and the first amorphous silicon layer 31 are selected. To remove the gate insulating layer 30,
By forming the source / drain electrodes 12, 21 and the pixel electrode 41 including the formed tantalum oxide layer 64, the semiconductor device for an image display device of the sixth embodiment is completed.

Also in the sixth embodiment, as can be seen from FIG. 4D, the drain electrode 21 of the insulated gate transistor, the source electrode 12 also serving as a signal line, and the pixel electrode 41 Although the insulating layers 63 to 65 are present, the outer surface is exposed, and the passivation of the wiring is not complete. Therefore, in the seventh embodiment, a technique of forming the insulating layer 66 on the side surface is added to further improve the reliability.

In the seventh embodiment, although not shown, the active substrate (glass substrate) 2 is immersed in a chemical conversion solution, and the pattern of the source electrodes 12 is arranged in parallel or in series in an appropriate region on the outer periphery of the active substrate 2. When a positive potential is applied to the conductive pattern connected to the substrate by using a connecting device such as a clip to perform anodic oxidation, the conductive material not covered with the passivation insulating layer 37 as shown in FIG. All are oxidized to form an oxide layer. That is, a silicon oxide layer 62 on the side surface of the first amorphous silicon layer 31, a silicon oxide layer 63 containing impurity phosphorus on the side surface of the second amorphous silicon layer 33, and Ta and Al The tantalum oxide (Ta ₂ O ₅ ) layer 64 and the Al ₂ O ₃ layer 6
5 are formed. The formation voltage of each oxide layer is 10
When the voltage is 0 V, the thickness is 0.1 to 0.2 μm, and the insulating layer 66 can have a sufficient thickness.

In the eighth embodiment, as shown in FIGS. 5A and 5B, a metal layer 34 made of anodizable Ta or a silicide thin film thereof is formed on the entire surface as a heat-resistant metal layer.
An Al layer 35 is formed as a low-resistance wiring layer by using a 0.1 μm
Until a film having a thickness of about 3 μm is formed, the same manufacturing steps as those of the third to fifth embodiments are performed, and FIG.
As shown in FIG. 5, an opening 61 narrower than the gate electrode 11 is formed on the gate electrode 11 using the photosensitive resin pattern 60.
Is formed, and the Al layer 35 is selectively removed to partially expose the Ta layer 34. Then, the photosensitive resin pattern 60
Using the (or passivation insulating layer 37) as a mask, the Ta layer 34 and the second amorphous silicon layer 33 are partially anodized to be converted into a tantalum oxide layer 64 and a silicon oxide layer 63 containing impurities.

Next, as shown in FIG.
5, including the Ta layer 34, the second amorphous silicon layer 33, and the first amorphous silicon layer 31 which are selectively removed to expose the gate insulating layer 30 and the formed tantalum oxide layer 64 To form source / drain electrodes 12, 21 and picture element electrode 41.

Finally, as shown in FIG. 5E, the Al ₂ O ₃ layer 65, which is an insulating layer, is formed again by anodic oxidation over the entire surface of the Al layer 35.
The semiconductor device for an image display device according to the embodiment is completed.

In the ninth embodiment, as shown in FIGS. 6A to 6C, the same manufacturing steps as in the eighth embodiment are performed until the tantalum oxide layer 64 is selectively formed. d)
As shown in FIG.
A photosensitive polyimide-based resin pattern 70 corresponding to the source / drain electrodes 12 and 21 containing Al is formed on the AL layer 35, and using the resin pattern 70 as a mask,
5, after selectively removing the Ta layer 34, the second amorphous silicon layer 33, and the first amorphous silicon layer 31 to expose the gate insulating layer 30 and complete the active substrate 2, This is sent to the panel assembly process.

In the structure of the ninth embodiment, as in the sixth embodiment, the side surfaces of the source / drain electrodes 12 and 21 are exposed, and in order to provide more complete passivation, the structure of the ninth embodiment is different from that of the ninth embodiment. Similarly to the eighth embodiment, it is necessary to form an insulating layer on the side surfaces of the source / drain electrodes 12 and 21 by an appropriate technique. That's the tenth
It is an embodiment.

More specifically, after the selective formation of the source / drain electrodes 12 and 21 shown in FIG. 6D, the photosensitive polyimide resin pattern 70 used as an etching mask is exposed to a high temperature of post-baking or higher. After heating and fluidizing, as shown in FIG.
This can be achieved by a very simple means of coating 71 the side surfaces 2 and 21 with a photosensitive polyimide resin.

In the sixth through tenth embodiments, the source / drain electrodes 12 and 21 are
Although the description has been made by using the laminated structure of the a layer 34 and the AL layer 35 having a low resistance, when the resistance value of the signal line does not matter, the source / drain electrodes 12 and 21 may be replaced with a tantalum layer or a silicide thin film thereof. There is no problem in forming a single layer.

Note that the requirement of the present invention is that a non-burning IP
An object of the present invention is to provide an S type liquid crystal panel. Therefore, the three-layer film formation by the PCVD apparatus is performed by combining the first insulating layer with the first insulating layer.
Restrictions must be placed on the sequential formation of an amorphous silicon layer containing no impurity and a second amorphous silicon layer containing an impurity, and in some cases, the signal line may be made of a material that can be anodized. Except for this, semiconductor devices for image display devices having different materials or thicknesses of scanning lines, signal lines, gate insulating layers, and the like also belong to the category of the present invention.

[0098]

As described above, according to the liquid crystal image display device and the method of manufacturing a semiconductor device for an image display device of the present invention, in the active type liquid crystal panel of the IPS system, the constituent factors of the liquid crystal cell are reduced. Since the passivation insulating layer having poor film quality is excluded, unnecessary charge accumulation does not occur in the liquid crystal cell, so that an image display without burning can be obtained.

Further, when the passivation forming method without using the PCVD apparatus is used, the investment amount of the production equipment can be reduced, and the yield can be expected to be improved since no generation of particles is caused. The effect is also obtained.

Further, since it is not necessary to form a thick amorphous silicon layer containing no impurities when manufacturing a channel-etch type TFT, the generation of particles of the PCVD apparatus or the improvement of the productivity have to be compared with the existing apparatus. Many improvements are realized in comparison.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a manufacturing process of a semiconductor device for an image display device according to a first embodiment and a second embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing process of a semiconductor device for an image display device according to a third embodiment of the present invention.

FIG. 3 is a sectional view for explaining a manufacturing process of a semiconductor device for an image display device according to a fourth embodiment and a fifth embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a manufacturing process of the semiconductor device for an image display device according to the sixth and seventh embodiments of the present invention.

FIG. 5 is a cross-sectional view for explaining a manufacturing process of a semiconductor device for an image display device according to an eighth embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining a manufacturing process of the semiconductor device for an image display device according to the ninth and tenth embodiments of the present invention.

FIG. 7 is a perspective view showing a mounting state of a conventional liquid crystal panel.

FIG. 8 is an equivalent circuit diagram of a conventional liquid crystal panel.

FIG. 9 is a sectional view of a conventional liquid crystal panel.

FIG. 10 is a plan view of a conventional active substrate.

FIG. 11 is a cross-sectional view for explaining a manufacturing process of a conventional active substrate.

FIG. 12 is a cross-sectional view of a conventional IPS type liquid crystal panel.

FIG. 13 is a plan view of a conventional IPS active substrate.

FIG. 14 is a cross-sectional view for explaining a manufacturing process of a conventional IPS type active substrate.

[Explanation of symbols]

Reference Signs List 1 liquid crystal panel 2 active substrate (one glass substrate) 3 semiconductor integrated circuit chip 4 TCP film 9 color filter (other glass substrate) 10 insulated gate transistor 11 scanning line (gate electrode) 12 signal line (source wiring, source electrode) 13) liquid crystal cell 17 liquid crystal 20 alignment film 21 drain electrode (picture element electrode) 22 (transparent) picture element electrode 30 gate insulating layer (SiNx) 31 (first) amorphous silicon layer containing no impurity 32 etching stopper (SiNx) layer 33 (second) amorphous silicon layer containing impurities 34 Heat resistant barrier metal layer (Ti) 35 Low resistance wiring layer (Al) 37 Passivation insulating layer 38 Opening 40 Counter electrode (of IPS panel) 41 Pixel electrode 60 Photosensitive resin pattern 62 Silicon oxide layer (on the side) 63 Impurity Photosensitive polyimide resin pattern plastically deformed without silicon oxide layer 64 refractory barrier metal (tantalum) layer oxide layer of the oxide layer 65 of aluminum (Al ₂ O ₃₎ 70 photosensitive polyimide resin pattern 71 heated

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 GA60 HA27 JA24 JA34 JA36 JA41 JB52 JB57 JB69 KA05 KA10 MA08 MA12 MA24 MA29 NA01 NA27 PA01 PA08 QA07 5C094 AA12 AA42 AA43 AA54 BA03 BA43 BA44 CA19 CA24 DA13 DA04 DB03 FA01 FA02 FB01 FB02 FB15 GA10 GB10 5F110 CC07 DD02 EE03 EE04 EE05 EE44 FF03 FF30 GG02 GG15 GG24 GG35 HK03 HK04 HK05 HK21 NN02 NN04 NN22 NN23 NN24 NN27 NN35 NN38 QQ01

Claims (20)

[Claims] 1. An insulated gate transistor on one main surface, a picture element electrode connected to a drain of the insulated gate transistor, and a counter electrode formed at a predetermined distance from the picture element electrode. A first transparent insulating substrate in which at least one unit picture element is arranged in a two-dimensional matrix, and a first transparent insulating substrate and a second transparent insulating substrate or a color filter; In a liquid crystal image display device in which liquid crystal is filled in between, a gate of the insulated gate transistor and the counter electrode are formed on the first transparent insulating substrate, and the first electrode is interposed via a gate insulating layer. A silicon oxide layer containing impurities is formed on a channel of an insulated gate transistor formed on a transparent insulating substrate, and a channel is in contact with the silicon oxide layer and through an amorphous silicon layer containing impurities. Forming a source / drain wiring formed on an amorphous silicon layer containing no impurities to be formed from at least one heat-resistant metal layer capable of being anodized or at least one metal layer including a silicide layer thereof; A liquid crystal image display device comprising an insulating layer formed on a wiring. 2. An insulated gate transistor on one main surface, a picture element electrode connected to a drain of the insulated gate transistor, and a counter electrode formed at a predetermined distance from the picture element electrode. A first transparent insulating substrate in which at least one unit picture element is arranged in a two-dimensional matrix, and a first transparent insulating substrate and a second transparent insulating substrate or a color filter; In a liquid crystal image display device in which liquid crystal is filled in between, the gate of the insulated gate transistor and the counter electrode are formed on the first transparent insulating substrate, and the first A silicon oxide layer containing an impurity is formed on a channel of an insulated gate transistor formed on a transparent insulating substrate, and a channel is in contact with the silicon oxide layer and through an amorphous silicon layer containing an impurity. Forming a source / drain wiring formed on an amorphous silicon layer containing no impurity by at least one heat-resistant metal layer capable of being anodized or at least one metal layer including a silicide layer thereof; A liquid crystal image display device comprising: an insulating layer formed on a wiring; and an anodized layer formed on each of side surfaces of the source / drain wiring. 3. An insulated gate transistor on one main surface, a picture element electrode connected to a drain of the insulated gate transistor, and a counter electrode formed at a predetermined distance from the picture element electrode. A first transparent insulating substrate in which at least one unit picture element is arranged in a two-dimensional matrix, and a first transparent insulating substrate and a second transparent insulating substrate or a color filter In a liquid crystal image display device filled with liquid crystal, the gate of the insulated gate transistor and the counter electrode are formed on the first transparent insulating substrate, and the first transparency is formed via a gate insulating layer. A silicon oxide layer containing an impurity is formed over a channel of an insulated gate transistor formed on an insulating substrate, and the channel is in contact with the silicon oxide layer and through an amorphous silicon layer containing an impurity. Forming a source / drain wiring formed on an amorphous silicon layer containing no impurities by at least one heat-resistant metal layer capable of being anodized or at least one metal layer including a silicide layer thereof; A liquid crystal image display device, wherein an anodized layer is formed on each surface of the liquid crystal display. 4. An insulated gate transistor, a pixel electrode connected to a drain of the insulated gate transistor, and a counter electrode formed at a predetermined distance from the pixel electrode on one main surface. A first transparent insulating substrate in which at least one unit picture element is arranged in a two-dimensional matrix, and a first transparent insulating substrate and a second transparent insulating substrate or a color filter; In a liquid crystal image display device in which a liquid crystal is filled in between, a gate of the insulated gate transistor and the counter electrode are formed on a first transparent insulating substrate, and the first transparent electrode is interposed via a gate insulating layer. Forming an impurity-containing silicon oxide layer on a channel of an insulated gate transistor formed on a conductive insulating substrate; contacting the silicon oxide layer with the channel through an impurity-containing amorphous silicon layer; Forming a source / drain wiring formed on an amorphous silicon layer containing no impurities by at least one heat-resistant metal layer capable of being anodized or at least one metal layer including a silicide layer thereof; A liquid crystal image display device comprising a photosensitive polyimide resin layer formed thereon. 5. An insulated gate transistor on one main surface, a picture element electrode connected to a drain of the insulated gate transistor, and a counter electrode formed at a predetermined distance from the picture element electrode. A first transparent insulating substrate in which at least one unit picture element is arranged in a two-dimensional matrix, and a first transparent insulating substrate and a second transparent insulating substrate or a color filter; In a liquid crystal image display device in which a liquid crystal is filled in between, a gate of the insulated gate transistor and the counter electrode are formed on a first transparent insulating substrate, and the first transparent electrode is interposed via a gate insulating layer. Forming an impurity-containing silicon oxide layer on a channel of an insulated gate transistor formed on a conductive insulating substrate; contacting the silicon oxide layer with the channel through an impurity-containing amorphous silicon layer; Forming a source / drain wiring formed on an amorphous silicon layer containing no impurities by at least one heat-resistant metal layer capable of being anodized or at least one metal layer including a silicide layer thereof; A liquid crystal image display device comprising a photosensitive polyimide resin layer formed on the surface of a liquid crystal display. 6. An insulated gate transistor on one main surface, a picture element electrode connected to a drain of the insulated gate transistor, and a counter electrode formed at a predetermined distance from the picture element electrode. A first transparent insulating substrate in which at least one unit picture element is arranged in a two-dimensional matrix, and a first transparent insulating substrate and a second transparent insulating substrate or a color filter; In a liquid crystal image display device in which a liquid crystal is filled in between, a gate of the insulated gate transistor and the counter electrode are formed on a first transparent insulating substrate, and the first transparent electrode is interposed via a gate insulating layer. Forming a tantalum oxide layer and a silicon oxide layer containing impurities on a channel of an insulated gate transistor formed on a conductive insulating substrate, and contacting the tantalum oxide layer with an amorphous silicon layer containing impurities interposed therebetween; Forming a source / drain wiring formed on an amorphous silicon layer containing no impurity serving as a channel by using a tantalum layer or a silicide layer thereof, or a lamination of them with a metal layer containing aluminum as a main component, Source·
A liquid crystal image display device comprising an insulating layer formed on a drain wiring. 7. An insulated gate transistor, a picture element electrode connected to a drain of the insulated gate transistor, and a counter electrode formed at a predetermined distance from the picture element electrode on one main surface. A first transparent insulating substrate in which at least one unit picture element is arranged in a two-dimensional matrix, and a first transparent insulating substrate and a second transparent insulating substrate or a color filter; In a liquid crystal image display device in which liquid crystal is filled in between, a gate of the insulated gate transistor and the counter electrode are formed on the first transparent insulating substrate, and the first electrode is interposed via a gate insulating layer. Forming a tantalum oxide layer and an impurity-containing silicon oxide layer on a channel of an insulated gate transistor formed on a transparent insulating substrate, and contacting the tantalum oxide layer and containing an impurity-containing amorphous silicon layer A source / drain wiring formed on an amorphous silicon layer containing no impurity serving as a channel through a tantalum layer or a silicide layer thereof, or a lamination thereof with a metal layer containing aluminum as a main component, A liquid crystal image display device comprising: an insulating layer formed on the source / drain wiring; and an anodic oxide layer formed on side surfaces of the source / drain wiring. 8. An insulated gate transistor on one main surface, a picture element electrode connected to a drain of the insulated gate transistor, and a counter electrode formed at a predetermined distance from the picture element electrode. A first transparent insulating substrate in which at least one unit picture element is arranged in a two-dimensional matrix, and a first transparent insulating substrate and a second transparent insulating substrate or a color filter; In a liquid crystal image display device in which liquid crystal is filled in between, a gate of the insulated gate transistor and the counter electrode are formed on the first transparent insulating substrate, and the first electrode is interposed via a gate insulating layer. Forming a tantalum oxide layer and an impurity-containing silicon oxide layer on a channel of an insulated gate transistor formed on a transparent insulating substrate, and contacting the tantalum oxide layer and containing an impurity-containing amorphous silicon layer A source / drain wiring formed on an amorphous silicon layer containing no impurity serving as a channel through a tantalum layer or a silicide layer thereof, or a lamination thereof with a metal layer containing aluminum as a main component, A liquid crystal image display device, wherein an anodic oxide layer is formed on the surface of each of the source / drain wirings. 9. An insulated gate transistor, a pixel electrode connected to a drain of the insulated gate transistor, and a counter electrode formed at a predetermined distance from the pixel electrode on one main surface. A first transparent insulating substrate in which at least one unit picture element is arranged in a two-dimensional matrix, and a first transparent insulating substrate and a second transparent insulating substrate or a color filter; In a liquid crystal image display device in which liquid crystal is filled in between, the gate of the insulated gate transistor and the counter electrode are formed on the first transparent insulating substrate, and the first Forming a tantalum oxide layer and an impurity-containing silicon oxide layer on a channel of an insulated gate transistor formed on a transparent insulating substrate, and contacting the tantalum oxide layer and containing an impurity-containing amorphous silicon layer A source / drain wiring formed on an amorphous silicon layer which does not contain impurities serving as a channel through a tantalum layer or a silicide layer thereof, or a lamination of them with a metal layer mainly containing aluminum, A liquid crystal image display device, wherein a photosensitive polyimide resin layer is formed on the source / drain wiring. 10. An insulated gate transistor, a picture element electrode connected to a drain of the insulated gate transistor, and a counter electrode formed at a predetermined distance from the picture element electrode on one main surface. A first transparent insulating substrate in which at least one unit picture element is arranged in a two-dimensional matrix, and a first transparent insulating substrate and a second transparent insulating substrate or a color filter; In a liquid crystal image display device in which a liquid crystal is filled in between, a gate of the insulated gate transistor and the counter electrode are formed on a first transparent insulating substrate, and the first transparent electrode is interposed via a gate insulating layer. Forming a tantalum oxide layer and a silicon oxide layer containing impurities on a channel of an insulated gate transistor formed on a conductive insulating substrate, and contacting the tantalum oxide layer with an amorphous silicon layer containing impurities. Forming a source / drain wiring formed on an amorphous silicon layer which does not contain impurities serving as a channel by using a tantalum layer or a silicide layer thereof, or a lamination thereof with a metal layer containing aluminum as a main component, The source
A liquid crystal image display device comprising a photosensitive polyimide resin layer formed on a surface of a drain wiring. 11. A step of selectively depositing a scan line comprising one or more first metal layers and also serving as a gate of an insulated gate transistor and a counter electrode on one main surface of an insulating substrate; One or more gate insulating layers and a first
After sequentially depositing an amorphous silicon layer and a second amorphous silicon layer containing an impurity, the insulating layer is insulated from one or more second metal layers including an anodizable heat-resistant metal layer or a silicide layer thereof. Forming a second amorphous silicon layer by selectively removing an insulating layer and a second metal layer on the gate, and then anodizing the second amorphous silicon layer. Converting the amorphous silicon layer to a silicon oxide layer; and selectively removing the insulating layer, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer to form a gate. Exposing the insulating layer and forming source / drain wiring having the insulating layer on the insulating layer. 12. A step of selectively depositing a scan line comprising at least one first metal layer and also serving as a gate of an insulated gate transistor and a counter electrode on one main surface of an insulating substrate; One or more gate insulating layers and a first
After successively depositing an amorphous silicon layer and a second amorphous silicon layer containing an impurity, the insulating layer is insulated from one or more second metal layers including the anodically oxidizable heat-resistant metal layer or its silicide layer. Forming a second amorphous silicon layer by selectively removing an insulating layer and a second metal layer on the gate, and then anodizing the second amorphous silicon layer. Converting the amorphous silicon layer to a silicon oxide layer; and selectively removing the insulating layer, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer to form a gate. A step of exposing the insulating layer and forming source / drain wiring having the insulating layer thereon, and oxidizing the side surfaces of the source / drain wiring and the side surfaces of the first and second amorphous silicon layers by anodic oxidation, respectively. Image display device comprising a step of forming a layer The method of manufacturing a semiconductor device. 13. A step of selectively forming a scanning line comprising at least one first metal layer and also serving as a gate of an insulated gate transistor and a counter electrode on one principal surface of an insulating substrate; One or more gate insulating layers and a first
Of an amorphous silicon layer and a second amorphous silicon layer containing impurities are sequentially deposited, and then one or more second metal layers including an anodically oxidizable heat-resistant metal layer or a silicide layer thereof are covered. Depositing and selectively removing the second metal layer on the gate to expose the second amorphous silicon layer, and then anodizing the second amorphous silicon layer to form a silicon oxide layer And selectively removing the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer to expose the gate insulating layer and form source / drain wiring Forming an oxide layer on the surface of the source / drain wiring and side surfaces of the first amorphous silicon layer and the second amorphous silicon layer by anodic oxidation. A method for manufacturing a semiconductor device for a display device. 14. A step of selectively depositing a scan line comprising at least one first metal layer and also serving as a gate of an insulated gate transistor and a counter electrode on one main surface of an insulating substrate; One or more gate insulating layers and a first
Of a heat-resistant metal layer capable of being anodized or one or more second metal layers including the silicide layer of the heat-resistant metal layer. Depositing and selectively removing the second metal layer on the gate to expose the second amorphous silicon layer, and then anodizing the second amorphous silicon layer to form a silicon oxide layer And selectively removing the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer using a photosensitive polyimide resin layer to remove source / drain wiring. A method of manufacturing a semiconductor device for an image display device, comprising: a forming step; and a step of leaving the patterned photosensitive polyimide resin layer as it is. 15. The method for manufacturing a semiconductor device for an image display device according to claim 14, wherein the patterned photosensitive polyimide resin layer is heated and left as it is. 16. A step of selectively depositing a scan line comprising one or more first metal layers and also serving as a gate of an insulated gate transistor and a counter electrode on one main surface of an insulating substrate; One or more gate insulating layers and a first
An amorphous silicon layer and a second amorphous silicon layer containing impurities are successively deposited, and then an anodically oxidizable tantalum layer or a silicide layer thereof, or a second metal mainly composed of aluminum Stacking layers and sequentially depositing an insulating layer, and selectively removing the insulating layer and the second metal layer on the gate to expose the tantalum layer, and then anodizing the tantalum layer. Converting the second amorphous silicon layer into a tantalum oxide layer and a silicon oxide layer, respectively; and forming the insulating layer and the laminate, the second amorphous silicon layer and the first amorphous silicon layer. Selectively removing the gate insulating layer to expose the gate insulating layer, and forming source / drain wiring having the insulating layer thereon. 17. A step of selectively depositing a scan line comprising one or more first metal layers and also serving as a gate of an insulated gate transistor and a counter electrode on one main surface of an insulating substrate; One or more gate insulating layers and a first
An amorphous silicon layer and a second amorphous silicon layer containing impurities are successively deposited, and then an anodically oxidizable tantalum layer or a silicide layer thereof, or a second metal mainly composed of aluminum Stacking layers and sequentially depositing an insulating layer; selectively removing the insulating layer and the second metal layer on the gate to expose the tantalum layer; and then anodizing the tantalum layer and the second metal layer. Converting the two amorphous silicon layers into a tantalum oxide layer and a silicon oxide layer, respectively, and selecting the insulating layer, the lamination, the second amorphous silicon layer and the first amorphous silicon layer. Forming a source / drain wiring having an insulating layer thereon by exposing the gate insulating layer, and anodic oxidation to form side surfaces of the source / drain wiring and the first amorphous silicon layer and the second amorphous silicon layer.
Forming an oxide layer on the side surface of the amorphous silicon layer and a method for manufacturing a semiconductor device for an image display device. 18. A step of selectively depositing a scan line comprising one or more first metal layers and also serving as a gate of an insulated gate transistor and a counter electrode on one main surface of an insulating substrate; One or more gate insulating layers and a first
After sequentially depositing an amorphous silicon layer and a second amorphous silicon layer containing impurities, a tantalum layer or a silicide layer thereof, or a lamination of them with a second metal layer containing aluminum as a main component And exposing the tantalum layer by selectively removing the second metal layer on the gate, and then anodizing the tantalum layer and the second amorphous silicon layer, respectively. Converting the stack and the second amorphous silicon layer and the first amorphous silicon layer to expose a gate insulating layer; Forming a wiring, and forming an oxide layer on the surface of the source / drain wiring and side surfaces of the first amorphous silicon layer and the second amorphous silicon layer by anodic oxidation. Picture The method of manufacturing a semiconductor device for a display device. 19. A step of selectively depositing a scanning line comprising one or more first metal layers and also serving as a gate of an insulated gate transistor and a counter electrode on one main surface of an insulating substrate; One or more gate insulating layers and a first
After sequentially depositing an amorphous silicon layer and a second amorphous silicon layer containing impurities, a tantalum layer or a silicide layer thereof, or a lamination of them with a second metal layer containing aluminum as a main component And exposing the tantalum layer by selectively removing the second metal layer on the gate, and then anodizing the tantalum layer and the second amorphous silicon layer, respectively. Converting the layer and the second amorphous silicon layer and the first amorphous silicon layer using a photosensitive polyimide resin layer to selectively remove the source and silicon oxide layers. A method for manufacturing a semiconductor device for an image display device, comprising: a step of forming a drain wiring; and a step of leaving the patterned photosensitive polyimide resin layer as it is. 20. The method according to claim 19, wherein the patterned photosensitive polyimide resin layer is left after being heated.