JP2000269802A - I / O circuit - Google Patents

Abstract

(57) Abstract: To prevent a malfunction of an input circuit caused by a large current drive of an output circuit without increasing a chip area and without largely changing a circuit layout design. SOLUTION: A transistor QP is provided between power supply lines 6 and 7.
5, a charging circuit 22 including QP6 and a capacitor 20 are connected in series, and a discharging circuit 23 including transistors QN5 and QN6 is connected between terminals of the capacitor 20. When the voltage of the power supply line 6 rises sharply due to ringing, the transistor QP5 turns on and the charge that causes the power supply line 6 to overshoot is absorbed by the capacitor 20. As a result, when the voltage between the terminals of the capacitor 20 sharply increases, the transistor QN5 is turned on after a delay time, and the capacitor 20 is discharged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output circuit formed on a semiconductor substrate and provided with an input circuit and an output circuit supplied with a pair of high-potential and low-potential DC power supply lines.

[0002]

2. Description of the Related Art For example, a general-purpose ASIC (Application Sp
A conventional input / output circuit configured on an ecific integrated circuit (IC for specific application) cell will be described with reference to FIGS. In FIG. 12 showing the electrical configuration of the input / output circuit, the input / output circuit 1 includes a large current output buffer circuit 2, an input buffer circuit 3, an output protection circuit 4, and an input protection circuit 5.

The large current output buffer circuit 2 is configured as a circuit configuration in which a PMOS transistor QP1 and an NMOS transistor QN1 are connected in a complementary manner. For example, a power supply line 6 supplied with a DC voltage of 5 [V] and a ground potential are supplied. Connected to the power supply line 7. That is, the source of the transistor QP1 and the source of the transistor QN1 are connected to the power supply line 6 and the power supply line 7, respectively, and the drains and the gates of the transistors QP1 and QN1 are connected. Here, the drains of the commonly connected transistors QP1 and QN1 are connected to the output line 8 as the output terminal of the large current output buffer circuit 2, and the commonly connected gate is connected to the input terminal A1. I have.

The input buffer circuit 3 has a circuit configuration in which a PMOS transistor QP2 and an NMOS transistor QN2 are connected in a complementary manner. For example, a power supply line 9 supplied with a DC voltage of 5 [V] and a power supply supplied with a ground potential are provided. Connected to the line 10. Here, the gates of the commonly connected transistors QP2 and QN2 are connected to the input line 11 as the input terminals of the input buffer circuit 3, and the commonly connected transistors QP2 and QN2 are connected to each other.
2 is connected to the output terminal A2.

When a voltage out of a normal voltage range (for example, 0 [V] to 5 [V]) is applied to the output line 8, the output protection circuit 4 outputs each transistor QP 1 of the large current output buffer circuit 2. , QN1 to prevent overvoltage from being applied. The output protection circuit 4 includes a PMO having a source and a drain connected between the power supply line 6 and the output line 8.
It comprises an S transistor QP3 and an NMOS transistor QN3 having a drain and a source connected between the output line 8 and the power supply line 7. Here, the transistor Q
Each gate of P3 and QN3 is connected to each source.

The input protection circuit 5 protects the transistors QP2 and QN2 of the input buffer circuit 3 from being applied with an overvoltage when a voltage out of the normal voltage range is applied to the input line 11. It is. The input protection circuit 5 includes a PMOS transistor QP4 having a source and a drain connected between the power supply line 6 and the input line 11,
An NMOS transistor QN4 having a drain and a source connected between the input line 11 and the power supply line 7. Here, the gates of the transistors QP4 and QN4 are connected to the respective sources.

The above-mentioned transistors QP1 to QP
P4 and QN1 to QN4 have parasitic capacitances CfQP1 to CfQP4 and CfQN1 to CfQN4 (CfQP2
And CfQN2 (not shown) can be shown as an equivalently connected model.

Power supply lines 6 and 7 common to the large current output buffer circuit 2, the output protection circuit 4, and the input protection circuit 5
Are respectively connected to bonding pads 12 and 13 for receiving power supply from a DC power supply (not shown) provided outside the ASIC. Similarly, the power lines 9 and 10 for the input buffer circuit 3 are connected to the bonding pads 12 and 13 by forming wiring paths independent of the power lines 6 and 7, respectively. The output line 8 and the input line 11 are connected to bonding pads 14 and 15, respectively.

The large current output buffer circuit 2, the input buffer circuit 3, the output protection circuit 4, and the input protection circuit 5
It is located at a relatively short distance within the SIC. Parasitic impedances corresponding to the frequency of the signal to be handled exist in the wiring portions from these arrangement positions to the bonding pads 12 to 15, and these are shown in the figure as impedances Za to Zf as equivalent circuit constants. I have. The impedances Za to Zf are represented by resistance components Ra to R
It is shown as a circuit combining f and inductances La to Lf.

FIG. 13 shows a portion of the input protection circuit 5 in the layout of the input / output circuit 1 on the ASIC chip. The ASIC chip is, for example, a CMOS.
It is composed of a gate array. In FIG. 13, bonding pads 15 arranged on the outer peripheral portion of the chip are provided.
On the other hand, the P-channel transistor formation region 1
6 and an N-channel transistor forming region 17 are arranged and formed in a strip shape. In each of the formation regions 16 and 17, a plurality of cell transistors of a predetermined size are formed, and the plurality of cell transistors constitute one circuit block sharing a power supply line disposed thereabove.

More specifically, each of the transistors QP4, QN4
Is composed of 10 cell transistors connected in parallel. The drains of these transistors QP4 and QN4 are connected to a bonding pad 15 via a wiring 11a serving as an input line 11, and a wiring 6a serving as a power supply line 6 and a power supply line are provided above the transistors QP4 and QN4, respectively. A wiring 7a as 7 is provided.

[0012]

However, in the input / output circuit 1 described above, the large current output buffer circuit 2
When the output current increases, the following problems may occur. That is, the bonding pad 14
When a large load (not shown) is connected to the input terminal A1 of the large current output buffer circuit 2, an H level (5
[V]) to L level (0 [V]) and L level to H
When an input signal S1 that changes to a level is given, the voltage of each part of the input / output circuit 1 changes with oscillation as shown in FIG. In FIG. 14 and the following description, the voltage of each unit means a voltage at a point near each of the circuits 2 to 5.

The input signal S to the large current output buffer circuit 2
At times t10 and t20 at which the level of 1 changes, the voltage of the output line 8 changes with a delay of the propagation delay time of the large current output buffer circuit 2, and the voltage has an overshoot and an undershoot having damped oscillation characteristics. (Ringing) occurs. This ringing is caused by the parasitic impedances Zb and Ze and the parasitic capacitances CfQP1 and CfQN.
1, which occurs due to CfQP3 and CfQN3.

The ringing generated on the output line 8 is transmitted to the power supply line 6 through the parasitic capacitances CfQP1 and CfQP3, and is also transmitted to the power supply line 7 through the parasitic capacitances CfQN1 and CfQN3.
Is propagated to Further, the ringing (AC voltage component) propagated to the power supply lines 6 and 7 is propagated to the input line 11 through the parasitic capacitances CfQP4 and CfQN4 of the transistors QP4 and QN4 of the input protection circuit 5. As a result, the voltage of the input line 11 fluctuates, and when the voltage of the input line 11 exceeds the threshold value of the input buffer circuit 3, the output signal S2 of the input buffer circuit 3 is inverted to cause a malfunction.

In order to prevent such a malfunction, as a layout on the chip, the transistors QP1 and QN1 forming the large current output buffer circuit 2 and the transistors QP2 and QN2 forming the input buffer circuit 3 and the input protection circuit 5 are formed. What is necessary is just to comprise in the circuit block different from the transistor QP4 and QN4 which comprise. However, such a configuration involves an increase in chip area, and also requires a significant change in the arrangement and wiring of each transistor in the conventional input / output circuit 1, resulting in an increase in design cost and product cost.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an output circuit without increasing the area occupied by an input / output circuit on a semiconductor substrate and without greatly changing the layout design. It is an object of the present invention to provide an input / output circuit capable of preventing a malfunction of an input circuit caused by superposition of an AC voltage component on a power supply line or the like caused by driving of the input circuit.

[0017]

In order to achieve the above object, an input / output circuit according to the present invention is formed on a semiconductor substrate.
In an input / output circuit provided with an input circuit and an output circuit supplied with power from a pair of high-potential and low-potential DC power lines, the pair of direct-current (DC) power supplies are absorbed so as to absorb an AC voltage component superimposed on the high-potential DC power line. A high-potential-side power stabilizing circuit is provided between the power supply lines, and the high-potential-side power stabilizing circuit is used to change the voltage of the high-potential DC power supply line relative to the high-potential-side charge absorbing element and the high-potential-side charge absorbing element. And a high-potential-side charge absorption circuit that performs a charge absorption operation accordingly.

According to this configuration, when an AC voltage component such as ringing is superimposed on the high-potential DC power supply line, the high-potential-side charge absorption circuit operates in response to a voltage change of the high-potential DC power supply line due to the AC voltage component. Since the potential-side charge absorbing element performs the charge absorbing operation on the high-potential DC power supply line, the AC voltage component superimposed on the high-potential DC power supply line is suppressed.

In this case, a high-potential-side power supply stabilizing circuit is provided with a capacitor provided as a high-potential-side charge absorbing element and a first switch provided as a high-potential-side charge absorbing circuit and forming a charging path for the capacitor. It is preferable to comprise a circuit and a second switch circuit forming a discharge path, and a switch control circuit for controlling a switching operation of the first and second switch circuits according to a voltage change of a high-potential DC power supply line. 2).

According to this configuration, the switch control circuit controls the switching operation of the first and second switch circuits according to the voltage change of the high-potential DC power supply line. Then, when the switch control circuit turns on the first switch circuit, a charge path to the capacitor is formed, and the AC voltage component superimposed on the high-potential DC power supply line is attenuated by the charge absorption action of the capacitor, and the switch control circuit is turned on by the switch control circuit. When the second switch circuit is turned on, a discharge path of the capacitor is formed, and the capacitor discharges electric charges in preparation for the next charge absorption operation. As a result, since the capacitor performs the charge absorption operation from the initial state without charge, the high-potential-side power supply stabilizing circuit can effectively suppress the AC voltage component such as ringing.

The high-potential-side power supply stabilizing circuit includes a capacitor provided as a high-potential-side charge absorbing element, a charging circuit provided as a high-potential-side charge absorbing circuit, and a charging operation for performing a charging operation on the capacitor. The capacitor can perform the charge absorption operation from the initial state with no charge in the same manner as described above, effectively suppressing the AC voltage component superimposed on the high-potential DC power supply line. (Claim 3).

In the above case, a protection circuit section is formed in each of the input circuit and the output circuit, and a high-potential-side charge absorption circuit is formed in a part of a region where the protection circuit section is formed, and a capacitor is formed in the semiconductor circuit. Preferably, it is formed in a lower layer of the bonding pad provided on the substrate (claim 4). According to this configuration, the capacitor and the high-potential-side charge absorption circuit can be formed without increasing the chip area and without substantially changing the conventional circuit layout.

Further, a low-potential-side power stabilization circuit connected to the low-potential DC power supply line is provided so as to absorb an AC voltage component superimposed on the low-potential DC power supply line. It is preferable to comprise a low-potential-side charge absorbing element and a low-potential-side charge absorbing circuit that causes the low-potential-side charge absorbing element to perform a charge absorbing operation according to a voltage change of the low-potential DC power supply line ( Claim 4). According to this configuration, the low-potential-side charge-absorbing circuit causes the low-potential-side charge-absorbing element to perform a charge-absorbing operation on the low-potential DC power supply line. Voltage components can also be suppressed.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention (corresponding to claims 1, 3 and 4) will be described below with reference to FIGS. In FIGS. 1 and 2, the same components as those in FIG. 12 are denoted by the same reference numerals, and in FIG. 3, the same components as those in FIG. 13 are denoted by the same reference numerals. explain.

FIG. 1 schematically shows the electrical configuration of the input / output circuit 18 as a block diagram. In FIG. 1, a large current output buffer circuit 2, an output protection circuit 4
A power line 6 (corresponding to a high-potential DC power line according to the present invention) and a power line common to the input protection circuit 5 (corresponding to the input circuit according to the present invention) and the input protection circuit 5 (corresponding to the input circuit according to the present invention). 7 (corresponding to the low-potential DC power supply line in the present invention), a power supply stabilizing circuit 19 (corresponding to the high-potential-side power stabilizing circuit in the present invention) is connected. This power stabilizing circuit 19
Is a capacitor 20 as a high potential side charge absorbing element,
And a charge / discharge circuit 21 (corresponding to a high-potential-side charge absorption circuit in the present invention) for performing a charge operation and a discharge operation for the capacitor 20.

FIG. 2 shows a specific electrical configuration of the input / output circuit 18 shown in FIG. In FIG. 2, between power supply lines 6 and 7, a source-drain of P-channel MOS transistor QP5 and a capacitor 20 are connected in series, and an N-channel MOS transistor is connected between both terminals of capacitor 20. The drain-source of QN5 is connected with the power supply line 7 as the source.

Between the power supply line 6 and the gate of the transistor QP5, the source-drain of the P-channel MOS transistor QP6 is connected, and the gate of the transistor QP6 is connected to the power supply line 7. An N-channel MOS is provided between the drain and the gate of the transistor QN5.
The drain-source of the transistor QN6 is connected,
The gate of the transistor QN6 is connected to the power supply line 6. Here, the transistors QP5 and QP6 constitute a charging circuit 22 in the charging / discharging circuit 21, and the transistors QN5 and QN6 constitute the charging / discharging circuit 21.
Of the discharge circuit 23 in FIG.

FIG. 3 shows a portion of the input protection circuit 5 in the layout of the input / output circuit 18 on the ASIC chip. A capacitor 20 is arranged and formed below the bonding pad 15. This capacitor 20 is formed by using a diffusion layer formed in a semiconductor substrate and a polysilicon film formed so as to face the diffusion layer via an insulating film as a counter electrode. The electrical connection is made to each of them. 13, transistors QP5 and QN6 forming the charging circuit 22 and transistors QN5 and QN6 forming the discharging circuit 23 are formed in a part of the area where the transistors QP4 and QN4 of the input protection circuit 5 are formed. Thus, the power supply stabilizing circuit 19 can be provided without increasing the chip area as compared with the conventional input / output circuit 1 and with a slight layout change.

Next, the operation of the present embodiment will be described with reference to FIG. When the output current of the large current output buffer circuit 2 is small, the ringing described later does not occur (or is small even if it occurs), so that the input buffer circuit 3 does not malfunction. However, when a load (not shown) through which a large current flows is connected to the bonding pad 14, the input terminal A of the large current output buffer circuit 2 is connected.
1, from H level (5 [V]) to L level (0 [V])
Is input, the input / output circuit 1
The voltage of each part 8 changes with vibration as shown in FIG. Here, the “voltage” is a potential difference based on the potential of the bonding pad 13, and the voltage of each part in FIG. 4 and the following description is the large current output buffer circuit 2, the input buffer circuit 3, A voltage at a point near the output protection circuit 4 and the input protection circuit 5 is arranged.

The voltage of the output line 8 changes from the L level to the H level with a delay of the propagation delay time of the large current output buffer circuit 2 (time t10). Undershoot (ringing) occurs. As described above, this ringing occurs due to the parasitic impedance Zb interposed in the power supply line 6, the parasitic impedance Ze interposed in the power supply line 7, the parasitic capacitances CfQP1, CfQP3, CfQN1, CfQN3, and the like. The amplitude tends to increase as the output current of the large current output buffer circuit 2 increases.

The ringing generated on the output line 8 propagates to the power supply line 6 through the parasitic capacitances CfQP1 and CfQP3, and propagates to the power supply line 7 through the parasitic capacitances CfQN1 and CfQN3. In this case, the voltage of the power supply line 6 becomes the time when the voltage of the output line 8 reaches 5 [V] from 0 [V] (time t11).
, An AC voltage component oscillating in substantially the same phase as the ringing of the output line 8 is superimposed. In addition, the voltage of the power supply line 7 is set at the time when the voltage of the output line 8 reaches 5 [V] from 0 [V] (time t).
Then, the AC voltage component which rises to 11) and oscillates in substantially the opposite phase to the ringing of the output line 8 is superimposed.

Now, at time t11, when the voltage of power supply line 6 sharply rises due to ringing, transistor QP
The source potential of No. 5 rises accordingly. On the other hand, the gate of the transistor QP5 is connected to the power supply line 6 via the source and the drain of the transistor QP6 functioning as a resistor. The gate potential of transistor QP5 rises later than the voltage rise of power supply line 6.
As a result, a positive voltage is applied between the gate and source of the transistor QP5, and the transistor QP5 is turned on from time t11 to time t12 when the gate-source voltage becomes equal to or lower than the threshold.

When the transistor QP5 is turned on, the charge causing the overshoot of the ringing on the power supply line 6 and the charge causing the undershoot of the ringing on the power supply line 7 are absorbed by the capacitor 20 through the transistor QP5 (the charging operation in the present invention). ), The amplitude of the ringing of the power supply lines 6 and 7 is reduced, and the time required for the attenuation is reduced. This charge absorption operation (charging operation) is performed in a state where no electric charge is stored in the capacitor 20 as described later, and therefore, compared to a circuit in which the capacitor 20 is simply connected between the power supply lines 6 and 7, for example. In addition, the charge absorbing effect of the capacitor 20 is large, and ringing can be more effectively suppressed. In FIG. 4, a ringing waveform appearing on the power supply line 6 of the input / output circuit 1 having a conventional configuration is indicated by a broken line.

The capacitor 2 is connected through the transistor QP5.
When the electric charge is accumulated at 0, the capacitor 20
, That is, the drain potential of the transistor QN5 sharply rises. At this time, the gate of the transistor QN5 near the ground potential is connected to its own drain via the drain-source of the transistor QN6 functioning as a resistor. Delayed, the gate potential of transistor QN5 rises later than the rise of its drain potential. As a result, a positive voltage is applied between the gate and source of the transistor QN5 after the elapse of the delay time,
The transistor QN5 turns on. This transistor QN
As for the timing at which the transistor 5 turns on, the respective constants are adjusted so as to be after time t12 when the transistor QP5 turns off in order to prevent a short circuit between the power supply lines 6 and 7. In FIG. 4, the transistor QN5 is turned on at time t12. When the transistor QN5 turns on, the capacitor 20
Is discharged, and the capacitor 20 is returned to the initial state where no charge is accumulated. When the discharge is substantially completed, the transistor QN5 automatically turns off because the gate bias is removed.

On the other hand, the ringing of the power supply lines 6 and 7 is transmitted to the input line 11 through the parasitic capacitances CfQP4 and CfQN4 of the transistors QP4 and QN4 of the input protection circuit 5. In this case, when the input line 11 is at the H level, the ringing of the power supply line 6 is transmitted to the input line 11 while maintaining substantially the same waveform, and when the input line 11 is at the L level, the ringing of the power supply line 7 is substantially The same waveform is held and propagated to the input line 11. However, since the ringing (AC voltage component) of the power supply lines 6 and 7 is suppressed by the charge absorbing action of the capacitor 20, the ringing transmitted to the input line 11 is also reduced. As a result, the voltage of the input line 11 is
(Equivalent to the input circuit in the present invention), the threshold voltage does not change, and malfunction due to inversion of the output signal S2 of the input buffer circuit 3 is prevented.

As described above, according to this embodiment, the capacitor 20 and the capacitor 20 are provided between the power supply line 6 (wiring 6a) and the power supply line 7 (wiring 7a) shared by the input circuit and the output circuit. Is characterized in that a power supply stabilizing circuit 19 composed of a charging circuit 22 and a discharging circuit 23 is provided. The power supply stabilizing circuit 19 can suppress ringing (AC voltage component) appearing on the power supply lines 6 and 7 due to the level inversion operation of the large current output buffer circuit 2 by the charge absorbing operation of the capacitor 20. The power supply stabilizing circuit 19 also has a noise suppression effect against noise that enters from outside through the bonding pads 12 and 13. Thereby, the parasitic capacitance CfQP is removed from the power supply lines 6 and 7.
4. Ringing (noise) transmitted to the input line 11 through the CfQN4 is reduced, and malfunction of the input buffer circuit 3 or other circuits connected to the power supply lines 6 and 7 can be prevented.

In this case, the charge absorbed by the capacitor 20 is discharged through the discharge circuit 23 after the charge absorption operation, so that the ringing absorption is started from an initial state in which no charge is accumulated in the capacitor 20. Will be. Therefore, the charge absorbing effect of the capacitor 20 is large, and the ringing (noise) is more effectively suppressed.

In the layout of the input / output circuit 18, since the capacitor 20 is formed using the lower layer of the bonding pad 15, a large capacitance can be obtained without increasing the chip area. Thereby, the charge absorbing effect of the capacitor 20 is further increased. Further, since the power supply stabilizing circuit 19 is formed in a part of the region where the transistors QP4 and QN4 are formed in the conventional input / output circuit 1, the input / output circuit 18 has a larger chip area than the conventional input / output circuit 1. There is no need to change the layout, and there is almost no need to change the layout. Therefore, an increase in design cost and product cost can be suppressed.

(Second Embodiment) Next, a second embodiment (corresponding to claims 1, 3 and 4) of the present invention will be described with reference to FIG. 5 with respect to parts different from the first embodiment. I do. In FIG. 5 showing the electrical configuration of the input / output circuit 24,
A power stabilizing circuit 25 (corresponding to a high-potential-side power stabilizing circuit in the present invention) is connected between the power lines 6 and 7.
The power supply stabilizing circuit 25 includes a power supply line 6 and a transistor QP.
2, a resistor 26 is connected instead of the transistor QP6 in FIG. 2, and a resistor 27 is connected between the drain and the gate of the transistor QN5 instead of the transistor QN6 in FIG. These resistors 26 and 2
7 is formed on the chip as a diffusion resistor or a thin film resistor. In this case, the transistor QP5 and the resistor 26
Form a charging circuit 28, and the transistor QN5
A discharge circuit 29 is constituted by the resistor 27 and the resistor 27. With the input / output circuit 24 having the above configuration, substantially the same operation and effect as those of the first embodiment can be obtained.

(Third Embodiment) Next, a third embodiment (corresponding to claims 1 and 2) of the present invention will be described with reference to FIG. 6 with respect to parts different from the first embodiment. FIG. 6 schematically shows an electrical configuration of the input / output circuit 30 as a block diagram. In FIG. 6, a power stabilizing circuit 31 (corresponding to the high-potential-side power stabilizing circuit in the present invention) is connected between the power lines 6 and 7. The power supply stabilizing circuit 31 includes a capacitor 20, a switch circuit 32 connected between the power supply line 6 and the capacitor 20 to form a charge charging path, and a switch connected between both terminals of the capacitor 20 to form a charge discharging path. Circuit 33, and a switch control circuit 3 for controlling these switch circuits 32, 33
4. As the switch circuits 32 and 33, for example, MOS transistors are used.

The switch control circuit 34 is not limited to a time constant circuit composed of a capacitor (including a gate capacitance) for generating timing and a resistor (including a case where a MOS transistor is used as a load element). 6, a digital logic circuit or an analog operation circuit (for example, a level detection circuit, a comparison circuit,
Circuit including timing adjustment circuit, switch drive circuit, etc.)
Can be configured as

According to the power stabilizing circuit 31 having the above configuration, the switch control circuit 34 constantly monitors the voltage of the power supply line 6 by inputting the voltage as a control signal. When the ringing is superimposed on the power supply line 6 due to the level inversion operation of the large current output buffer circuit 2 or the like, the switch control circuit 34 sets the timing at which the ringing can be most effectively suppressed, for example, when the voltage of the power supply line 6 becomes a predetermined value. During the overshoot exceeding the voltage (5 [V]), the switch circuit 32 is turned on, and the capacitor 20 absorbs the charge that causes the overshoot. Further, the switch control circuit 34 controls the switch circuit 33 to be turned on at an appropriate timing while the switch circuit 32 is turned off, and discharges the electric charge of the capacitor 20.

As described above, according to the present embodiment, the switch control circuit 34 drives the switch circuits 32 and 33 based on the voltage of the power supply line 6 input as the control signal, and transfers the charge to the capacitor 20. Since charging and discharging are controlled, it is possible to suppress AC voltage components such as ringing superimposed on the power supply line 6 and noise intruding from the outside. As a result, due to the parasitic capacitance in the input protection circuit 5, the input line 1
Ringing or the like propagated to 1 is reduced, and malfunction of the input buffer circuit 3 or other circuits connected to the power supply lines 6 and 7 can be prevented.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIGS.
7 and 8, the same components as those in FIGS. 2 and 3 are denoted by the same reference numerals, and different components will be described here.

FIG. 7 shows the electrical configuration of the input / output circuit 35. In FIG. 7, the power supply line 7 is connected to a power supply stabilization circuit 36 (corresponding to the low-potential-side power supply stabilization circuit in the present invention) configured as follows. That is, the power line 7
Is connected to one terminal of a capacitor 37 serving as a low-potential-side charge absorbing element. Between the other terminal of the capacitor 37 and the power supply line 7, between the drain-source of the N-channel MOS transistor QN7 and the N-channel MOS transistor Q
The drain-source of N8 is connected in series.
The gates of the transistors QN7 and QN8 are connected to the power supply line 7 and the power supply line 6, respectively. These transistors QN7 and QN8 constitute a charging circuit 38.

An N-channel MOS transistor QN9 is connected between the other terminal of the capacitor 37 and the power supply line 7.
Are connected between the drain and the source of the semiconductor device. Between the gate and source of this transistor QN9, the drain and source of N channel MOS transistor QN10 are connected,
The gate of transistor QN10 is connected to power supply line 6. These transistors QN9 and QN10 constitute a discharge circuit 39.

FIG. 8 shows a portion of the input protection circuit 5 in the layout of the input / output circuit 35 on the ASIC chip. In a part of the area where the transistor QN4 of the input protection circuit 5 is formed in FIG. 13, the transistors QN7 and QN8 forming the charging circuit 38 and the transistors QN9 and QN10 forming the discharging circuit 39 are provided.
The power stabilizing circuit 36 can be provided without increasing the chip area as compared with the conventional input / output circuit 1 and with a slight layout change.

Next, the operation of the present embodiment will be described with reference to FIG. FIG. 9 shows the components when the input signal S1 that changes from the L level to the H level is supplied to the input terminal A1 of the large current output buffer circuit 2 when the output current of the large current output buffer circuit 2 becomes a large current. 3 shows a voltage waveform.

The voltage of the output line 8 changes from the H level to the L level with a delay of the propagation delay time of the large current output buffer circuit 2 (time t20), and ringing occurs superimposed on it. The ringing generated on the output line 8 is transmitted to the power supply lines 6 and 7 through the parasitic capacitances CfQP1 and CfQP3 and CfQN1 and CfQN3. In this case, the voltage of the output line 8 is changed from 5 [V] to 0 [V] in the voltage of the power supply line 7.
(Time t21), the AC voltage component oscillating in substantially the same phase as the ringing of the output line 8 is superimposed. In addition, the voltage of the output line 8 is changed from 5 [V] to 0
An AC voltage component that falls until reaching [V] (time t21) and then oscillates in substantially the opposite phase to the ringing of the output line 8 is superimposed.

At time t21, when the voltage of the power supply line 7 sharply drops due to ringing, the transistor QN
The source potential of No. 9 falls in accordance with that voltage. On the other hand, since the gate of the transistor QN9 is connected to the power supply line 7 via the source and the drain of the transistor QN10 functioning as a resistor, the potential change is delayed by the amount of the gate capacitance, The gate potential falls later than the voltage drop of the power supply line 6. as a result,
A positive voltage is applied between the gate and the source of transistor QN9, and transistor QN9 is applied from time t21 to time t22 when the voltage between the gate and the source is equal to or lower than the threshold value.
9 turns on. When the transistor QN9 is turned on, the charge of the capacitor 37 is discharged, and the capacitor 37 is returned to the initial state.

Thereafter, when the voltage of the power supply line 7 starts to rise, the gate potential of the transistor QN7 rapidly rises in accordance with the voltage. On the other hand, transistor QN7
The source potential of the transistor QN7 rises later than the voltage rise of the power supply line 7, since the drain-source of the transistor QN8 functioning as a resistor is interposed between the source of the power supply line 7 and the power supply line 7. As a result, the transistor Q
A positive voltage is applied between the gate and source of N7 (time t23), and the transistor QN7 is turned on until time t24 when the gate-source voltage becomes equal to or lower than the threshold value. The timing at which this transistor QN7 turns on (time t2
3) In order to prevent a short circuit between the power supply lines 6 and 7,
Each constant is adjusted so as to be after time t22 when the transistor QN9 is turned off.

When transistor QN7 is turned on, the charge causing overshoot of ringing in power supply line 7 is absorbed by capacitor 37, so that ringing after time t23 is alleviated. As a result, the parasitic capacitance CfQP
4. Ringing propagated to the input line 11 through CfQN4 is also reduced, and malfunction of the input buffer circuit 3 is prevented. In FIG. 9, ringing waveforms appearing on the power supply line 7 and the input line 11 of the input / output circuit 1 having a conventional configuration are indicated by broken lines.

As described above, according to this embodiment, the power supply line 7 (wiring 7a) is provided with the power supply stabilizing circuit 36 composed of the capacitor 37 and the charging circuit 38 and the discharging circuit 39 of the capacitor 37. It is characterized by points. As a result, ringing (including noise invading from the outside), which is an AC voltage component appearing on the power supply line 7, can be suppressed by the charge absorption operation of the capacitor 37, and other components connected to the input buffer circuit 3 or the power supply line 7 Malfunction of the circuit can be prevented. In this case, the ringing absorption is started from an initial state in which no electric charge is stored in the capacitor 37, so that the effect of suppressing the ringing is further enhanced. Further, similarly to the first embodiment, there is no increase in chip area and no significant change in layout is required, so that an increase in cost can be suppressed.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described with reference to FIG. 10 for differences from the fourth embodiment. In FIG. 10 showing the electrical configuration of the input / output circuit 40, a power supply stabilization circuit 40 (corresponding to the low-potential-side power supply stabilization circuit in the present invention) configured as follows is connected to the power supply line 7. That is, a resistor 42 is connected between the source of the transistor QN7 and the power supply line 7 instead of the transistor QN8 in FIG. 7, and a resistor 43 is connected between the gate and source of the transistor QN9 instead of the transistor QN10 in FIG. Have been. These resistors 42 and 43 are formed as diffusion resistors and thin-film resistors on the chip. In this case, a charging circuit 44 is formed by the transistor QN7 and the resistor 42, and a discharging circuit 4 is formed by the transistor QN9 and the resistor 43.
5 are configured. Input / output circuit 40 having the above configuration
With this configuration, substantially the same operation and effect as those of the fourth embodiment can be obtained.

(Sixth Embodiment) Next, a sixth embodiment (corresponding to claim 5) of the present invention will be described with reference to FIG. 11 with respect to portions different from the first or fourth embodiment. . In FIG. 11 showing the electrical configuration of the input / output circuit 46, the power supply stabilization circuit 19 shown in FIG. 2 is connected between the power supply lines 6 and 7, and the power supply stabilization circuit shown in FIG. 36 are connected. In this case, although not shown, the capacitor 37 is formed below the bonding pad 14. In addition, in a part of the region where the transistors QP4 and QN4 of the input protection circuit 5 are formed in FIG.
QP6, QN5, QN6 and transistors QN7, QN8, QN9, QN10 constituting the power supply stabilizing circuit 33 are formed, and it is not necessary to increase the chip area or change the layout as compared with the conventional input / output circuit 1. .

According to the input / output circuit 46 having the above configuration, the power supply stabilizing circuit 19 acts on ringing (noise) appearing on the power supply line 6 due to the level inversion operation of the large current output buffer circuit 2 and the like. The power supply stabilizing circuit 36 acts on the ringing (noise) appearing at 7. As a result, the same operation and effect as those of the first embodiment and the same operation and effect as those of the fourth embodiment can be obtained, and the malfunction of the input / output circuit 46 is further reduced and the reliability thereof is further improved.

(Other Embodiments) The present invention is not limited to the embodiments described above and shown in the drawings, and the following expansions or modifications are possible. In the layout of each embodiment, the capacitor 20 or 37 may be provided in a lower layer of the bonding pad different from the bonding pad 15, or a capacitor formed in a lower layer of two or more bonding pads may be connected in parallel. . Transistor QP Constituting Power Supply Stabilizing Circuit 19
5, QP6, QN5, QN6, and transistors QN7, QN8, QN9, QN10 forming the power stabilizing circuit 36
Is formed in a part of the area where the transistors QP4 and QN4 of the input protection circuit 5 are formed, but is formed in a part of the area where the transistors QP3 and QN3 of the output protection circuit 4 are formed. Is also good.

[0058]

Since the present invention is as described above,
The following effects are obtained. According to the input / output circuit of claims 1 to 3, the high-potential-side power stabilizing circuit including the high-potential-side charge absorbing element and the high-potential-side charge absorbing circuit is provided between the high-potential and low-potential DC power supply lines. The high-potential-side charge absorbing element performs an operation of absorbing a charge corresponding to the AC voltage component on the high-potential DC power supply line, and suppresses the AC voltage component. This allows
The voltage of the high-potential DC power supply line is stabilized, and malfunction of the output circuit can be prevented.

According to the input / output circuit of the fourth aspect, the input circuit and the output circuit are each formed with a protection circuit portion, and the high potential side charge absorption circuit is formed in a part of the region where the protection circuit portion is formed. Therefore, the malfunction of the output circuit can be prevented without increasing the chip area and without substantially changing the conventional circuit layout. Also, since the capacitor is formed under the bonding pad provided on the semiconductor substrate, a large capacitance can be secured without increasing the chip area, and the malfunction of the output circuit can be more reliably prevented. Can be.

According to the input / output circuit of the fifth aspect, the low-potential-side power supply stabilizing circuit connected to the low-potential DC power supply line and including the low-potential-side charge absorbing element and the low-potential-side charge absorbing circuit is provided. The potential-side charge absorbing element absorbs the charge corresponding to the AC voltage component on the low-potential DC power supply line, and suppresses the AC voltage component. Thus, the voltage of the low-potential DC power supply line is stabilized, and malfunction of the output circuit can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram of an input / output circuit according to a first embodiment of the present invention.

FIG. 2 is an electrical configuration diagram of an input / output circuit;

FIG. 3 is a diagram showing a part of a layout of an input / output circuit on a semiconductor substrate;

FIG. 4 is a voltage waveform diagram of each part when the output voltage of the large current output buffer circuit changes.

FIG. 5 is a view corresponding to FIG. 2, showing a second embodiment.

FIG. 6 is a view corresponding to FIG. 1, showing a third embodiment;

FIG. 7 is a view corresponding to FIG. 2, showing a fourth embodiment;

FIG. 8 is a diagram corresponding to FIG. 3;

FIG. 9 is a diagram corresponding to FIG. 4;

FIG. 10 is a view corresponding to FIG. 2, showing a fifth embodiment;

FIG. 11 is a view corresponding to FIG. 2, showing a sixth embodiment;

FIG. 12 is a diagram corresponding to FIG. 2, showing a conventional configuration.

FIG. 13 is a diagram corresponding to FIG. 3;

FIG. 14 is a diagram corresponding to FIG. 4;

[Description of Signs] 2 is a large current output buffer circuit (output circuit), 3 is an input buffer circuit (input circuit), 4 is an output protection circuit (output circuit), 5 is an input protection circuit (input circuit), and 6 is a power supply. Line (high-potential DC power line), 7 is a power line (low-potential DC power line),
18, 24, 30, 35, 40 and 46 are input / output circuits,
Reference numerals 9, 25 and 31 denote a power stabilizing circuit (high-potential-side power stabilizing circuit), 20 denotes a capacitor (high-potential-side charge absorbing element),
1 is a charge / discharge circuit (high-potential side charge absorption circuit), 22, 2
8, 38 and 44 are charging circuits, 23, 29, 39 and 45 are discharging circuits, 32 is a switching circuit (first switching circuit), 33 is a switching circuit (second switching circuit), 3
4 is a switch control circuit, 36 and 41 are power stabilizing circuits (low-potential-side power stabilizing circuits), and 37 is a capacitor (low-potential-side charge absorbing element).

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Yoshiya 25-1 Ekimae Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa F-term (reference) 5J032 AA05 AB11 AC16 5J055 AX25 AX41 AX44 AX59 AX63 BX05 BX16 CX02 DX22 DX48 EX07 EX16 EY01 EY10 EZ01 EZ05 EZ22 FX19 FX27 FX28 FX37 GX01 GX05 GX08 5J056 AA01 AA04 BB22 CC03 CC19 CC20 DD13 DD29 DD51 DD52 DD54 FF08 GG09 HH03 KK01 5J090 AA01 AA45 CA04 HA01 HA03 HA04 HA01 HA03 HA04

Claims (5)

[Claims] An input / output circuit formed on a semiconductor substrate and provided with an input circuit and an output circuit supplied from a pair of high-potential and low-potential DC power supply lines, wherein the input / output circuit is superimposed on the high-potential DC power supply line. A high-potential-side power stabilizing circuit is provided between the pair of DC power supply lines so as to absorb the AC voltage component, and the high-potential-side power stabilizing circuit is provided with a high-potential-side charge absorbing element and a high-potential-side charge absorbing element. On the other hand, an input / output circuit comprising a high-potential-side charge absorption circuit for performing a charge absorption operation in accordance with a voltage change of the high-potential DC power supply line. 2. A high-potential-side power supply stabilizing circuit, comprising: a capacitor provided as a high-potential-side charge absorbing element; and a first switch circuit provided as a high-potential-side charge absorbing circuit and forming a charging path for the capacitor. And a second switch circuit forming a discharge path, and a switch control circuit controlling a switching operation of the first and second switch circuits according to a voltage change of a high-potential DC power supply line. The input / output circuit according to claim 1, wherein 3. A high-potential-side power supply stabilizing circuit, comprising: a capacitor provided as a high-potential-side charge absorbing element; a charging circuit provided as a high-potential-side charge absorbing circuit; 2. The input / output circuit according to claim 1, further comprising a discharge circuit for performing the following. 4. A protection circuit section is formed in each of the input circuit and the output circuit, a high-potential-side charge absorption circuit is formed in a part of a region where the protection circuit section is formed, and a capacitor is provided on a semiconductor substrate. 4. The input / output circuit according to claim 2, wherein the input / output circuit is formed in a lower layer of the provided bonding pad. 5. A low-potential power supply stabilizing circuit connected to the low-potential DC power supply line so as to absorb an AC voltage component superimposed on the low-potential DC power supply line; A low-potential-side charge-absorbing element, and a low-potential-side charge-absorbing circuit for performing a charge-absorbing operation on the low-potential-side charge-absorbing element in accordance with a voltage change of the low-potential DC power supply line. Claim 1
Input / output circuit as described.