JP2000277405A - Method for producing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To produce a semiconductor device using a SiC wafer having relatively a large diameter. SOLUTION: A semiconductor substrate 10 is formed by mounting second Sic wafers 1, 2, which have a 2-inch diameter disc shape each and are bonded together, on the central part of one end of a first Sic wafer 11 having a 4-inch diameter disc shape. By moving the second wafer 12 on the first wafer 11, the second wafer 12 can be processed by various types of processing devices as a part of the semiconductor substrate 10. To bond the first wafer 11 and the second wafer 12 together, each surface of the first wafer 11 and the second wafer 12 are required to be processed to get mirror condition. After forming a silicon oxide film is formed respectively on each bonded surface of the two wafers, each silicon oxide film of the first wafer 11 and the second wafer 12 can be bonded by being pasted together and heated. Each orientation flat direction of the first wafer 11 and the second wafer 12 is required to be the same direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device using silicon carbide crystal (SiC).

[0002]

2. Description of the Related Art Power conversion, which is the basis of power electronics, largely depends on the performance of a power device (power semiconductor element) having a switching function. The main characteristics required for a power device include four characteristics: withstand voltage, low steady-state loss, fast switching and low switching loss, and ease of control. In power devices, studies have been made to make each of the above-mentioned characteristics close to the ideal.

As a main element of a power device,
There is a so-called self-extinguishing element capable of controlling large power on / off by a gate signal, and includes a power transistor, a gate turn-off thyristor (hereinafter, referred to as GTO thyristor), and an insulated gate bipolar transistor (hereinafter, referred to as IGBT) ), Electrostatic induction thyristor (S
Self-extinguishing elements such as ITh (hereinafter referred to as SI thyristors) have been developed. For example, in the case of a GTO thyristor having the highest withstand voltage and large current among the self-extinguishing elements, 8 k
V / 6 kA class devices have been developed.

However, in the above device, 8 kV / 6 k
It is considered that it is difficult to increase the breakdown voltage and increase the current to a level higher than the class A due to the physical limit of silicon (Si) as a semiconductor material. Further, in the case of an element having a high withstand voltage and a large current, such as a GTO thyristor, the operation becomes a bipolar operation in order to suppress an increase in the steady-state loss, and it has been difficult to increase the frequency.

[0005] In recent years, power devices using silicon carbide (SiC) crystals, which are several orders of magnitude better in physical properties as semiconductors than Si, have been spotlighted. SiC
In the application of power devices to power devices, Baliga of North Carolina State University proposed a performance index for high-voltage devices in 1982 and a performance index for high-frequency / low-voltage devices in 1989. Most attention has been paid to device materials. Si
The performance index of power devices using C is 2-3 orders of magnitude better than commonly known power devices using Si or GaAs, and can be realized in the future with current advanced simulation technology. The characteristics of such devices are gradually being elucidated.

[0006]

The biggest obstacle in producing a power device using SiC is that a wafer having a large diameter and good crystallinity does not exist at present. On the other hand, when producing a crystal of Si, high purity, high crystallinity, and a crystal having a large diameter can be relatively easily obtained by a technique of melting the Si at a high temperature.

However, in the case of producing the SiC crystal, since the SiC cannot be melted (because there is no liquid phase), the technique of melting at a high temperature cannot be used, and the sublimation method is used. There is no other way to make crystals. That is, it is difficult to obtain a high-purity crystal because zone refining using a liquid phase cannot be used, there are more than 200 crystal types in SiC, (Necessary nuclei) by using the crystal orientation in (crystal growth using a specific crystal plane) other than the reason that the crystal can not be grown large by other methods,
It is extremely difficult to produce a large diameter SiC wafer such as a Si wafer.

In order to solve the above-mentioned problems, various technical developments are being made energetically around the world. As of 1998, the diameter of a commercially available SiC single crystal wafer is only about 2 inches. It is. At present, state-of-the-art manufacturing equipment such as microfabrication equipment used for Si semiconductor devices
In order to use the SiC wafer, the diameter of the SiC wafer needs to be at least 4 inches or more, preferably 6 inches or more. However, in view of the current technology level, it will not be possible to reach a technology level capable of manufacturing a SiC wafer having a diameter of 4 inches or more as described above unless a very innovative invention is made. It is expected to be.

The present invention has been made on the basis of the above-mentioned problems, and provides a SiC wafer on a Si wafer to form a semiconductor substrate. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of processing a SiC wafer and achieving a high breakdown voltage and a large current.

[0010]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device obtained by processing a semiconductor substrate formed of a wafer such as Si. The substrate is made of a disc-shaped, relatively small-diameter (for example, 2 inches) SiC single crystal with respect to one end surface of a disc-shaped first wafer (for example, a Si wafer) having a diameter of 4 inches or more. Characterized in that a second wafer is provided.

A second invention is characterized in that, in the first invention, the semiconductor substrate is formed by bonding and bonding one end surface of the first wafer and one end surface of the second wafer.

A third invention is characterized in that in the first or second invention, a wafer made of a Si single crystal is used as the first wafer.

[0013] A fourth invention is the above-mentioned first to third inventions, wherein:
The second wafer is manufactured by a CVD method or a sintering method.

According to a fifth aspect, in the first to fourth aspects,
The first wafer and the second wafer are bonded using solder as a brazing material.

In a sixth aspect, in the first to fourth aspects,
After forming an oxide film on each bonding surface of the first wafer and the second wafer by a thermal oxidation method or a CVD method, the first wafer and the second wafer are bonded and heat-treated. Features.

According to a seventh aspect, in the first to sixth aspects,
An orientation flat direction, which is a reference of each crystal orientation of the first wafer and the second wafer, is set to the same direction.

According to an eighth aspect, in the first to seventh aspects,
After previously forming one or more holes having the same shape as the second wafer and capable of fitting the second wafer to one end surface of the first wafer, the second wafer is The semiconductor substrate is formed by being fitted in a hole.

In a ninth aspect based on the eighth aspect, the hole is formed to be deeper than the thickness of the second wafer in advance, and the second wafer is fitted into the deeply formed hole. Features.

According to a tenth aspect, in the ninth aspect, after the second wafer is fitted into the hole, one end surface of the first wafer on the side where the second wafer is fitted is surface-polished to thereby provide the semiconductor. The thickness of the portion of the substrate where the second wafer is fitted is the same as the thickness of the portion of the semiconductor substrate where the second wafer is not fitted.

According to an eleventh aspect, in the first to tenth aspects, after using a Si single crystal wafer as the first wafer, providing the second wafer on the first wafer and forming the semiconductor substrate, The semiconductor device is formed by processing a portion of the semiconductor substrate where the second wafer is provided, and the semiconductor device is formed by processing a portion of the semiconductor substrate where the second wafer is not provided. .

According to a twelfth aspect, in the first to eleventh aspects, a plurality of the second wafers are provided for the first wafer.

According to a thirteenth aspect, in the twelfth aspect,
The second wafer is processed in advance to form rectangular (square, rectangular, quadrilateral, etc.) chips, and a plurality of chips are provided for the first wafer.

[0023]

Embodiments of the present invention will be described below. In the first to fourth embodiments of the present invention, in a single crystal wafer having a relatively small diameter made of existing SiC,
This is a study of a method of manufacturing a semiconductor device which is processed by a manufacturing device such as a microfabrication device used in an i-semiconductor device to achieve a high breakdown voltage and a large current. That is,
An existing SiC single crystal wafer (hereinafter, referred to as a second wafer; hereinafter, referred to as a second wafer; shaded portion in FIGS. 1 to 5) is bonded to an existing wafer, such as a large diameter Si wafer (hereinafter, referred to as a first wafer). The present invention has been studied so that the second wafer can be processed as a part of the semiconductor substrate by forming the semiconductor substrate by the method.

(First Embodiment) FIGS. 1A (plan view), B
(Cross-sectional view) shows a schematic configuration diagram of a semiconductor substrate provided with the second wafer in the first embodiment. 1A and 1B, reference numeral 11 denotes a disk-shaped first wafer having a relatively large diameter (4 inches in diameter), and reference numeral 11a is formed on a part of the outer peripheral portion of the first wafer 11. 3 shows an orientation flat. At the center of one end face of the first wafer 11, a disc-shaped second wafer 12 made of SiC and having a relatively small diameter (diameter is 2 inches) is provided by bonding to form a semiconductor substrate 10. Reference numeral 12a indicates an orientation flat formed on a part of the outer peripheral portion of the second wafer 12.

By providing the second wafer 12 on the first wafer 11 as described above, the second wafer 12 can be processed by various processing apparatuses as a part of the semiconductor substrate 10 having a diameter of 4 inches. Becomes The first wafer 11
It is preferable to use an inexpensive general-purpose Si wafer as the material. When the coefficient of thermal expansion between the first wafer 11 and the second wafer 12 is precisely controlled, CV
Alternatively, a SiC wafer (having a large diameter but having poor crystallinity and cannot be used as a semiconductor substrate) manufactured by the method D (chemical vapor deposition) may be used.

The first wafer 11 and the second wafer 12 can be bonded using solder. But,
Among manufacturing apparatuses for semiconductor devices, there are manufacturing apparatuses that require a processing temperature exceeding the melting point of solder, such as CVD apparatuses, so that a problem occurs in the bonding method using the solder. Therefore, a bonding method using a method of SDB (Silicon Direct Bonding), which is generally used for manufacturing an SOI substrate using Si, can be considered.

In order to bond the first wafer 11 and the second wafer 12 by the bonding method applying the above-mentioned SDB method, first, each bonding surface of the first wafer 11 and the second wafer 12 is processed (mirror surface). Treatment) to make mirror-like, thermal oxidation method or C
After forming the Si oxide films on the respective bonding surfaces by the VD method, the respective Si oxide films of the first wafer 11 and the second wafer 12 can be bonded to each other by laminating and heat-treating each other. .

By bonding the first wafer 11 and the second wafer 12 as described above, the first wafer 11 and the second wafer 12 do not peel off up to 1300 ° C. Can be used. The semiconductor substrate 1
0 is formed so that the orientation flat directions, which are the references for the respective crystal orientations of the first wafer 11 and the second wafer 12 in the semiconductor substrate 10, are the same.

(Second Embodiment) FIGS. 2A (plan view), B
(Cross-sectional view) shows a schematic configuration diagram of a semiconductor substrate provided with a second wafer according to the second embodiment. The same components as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. In FIG.
1 has the same shape as the second wafer 12, and the second wafer 1
2 shows a hole (dent) into which 2 can be fitted,
One end surface of the first wafer 11 is formed at the center. The hole 2
1 denotes the first wafer 11 by trench etching or the like.
Can be formed by etching the central part of one end face of. The second wafer 12 is inserted into the hole 21 of the first wafer 11.
The semiconductor substrate 20 is formed by fitting and bonding.

Semiconductor substrate 10 shown in the first embodiment
In the case of (1), the position of the bonding position of the second wafer 12 with respect to the first wafer 11 is determined by using a jig or the like for preventing a displacement that occurs when the second wafer 12 is bonded with the first wafer 11. There is a need. On the other hand, in the case of the semiconductor substrate 20 of the second embodiment, since the second wafer 12 is positioned by the holes 21 of the first wafer 11, a jig or the like for preventing displacement is used as described above. No need.

Further, as shown in FIG.
In the outer peripheral portion (the outer peripheral portion of the first wafer 11) and the thickness of the central portion (the portion where the second wafer 12 is fitted) can be made uniform (the same), so that the semiconductor in the photolithography process High precision processing of the substrate 20 becomes possible. Further, the focus of the first wafer 11 and the second wafer 12 in the photolithography process become the same. Therefore, by using a wafer made of a Si single crystal (hereinafter, referred to as a Si single crystal wafer) as the first wafer 11, a semiconductor element is formed on the second wafer and a semiconductor is formed on the Si single crystal wafer at the same time. An element can be formed, and the first wafer 11 can be effectively used.

FIGS. 3A (adhesion step) and B (polishing step) are explanatory views of a specific example in which the thickness of the outer peripheral portion and the thickness of the central portion of the semiconductor substrate 20 are made equal. Note that the same components as those shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. FIG. 3A shows a bonding step, in which the center of one end surface of the first wafer 11 is etched in advance to form a hole 31 having a diameter similar to the hole 21 and deeper than the hole 21.

The center portion of the semiconductor substrate 20 is formed to be slightly thinner than the outer peripheral portion of the semiconductor substrate 20 by fitting and bonding the second wafer 12 to the hole 31. Thereafter, in a polishing step shown in FIG. 3B, an outer peripheral portion (first
By polishing (surface polishing) a portion of the one end surface of the wafer 11 where the second wafer 12 is not fitted, the thickness of the outer peripheral portion and the thickness of the central portion of the semiconductor substrate 20 are made equal.

For example, when the thickness of the outer peripheral portion of the semiconductor substrate 20 is smaller than the thickness of the central portion of the semiconductor substrate 20, the second wafer 12 is hard (SiC is extremely hard), and thus the polishing step is performed. Polishing efficiency is lowered. On the other hand, by using a material such as Si that is softer than SiC as the first wafer 11 as in the present embodiment, when the thickness of the outer peripheral portion and the thickness of the central portion of the first wafer 11 become the same, Since the polishing rate is rapidly reduced, the end point of the polishing step can be easily detected, and the polishing efficiency increases.

(Third Embodiment) FIG. 4 shows a third embodiment of the present invention.
FIG. 2 is a schematic configuration diagram of a semiconductor substrate provided with a second wafer in the embodiment. Note that the same components as those shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. In FIG. 4, reference numeral 41 denotes a disk-shaped first wafer having a relatively large diameter (8 inches in diameter), and reference numeral 41a denotes an orientation formed on a part of the outer peripheral portion of the first wafer 41. It shows a flat.

Reference numeral 42 denotes a hole (dent) 42 having a shape similar to that of the second wafer 12 and in which the second wafer 12 can be fitted. A plurality (four in FIG. 4) are formed at equal intervals. The semiconductor substrate 40 is formed by fitting and bonding the second wafer 12 to each hole 42 of the first wafer 41. As shown in FIG.
By forming 0, a plurality of second wafers 12 can be processed.

(Fourth Embodiment) FIG. 5 shows a fourth embodiment of the present invention.
FIG. 2 is a schematic configuration diagram of a semiconductor substrate provided with a second wafer in the embodiment. The same components as those shown in FIG. 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. In FIG. 5, reference numeral 51 denotes a rectangular hole (recess) having a shape similar to that of a chip 52 to be described later and into which the chip 52 can be fitted. There are a plurality (17 in FIG. 5) formed at equal intervals on one end surface of the first wafer 41. Reference numeral 52 denotes a rectangular (square, rectangular, quadrilateral, etc.) chip obtained by processing a disk-shaped SiC wafer. The semiconductor substrate 50 is formed by fitting and bonding the holes 51 respectively.

By forming the semiconductor substrate 50 as shown in FIG. 5, since the shape of the chip 52 is rectangular, the chip 52 is formed between the adjacent second wafers 12 in the semiconductor substrate 40 as shown in FIG. The area between the adjacent chips 52 in the semiconductor substrate 50 can be reduced as compared with the area. Therefore, the first wafer 51
, More chips 52 can be provided,
The utilization rate of the chips 52 with respect to the first wafer 51 can be increased.

Each of the chips 52 is a disk-shaped S
Since the iC wafer is formed by cutting off the outer peripheral portion, the usage rate of the SiC wafer is reduced by the cutout. However, generally known disk-shaped S
Since there are many fatal crystal defects called micropipes in the outer peripheral portion (about half the area of the whole wafer) of the iC wafer, the cut-off portion is an unnecessary portion from the beginning.

[0040]

As described above, according to the present invention, Si
In the processing of the C wafer, it is possible to use a manufacturing apparatus (fine processing apparatus) for a Si semiconductor element using a wafer having a relatively large diameter. Si with high breakdown voltage and large current)
A C semiconductor device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor substrate according to a first embodiment.

FIG. 2 is a schematic configuration diagram of a semiconductor substrate according to a second embodiment.

FIG. 3 is an explanatory view (example) of a bonding step and a polishing step in a second embodiment of the present invention.

FIG. 4 is a schematic configuration diagram of a semiconductor substrate according to a third embodiment.

FIG. 5 is a schematic configuration diagram of a semiconductor substrate according to a fourth embodiment.

[Explanation of symbols]

 10, 20, 40, 50 ... semiconductor substrate 11, 41 ... first wafer 11a, 12a, 41a ... orientation flat 12 ... second wafer 21, 31, 42, 51 ... hole 52 ... chip

Claims (13)

[Claims] 1. A method of manufacturing a semiconductor device obtained by processing a semiconductor substrate formed of a wafer of Si or the like, wherein the semiconductor substrate has a disk-shaped first shape having a diameter of 4 inches or more.
The disk is relatively small in diameter and S
A method for manufacturing a semiconductor device, comprising providing a second wafer made of an iC single crystal. 2. The method according to claim 1, wherein the semiconductor substrate is formed by bonding and bonding one end surface of the first wafer and one end surface of the second wafer. 3. The wafer according to claim 1, wherein a wafer made of a single crystal of Si is used as the first wafer.
A method for manufacturing a semiconductor device as described in the above. 4. The method according to claim 1, wherein the second wafer is manufactured by a CVD method or a sintering method. 5. The method according to claim 1, wherein the first wafer and the second wafer are bonded by using solder as a brazing material. 6. An oxide film is formed on each bonding surface of the first wafer and the second wafer by a thermal oxidation method or a CVD method, and then the first wafer and the second wafer are bonded and heat-treated. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is bonded by bonding. 7. An orientation flat direction serving as a reference for each crystal orientation of the first wafer and the second wafer,
7. The device according to claim 1, wherein the respective directions are the same.
A method for manufacturing a semiconductor device as described in the above. 8. One or more holes having the same shape as the second wafer and capable of fitting the second wafer are formed in advance on one end surface of the first wafer. 8. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is formed by fitting a wafer into each of the holes. 9. The method according to claim 8, wherein the hole is formed deeper than the thickness of the second wafer in advance, and the second wafer is fitted into the deeply formed hole.
A method for manufacturing a semiconductor device as described in the above. 10. After fitting the second wafer into the hole,
By polishing one end surface of the first wafer on the side where the second wafer is fitted, the thickness of the portion of the semiconductor substrate where the second wafer is fitted and the second wafer of the semiconductor substrate are fitted. 10. The method for manufacturing a semiconductor device according to claim 9, wherein the thickness of the non-existing portion is the same. 11. A method according to claim 1, further comprising using a Si single crystal wafer as the first wafer, providing the second wafer on the first wafer to form the semiconductor substrate, and then providing a second wafer in the semiconductor substrate. 11. The manufacturing of a semiconductor device according to claim 1, wherein a portion is processed to form a semiconductor element, and a portion of the semiconductor substrate on which the second wafer is not provided is processed to form a semiconductor element. Method. 12. The method according to claim 1, wherein a plurality of said second wafers are provided for said first wafer. 13. The manufacturing of a semiconductor device according to claim 12, wherein a rectangular chip is formed by processing the second wafer in advance, and a plurality of chips are provided for the first wafer. Method.