JP2000277699A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor integrated circuit with a high operation rate, while dispensing with complicated manufacturing processes. SOLUTION: A plurality of sets of power supply units A (B), composed of functional structure parts 11 (21), P-channel transistor drive capability switching parts 12 (22), P-channel transistor drive parts 13 (23), N-channel transistor drive capability switching parts 14 (24) and N-channel transistor drive parts 15 (25) are mounted. The power supply interface units A and B are constituted mutually buffering of bidirectionally.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a multi-power supply interface.

[0002]

2. Description of the Related Art The logic inside a semiconductor integrated circuit chip is implemented by an FPGA (Field Programmable G).
In the case of a single-gate gate array or a one-mask gate array, when a semiconductor integrated circuit having a multi-power supply interface is created without restricting the terminal arrangement, a buffer is created so that the maximum voltage has a withstand voltage.
The power supply voltage was changed according to the power supply of the interface.

FIG. 3 shows a single power supply interface section C constituting a conventional interface buffer. The single power supply interface unit includes a function configuration unit 41 and a P
A channel transistor drive capacity switching unit 42;
It comprises a channel transistor drive section 43, an N-channel transistor drive capability switching section 44, and an N-channel transistor drive section 45.

[0004]

However, when an interface buffer for multiple power supplies is created by using a single power supply interface section as described above, the withstand voltage must be matched to the maximum voltage power supply among the multiple power supplies as described above. .
In this interface buffer, if it is driven by another power supply, it will be used at a voltage lower than the maximum voltage, but in such a case, the rise and fall of the voltage waveform will be very slow, and the operating speed will be slowed down There was a problem.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit having a high operation speed without going through a complicated manufacturing process.

[0006]

According to the present invention, there is provided a semiconductor integrated circuit comprising a functional component, a P-channel transistor driving capability switching unit, a P-channel transistor driving unit, and an N-channel transistor driving capability switching unit.
One multi-power interface unit is configured by mounting a plurality of power interface units each including an N-channel transistor drive unit, and the plurality of power interface units can be bidirectionally buffered. Features.

[0007] Thus, even if a P-channel transistor drive section and an N-channel transistor drive section having different power supply voltages are provided, a multi-power supply interface buffer can be freely configured and arranged.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor integrated circuit according to the present invention will be described below with reference to FIGS.

FIG. 1 is a diagram showing a configuration of a dual power supply interface buffer according to an embodiment of the present invention. The dual power supply interface buffer according to the present embodiment includes a first power supply interface unit A and a second power supply interface unit B. Each of these power supply interface units includes a functional configuration unit 11, 21 and a P-channel transistor driving capability switching unit. 12 and 22, P-channel transistor driving units 13 and 23, N-channel transistor driving capability switching units 14 and 24, and N-channel transistor driving units 15 and 25.

The functional components 11, 21 are composed of FPGA or one mask gate array. The functional components 11 and 21 are configured such that a bidirectional buffer is possible.

The P-channel transistor drive capacity switching sections 12 and 22 are connected by final metal wiring so as to disable or enable an input signal of a transistor to be used in accordance with a target drive capacity.

P-channel transistor driving units 13, 2
Reference numeral 3 has a wiring and a drain wiring which pass through these driving units from a PAD (not shown). When used as a P-type transistor, the drain wiring is connected to the PAD with a final metal. When not used as a P-type transistor, the through hole in the drain portion is covered with a final metal wiring, and no wiring is provided.

The N-channel transistor drive capacity switching units 14 and 24 are connected with final metal wiring so as to disable or enable an input signal of a transistor to be used in accordance with a target drive capacity.

N-channel transistor driving units 15, 2
Reference numeral 5 has a wiring and a drain wiring that pass through the driving section from the PAD. When used as an N-type transistor, the drain wiring is connected to the PAD with the final metal.
When not used as an N-type transistor, the through hole in the drain portion is covered with the final metal wiring, and no wiring is provided.

Next, a circuit pattern of the dual power supply interface buffer according to the above embodiment will be described with reference to FIG.

FIG. 2 is a plan view showing the driving capability switching unit 12 and the driving unit 13 when the interface buffer is constituted by two layers (the first metal wiring and the second metal wiring) and used as a P-channel transistor. It is. Note that the same configuration is used when the transistor is used as an N-channel transistor. In this drawing, reference numeral 31 denotes a portion where the first metal wiring and the second metal wiring are connected by a through hole, and reference numeral 32 denotes a contact between either the gate or the drain of each transistor and the first metal wiring and the second metal wiring. Reference numeral 33 denotes a portion where the source of each transistor and the first metal wiring are connected by a contact. The hatched portion indicates a second metal wiring which is the final metal wiring in the present embodiment.

The gate 34 of the transistor of the driving unit is controlled by a disable signal 35 or an enable signal 36 which is controlled by a functional component (not shown). The source of the transistor of the drive unit is connected to the power supply 37 of the first metal wiring by a contact.
The drain of the transistor of the drive unit is connected to a PAD (not shown) of the second metal wiring by a contact and a through hole.

As described above, by appropriately connecting the second metal wiring at the stage of finishing the semiconductor integrated circuit,
The functional component, the P-channel transistor driving capability switching unit, the P-channel transistor driving unit, the N-channel transistor driving capability switching unit, and the N-channel transistor driving unit are connected to each other, so that a desired power supply voltage interface can be realized.

[0019]

As described above, according to the semiconductor integrated circuit of the present invention, the functional component, the P-channel transistor driving capability switching unit, the P-channel transistor driving unit, and the N-channel transistor driving capability switching unit And a plurality of power supply interface sections each including an N-channel transistor drive section, thereby forming one multi-power supply interface section. The plurality of power supply interface sections can be bidirectionally buffered. It has a configuration.

Thus, even when driven by different power supply voltages, the multi-power supply interface buffer can be freely configured and arranged without suppressing the delay of the rise and fall of the voltage waveform. Therefore, an FPGA having a multiple power supply interface or one mask gate array can be easily created, so that the time required for completing the product can be reduced and the logic can be easily changed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a two-power interface according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a circuit pattern of a dual power interface according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration of a conventional single power supply interface.

[Explanation of symbols]

A first power supply interface section B second power supply interface section 11, 21 function component section 12, 22 P-channel transistor drive capability switching section 13, 23 P-channel transistor drive section 14, 24 N-channel transistor drive capability switching section 15, 25 N Channel transistor driver

Claims (1)

[Claims] 1. A multiple power supply interface section is configured by mounting a plurality of power supply interface sections each including a functional configuration section, a P or N channel transistor drive capability switching section, and a P or N channel transistor drive section. Wherein the plurality of power supply interface units can be bidirectionally buffered.