JP2000285227A - Information processing apparatus and control method thereof - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce wasteful power consumption of an information processing device such as a portable computer device operated by a battery and to prolong a battery operation time. SOLUTION: In a graphics accelerator for performing a drawing process for a VRAM at a high speed, a drawing command storage state in a FIFO buffer memory in which a drawing command to be processed is stored is monitored, and the FIFO buffer memory becomes empty and the drawing is performed. When the drawing process by the unit is in the non-execution state, the supply of the clock signal from the clock control unit to the drawing unit is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an information processing apparatus such as a portable computer device and a control method thereof.

[0002]

2. Description of the Related Art In an information processing apparatus such as a personal computer, power management for power saving is performed by an operating system. In the power management by the operating system, for example, when the system has not been used for a certain period of time, the system is set to a power down mode called a standby state. In this standby state, power consumption is reduced by lowering (stopping) the operation clock of the CPU or stopping the rotation of the hard disk.

However, devices that speed up drawing processing, such as graphics accelerators, are not subject to power management by the operating system, and not only during the above-described standby state, but also whether or not drawing processing is being performed. Regardless of this, a constant high-speed clock signal is always supplied to the drawing speed-up device.

Therefore, the power utilization efficiency of the above-described drawing speed-up device cannot be said to be excellent, and in particular, the PDA (Pers.
In personal information devices such as onalDigital Assistant), improvement in power use efficiency is strongly expected.

[0005]

In a drawing speed-up device such as a graphics accelerator, a high-speed clock is supplied even during a period in which drawing processing is not executed, which leads to wasteful consumption of power. In particular, in a personal information device operated by a battery, there is a problem that the battery operation time is shortened due to wasteful power consumption due to the high-speed clock supply when the drawing process is not executed.

An object of the present invention is to solve such a problem, and to reduce the power consumption of a high-speed arithmetic circuit for a drawing process, thereby contributing to prolonging a battery operation time. And a control method thereof.

[0007]

According to a first aspect of the present invention, there is provided an information processing apparatus, comprising: a storage unit for storing a drawing command; and a drawing unit configured to store a drawing command read from the storage unit. Drawing means for performing drawing processing on the memory for use, and means for controlling supply of a clock signal to the drawing means in accordance with the presence or absence of the drawing command in the storage means and the state of the drawing processing by the drawing means. It is characterized by the following.

According to a second aspect of the present invention, there is provided an information processing apparatus, comprising: storage means for storing a drawing command; drawing means for performing a drawing process on a drawing memory in accordance with the drawing command read from the storage means; Means for stopping supply of the clock signal to the drawing means when the drawing command is not stored in the drawing means and when the drawing processing by the drawing means is in a non-executing state. .

An information processing apparatus according to a third aspect of the present invention includes a storage unit for storing a drawing command, a drawing unit for performing a drawing process on a drawing memory based on the drawing command read from the storage unit, and the storage unit. If the drawing command is not present in the memory, or if the drawing command read from the storage unit is a drawing command for a drawing process independent of the operation of the drawing unit, and the drawing process by the drawing unit is not executed. Means for stopping the supply of the clock signal to the drawing means when in the state.

According to a fourth aspect of the present invention, there is provided a method for controlling an information processing apparatus, comprising: a storage unit for storing a drawing command; and a drawing unit for performing a drawing process on a drawing memory based on the drawing command read from the storage unit. Supplying a clock signal to the drawing unit when the drawing command is not stored in the storage unit and when the drawing process by the drawing unit is in a non-execution state. Is stopped.

According to a fifth aspect of the present invention, there is provided a control method for an information processing apparatus, comprising: a storage unit for storing a drawing command; and a drawing unit for performing a drawing process on a drawing memory based on the drawing command read from the storage unit. In the control method of the information processing apparatus, the case where the drawing command is not present in the storage unit or the case where the drawing command read from the storage unit is a drawing command for a drawing process independent of the operation of the drawing unit And when the drawing processing by the drawing means is in a non-execution state, the supply of the clock signal to the drawing means is stopped.

As described above, according to the present invention, it is possible to reduce unnecessary power consumption by controlling the supply of the high-speed clock signal to the drawing means, for example, when the drawing processing is not executed. In particular, the battery operation time of the information processing device operated by a battery can be extended.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a PDA according to an embodiment of the present invention.
1 shows an overall configuration of an information processing apparatus such as (Personal Digital Assistant).

[0015] As shown in FIG.
System memory (DRAM) 20, Processor (Proces)
sor) 21, power control circuit (Power Control) 22, M
It comprises a ROM 23, a VRAM 24, a keyboard controller (KBC) 25, and a device controller 26.

The system memory 20 is a memory that stores programs and data and is used as a work area of the processor 21. The processor 21 is a device that interprets and executes program instructions. The power supply control circuit 22 is a circuit for controlling a system power supply. The MROM 23 is a memory in which basic software of the system is stored. VRA
M24 is a memory for storing data to be displayed on the display device. The keyboard controller 25 is a device that controls a connected keyboard.

The device controller 26 includes a bus controller (Bus Controller) 1 and a display controller (LC).
D / CRT Controller 2, Graphics Accelerator 3, USB (Universal Serial Bu
s) Host controller 4, VRAM controller (V
RAM Controller) 5, PCMCIA Controller (P
CMCIA Controller 6, Smart Media Controller 7, I / O Bus Controller 8, Register Interface Bus 9, VRAM Interface Bus 10,
It comprises a clock controller (Clock Controller) 11 and an interrupt controller (Interrupt Controller) 12.

The bus controller 1 is a device for controlling the internal bus of the device controller 26. The display controller 2 is a device that controls display on a display device such as an LCD panel or a CRT. The graphics accelerator 3 is a device that performs an auxiliary operation for speeding up a drawing process. The USB host controller 4 is a device that controls a connected USB device. VRAM controller 5
Is a device for controlling the VRAM 24. The PCMCLA controller 6 is a PCMCLA (Personal Computer Memo).
This is a controller that handles an interface with a PC card conforming to the ry Card International Association (ry Card). The smart media controller 7 is a controller that controls a connected flash memory. The I / O bus controller 8 is a controller that controls the keyboard controller 25 and connected expansion devices. The register interface bus 9 is an internal bus used for accessing internal registers. The VRAM interface bus 10 connects devices that access the VRAM 24. The clock controller 11 is a controller that selects a clock source and performs clock gating. The interrupt controller 12 is a controller that identifies an interrupt factor and controls its enable / disable.

FIG. 2 shows a graphics accelerator 3.
Is shown.

As shown in FIG. 1, the graphics accelerator 3 includes a clock control unit 3-1, an accelerator control unit 3-2, a memory arbitration unit 3-4, a FIFO buffer memory 3-5, and a drawing unit 3-10. Be composed.

The accelerator control unit 3-2 receives a drawing command issued from the microprocessor 21 and converts the received drawing command through the memory arbitration unit 3-4 into a FIFO.
Write to the O buffer memory 3-5. Further, the accelerator control unit 3-2 reads out the drawing command from the FIFO buffer memory 3-5 through the memory arbitration unit 3-4,
It is transmitted to the drawing unit 3-10. Further, the accelerator control unit 3-2 detects a situation where no drawing command is stored in the FIFO buffer memory 3-5, and draws a picture to the clock control unit 3-1 when detecting a situation where this drawing command is not stored. The absence of a command is notified by signal 3-6.

The drawing unit 3-10 executes a drawing process based on a drawing command given by the accelerator control unit 3-2. The drawing unit 3-10 asserts the signal 3-7 during the execution of the drawing process to inform the clock control unit 3-1 that the drawing process is being executed. 7 is deasserted and the clock control unit 3-
1 is notified of the completion of the drawing process.

The clock control unit 3-1 includes a drawing unit 3-10.
Supplies a clock for drawing processing. The clock control unit 3-1 receives the signal 3-6 indicating that there is no drawing command from the accelerator control unit 3-2, and when the signal 3-7 generated from the drawing unit 3-10 is deasserted, It operates so as to stop the supply of the drawing processing clock to the drawing unit 3-10.

Next, the operation of the graphics accelerator 3 will be described.

The drawing command issued from the microprocessor 21 is written into an empty area of the FIFO buffer memory 3-5 specified by the memory arbitration unit 3-4 under the control of the accelerator control unit 3-2. When the drawing command is written into the FIFO buffer memory 3-5, the accelerator control unit 3-2 makes the FIFO buffer memory 3-5.
5 is notified to the clock control unit 3-1 by a signal 3-6 that the drawing command is present in the memory arbitration unit 3
-4 is requested to read a drawing command from the FIFO buffer memory 3-5.

The memory arbitration unit 3-4, which is requested to read the drawing command from the accelerator control unit 3-2,
The drawing command is sequentially read from the IFO buffer memory 3-5, and the drawing command is passed to the accelerator control unit 3-2. At this time, the drawing command is decoded by the accelerator control unit 3-2, and parameters relating to the drawing data in the command are set in an internal register (not shown).

On the other hand, when the clock controller 3-1 receives a signal 3-6 from the accelerator controller 3-2 to notify that there is a drawing command in the FIFO buffer memory 3-5, the clock controller 3-10 Clock for drawing processing 3-9
Supply.

The drawing section 3-10 refers to an internal register (not shown) in the accelerator
24 is performed. The drawing unit 3-10 asserts the signal 3-7 during the drawing processing to notify the clock control unit 3-1 that drawing is being executed. When the drawing processing is completed, the drawing unit 3-10 deasserts the signal 3-7 and notifies the clock control unit 3-1 that the drawing processing has been completed.

Further, the accelerator control section 3-2 includes:
When it is confirmed that all the drawing commands in the FIFO buffer memory 3-5 have been consumed and disappeared, the signal 3-6 transmitted to the clock control unit 3-1 is deasserted.

Thus, when the signal 3-7 of the drawing section 3-10 is deasserted and the signal 3-6 of the accelerator control section 3-2 is deasserted, the clock control section 3-1 sets the drawing section 3-10. The supply of the clock signal 3-9 to is stopped.

As described above, in the present embodiment, F
There is no drawing command in the IFO buffer memory 3-5, a signal 3-6 indicating the command is deasserted, and the drawing unit 3-10 finishes the drawing process, indicating that the drawing unit 3-10 is executing. When signals 3-7 are deasserted,
That is, while the drawing unit 3-10 is in the idle state, the supply of the clock 3-9 to the drawing unit 3-10 is stopped, so that the power consumption of the drawing unit 3-10 can be reduced. it can.

In this embodiment, the signal 3-6 to the clock control unit 3-1 is deasserted when there is no drawing command in the FIFO buffer memory 3-5. However, the FIFO buffer memory 3-5 Even if there is a drawing command inside, if this is a command other than a command for causing the drawing unit 3-10 to execute a drawing process, the signal 3-6 to the clock control unit 3-1 is deasserted as described above. You may do so.

Next, another embodiment of the graphics accelerator according to the present invention will be described with reference to FIG.

In the graphics accelerator 13 shown in FIG.
It monitors whether the command read from the FO buffer memory 13-5 is an execution command for drawing processing by the drawing unit 13-10, and if not, outputs a signal 13 to the clock control unit 13-1. Deassert -6.

That is, the drawing command includes VRAM2
Execution command for performing a drawing operation on
There is a non-execution command for performing only the parameter setting without performing the drawing operation on the AM 24. The accelerator control unit 13-2 of the present embodiment determines the execution command and the non-execution command and switches the state of the signal 13-6 to be output to the clock control unit 13-1.

Next, the operation of the graphics accelerator 13 will be described.

The drawing command issued from the microprocessor 21 is written into an empty area of the FIFO buffer memory 13-5 specified by the memory arbitration unit 13-4 under the control of the accelerator control unit 13-2. When the drawing command is written into the FIFO buffer memory 13-5, the accelerator control unit 13-2 informs the signal 13-of that the drawing command is present in the FIFO buffer memory 13-5.
6 and notifies the clock control unit 13-1 and requests the memory arbitration unit 13-4 to read the drawing command from the FIFO buffer memory 13-5.

Memory arbitration unit 13-4 requested to read a drawing command from accelerator control unit 13-2
Reads the drawing command sequentially from the FIFO buffer memory 13-5, and passes the drawing command to the accelerator control unit 13-2. At this time, the drawing command is decoded by the accelerator control unit 13-2, and it is determined whether the drawing command is an execution command or a non-execution command. When the drawing command is an execution command, parameters relating to drawing data in the command are set in an internal register (not shown).

On the other hand, the clock control unit 13-1 receives the signal 13-6 from the accelerator control unit 13-2,
When receiving a notification that there is a drawing command in the buffer memory 13-5, the drawing unit 13-10 is supplied with a drawing processing clock 13-9.

The drawing unit 13-10 refers to an internal register (not shown) in the accelerator control unit 13-2 to generate a VR.
A drawing process for the AM 24 is performed. While performing the drawing process, the drawing unit 13-10 asserts the signal 3-7 to notify the clock control unit 13-1 that drawing is being executed. When the drawing process is completed, the drawing unit 13-10 deasserts the signal 13-7 to notify the clock control unit 13-1 that the drawing process has been completed.

Further, the accelerator control unit 13-2
After confirming that all the drawing commands in the FIFO buffer memory 13-5 have been consumed and disappeared, deasserts the signal 13-6 to be transmitted to the clock control unit 13-1.

Thus, when the signal 13-7 of the drawing unit 13-10 is deasserted and the signal 13-6 of the accelerator control unit 13-2 is deasserted, the clock control unit 13-1 draws the signal. Clock signal 13 to
The supply of -9 is stopped.

Further, the accelerator control unit 13-2
If it is determined that the drawing command read from the FIFO buffer memory 13-5 is a non-execution command, only processing for setting parameters necessary for the drawing processing in the register is performed, and the processing to the clock control unit 13-1 is performed. Signal 13
Deassert -6. Therefore, the clock control unit 1
3-1 indicates that the signal 13-7 of the drawing unit 13-10 is deasserted and the signal 13-6 of the accelerator control unit 13-2 is deasserted, as in the case where the drawing command is lost in the FIFO buffer memory 13-5. When done
The supply of the clock signal 13-9 to the drawing unit 13-10 is stopped.

As described above, in the present embodiment, F
When there is no drawing command in the FIFO buffer memory 13-5, or when the drawing command read from the FIFO buffer memory 13-5 is drawn by the drawing command (non-execution command ) And when the drawing process by the drawing unit 13-10 is in the non-execution state, the clock control unit 13-1
By stopping the supply of the clock signal from the to the drawing unit 13-10, the power consumption of the drawing unit 3-10 can be reduced.

[0045]

As described above in detail, according to the present invention, the supply of the high-speed clock signal to the drawing means is controlled, for example, to stop when the drawing processing is not executed, so that the useless power is wasted. The consumption amount can be reduced, and in particular, the battery operating time of the information processing device that is operated by a battery can be extended.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of the graphics accelerator of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of a graphics accelerator according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Bus controller 2 ... Display controller 3 ... Graphics accelerator 3-1 ... Clock control part 3-2 ... Accelerator control part 3-4 ... Memory arbitration part 3-5. ··· FIFO buffer memory 3-10 ··· Drawing unit 4 ··· USB host controller 5 ··· VRAM controller 6 ···· PCMCIA controller 7 ··· Smart media controller 8 ··· I / O bus controller 9 ··· Register interface bus 10 VRAM interface bus 11 Clock controller 12 Interrupt controller 20 System memory 21 Microprocessor 24 VRAM 26 Device controller

Continuation of front page (72) Inventor Yoshiaki Murano 1-3-3 Shinmachi, Ome-shi, Tokyo F-term (reference) in Toshiba Computer Engineering Co., Ltd. 5B057 CH11 CH18 5B069 AA01 BB13 BC02 LA16 5B079 BA12 BB10 BC01

Claims (5)

[Claims] A storage unit configured to store a drawing command; a drawing unit configured to perform a drawing process on a drawing memory in accordance with the drawing command read from the storage unit; Means for controlling the supply of a clock signal to the drawing means in accordance with the state of the drawing processing by the drawing means. 2. A storage unit for storing a drawing command; a drawing unit for performing a drawing process on a drawing memory in accordance with the drawing command read from the storage unit; and wherein the drawing command is not stored in the storage unit. And a means for stopping the supply of the clock signal to the drawing means when the drawing processing by the drawing means is not performed. A storage unit for storing a drawing command; a drawing unit for performing a drawing process on a drawing memory based on the drawing command read from the storage unit; When the drawing command read from the storage unit is a drawing command for a drawing process independent of the operation of the drawing unit, and when the drawing process by the drawing unit is in a non-executing state, Means for stopping the supply of the clock signal. 4. A control method for an information processing apparatus, comprising: a storage unit for storing a drawing command; and a drawing unit for performing a drawing process on a drawing memory in accordance with the drawing command read from the storage unit. And stopping the supply of a clock signal to the drawing unit when the drawing command is not stored in the drawing unit and when the drawing process by the drawing unit is not executed. . 5. A control method for an information processing apparatus, comprising: a storage unit for storing a drawing command; and a drawing unit for performing a drawing process on a drawing memory in accordance with the drawing command read from the storage unit. If the drawing command is not present in the drawing unit, or if the drawing command read from the storage unit is a drawing command for a drawing process independent of the operation of the drawing unit, and the drawing process by the drawing unit is not executed A method for controlling an information processing apparatus, comprising: stopping a supply of a clock signal to the drawing means when in a state.