JP2000293208A - Sequence control system - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To easily verify the operation status of elements constituting a ladder sequence circuit diagram. A sensor for detecting a state of a production facility (10).
2 and the operation state of the actuator 14 for driving the production equipment 10 are stored in an input / output register 18.
Is output to the trace mechanism 26. Trace mechanism 2
Numeral 6 stores the previous state as the state of each register in the memory 30, stores the current state in the memory 28, compares the contents of both memories, and transfers the data relating to the register whose state has changed to the edit file 42. . Control verification mechanism 44
Fetches a ladder sequence control circuit diagram relating to a specified register from the definition file 36, compares this circuit diagram with the change state of each register input from the edit file 42, and obtains the operation coverage of the sequence from the comparison result. The result is displayed on the input / output device 46.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequence control system, and more particularly to a sequence control system suitable for controlling production equipment such as food, chemicals, chemicals, and general machines in accordance with a ladder sequence.

[0002]

2. Description of the Related Art Conventionally, an equipment control sequencer has been used for automatically controlling production equipment such as food, chemicals, pharmaceuticals, and general machinery. This sequencer controls a single or a plurality of equipments that operate at a fixed period. A sequence is provided. As a program language for describing the equipment control sequence, a language called a ladder sequence is used. The advantage of the ladder sequence is that the input condition and the output when the input condition is satisfied can be described by simple rules as a ladder sequence control circuit diagram, and the production equipment and the ladder sequence that controls this production equipment are paired. The point is that they correspond. For example, a register group that constitutes an element of the ladder sequence control circuit diagram, and a sensor, a valve, a pump, and the like that detect a state of a production facility correspond one-to-one.

On the other hand, the disadvantage of the ladder sequence is that, as the equipment to be controlled becomes larger and more complicated, the amount of description of the ladder sequence becomes enormous and maintenance becomes difficult.
Specifically, there are many cases where a point of mismatch between the production equipment and the ladder sequence is generated by repeatedly adding and renovating the production equipment. With aging due to aging, changes in production equipment, or circuit changes, some registers constituting the ladder sequence may not operate effectively.

[0004] On the other hand, the progress of the performance of the sequencer has been remarkable recently, but at present, the resource capacity of the memory or the like does not change much. For this reason, when creating a ladder sequence, it is necessary to pay particular attention to efficient use of resources.

[0005]

In the prior art,
Consideration has not been given to verifying the function of the ladder sequence. For example, when it is necessary to replace production equipment due to aging due to aging or expansion or renovation of production equipment, it is necessary to verify the function of the ladder sequence as a preliminary survey. A ladder sequence program list is output, and the ladder sequence function is checked by associating the list with a signal table or the like. However, in such a verification method, particularly in an old system, enormous time and labor are spent for the function investigation due to bad conditions such as a lack of related materials. In other words, if there is a mismatch between the equipment and the ladder sequence due to an extension or renovation of the production equipment or a circuit change, among the elements (registers) that constitute the ladder sequence, those that are not actually used It is difficult to determine whether there is.

An object of the present invention is to provide a sequence control system capable of easily verifying the operation states of elements constituting a ladder sequence control circuit diagram.

[0007]

In order to achieve the above object, the present invention provides a state detecting means for detecting a state of a controlled object, a driving means for driving the controlled object in accordance with an operation command, and the state detecting means. A sequence control unit that generates a drive command for driving the control target according to the detection output and the sequence control logic, and outputs the drive command to the drive unit, and a ladder sequence control circuit diagram according to the sequence control logic. Tracing means for tracing the operating states of the elements relating to the state detecting means and the driving means among the constituent elements based on the detection output of the state detecting means and the driving command; and Comparing the ladder sequence control circuit diagram with the ladder sequence control circuit diagram, the operation confirmation coverage of the elements constituting the ladder sequence control circuit diagram It is obtained by constituting the sequence control system comprising a coverage rate verification means for verifying.

According to the present invention, as means for visually verifying the validity, state detecting means for detecting a state of a controlled object, driving means for driving the controlled object in accordance with an operation command, A sequence control unit that generates a drive command for driving the control target according to a detection output and sequence control logic, and outputs the drive command to the drive unit, and a ladder sequence control circuit diagram according to the sequence control logic. Validation display means for sequentially displaying, along the time axis, the operation states of the elements related to the state detection means and the drive means among the elements to be performed, based on the detection output of the state detection means and the drive command. And a sequence control system including the following.

Further, when configuring a sequence control system, it is possible to configure a system capable of verifying coverage and validity by combining elements of the above-described sequence control systems.

In configuring each of the sequence control systems, the following elements can be added.

(1) The ladder sequence control circuit diagram is displayed, and the operation of the elements related to the state detecting means and the driving means among the elements constituting the ladder sequence control circuit diagram on the ladder sequence diagram. Circuit diagram display means for displaying a state based on the detection output of the state detection means and the drive command.

(2) Coverage ratio display means for displaying a verification result of the coverage ratio verification means is provided.

(3) Food, chemical, pharmaceutical, and general machinery production equipment is to be controlled.

According to the above means, the operation states of the elements related to the state detecting means and the driving means as elements constituting the ladder sequence control circuit diagram are traced based on the detection output of the state detecting means and the driving command, Since this trace result is compared with the ladder sequence control circuit diagram to verify the operation confirmation coverage of each element, it is possible to reliably verify whether or not the elements constituting the ladder sequence are actually used. . Also, by displaying the verification result, the operation check coverage of the ladder sequence can be visually verified. Further, by displaying the operation states of the elements constituting the ladder sequence together with the ladder sequence control circuit diagram, the operation states of each element can be visually verified and quantitatively grasped.

Further, by sequentially displaying the operation states of the elements constituting the ladder sequence along the time axis, it becomes easy to verify the validity of the ladder sequence. Further, it is possible to easily verify which equipment is effectively controlled as a control target for production equipment such as food, chemicals, chemicals, and general machinery.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In each drawing, a solid line with an arrow indicates a flow of processing, and a broken line with an arrow indicates a flow of data.

FIG. 1 is an overall configuration diagram of a sequence control system for production equipment according to an embodiment of the present invention. In FIG. 1, the sequence control system for production equipment
A production facility 10 such as a chemical / chemical / general equipment is controlled, and the production facility 10 is composed of various devices such as a valve and a pump. Various devices constituting the production facility 10 are provided with a plurality of sensors 12 as state detecting means for detecting the state of the production facility 10, that is, the state of each device, and driving each device in accordance with an operation command. A plurality of actuators 14 as means are provided. Each sensor 12 and each actuator 14 are connected to a sequencer 16, respectively.

The sequencer 16 includes an input / output register 18, equipment control ladder sequences 20a to 20n, and an interface register (shared memory) 22 as sequence control means, and a register status tracing mechanism 24 as trace means. Have been. The input / output register 18 includes an input register corresponding to each sensor 12 and an output register corresponding to each actuator 14.
Is a register controlled by the state of the input register,
For example, it is provided with a register controlled by establishment of an internal situation. Equipment control ladder sequence 20
a to 20n constitute a ladder sequence control circuit diagram according to the sequence control logic. For example, as shown in FIG. 2, the input register associated with the sensor 12 for detecting the open / closed state of the valve is a RE.
G00, a relay coil associated with the actuator 14 that drives the pump when the valve is closed is an output register REG02, a register controlled on condition that the register REG00 is operated is REG01, an input register REG00, The relay coil that operates when the condition with the register REG01 as the interface register 22 is satisfied is set to the output register R
If set as EG03, register REG0
Sequence logic that turns on the register REG02 when the condition of 0 is satisfied, and registers REG00 and REG
When the condition of 01 is satisfied, the information of the ladder sequence control circuit diagram according to the sequence logic in which the register REG03 is turned on is the equipment control ladder sequence 20a.
To 20n. In this case the register R
EG00, REG01, REG02, and REG03 are elements constituting a ladder sequence control circuit diagram, respectively. Signals relating to the operation states of the input / output register 18 and the interface register 22 are supplied to the register status tracing mechanism 24.

The register status tracing mechanism 24 includes a tracing mechanism 26, memories 28 and 30, and a trace file 32.
It is provided with. The tracing mechanism 26 captures signals from the input / output register 18 and the interface register 22 and stores the current state of each register, that is, the state of each register when the signal is captured, in the memory 28. Data relating to the previous state is fetched, only the register whose state has changed from the input / output register 18 and the interface register 22 is extracted, and the data relating to the extracted register is stored in the trace file 32. At this time, the trace file 32 stores only the data related to the register whose state has changed, so that it is not necessary to store the data related to all the registers.
Capacity can be reduced. The data stored in the trace file 32 is transferred to the host computer 34.

The host computer 34 operates as a coverage ratio verification means.
A ladder sequence definition file 36, an operation information file 38, a trace editing mechanism 40, an editing file 42, and a control verification mechanism 44 are provided.
4 is connected to the input / output device 46. The ladder sequence definition file 36 stores information related to the sequence control logic, and also stores information related to the ladder sequence control circuit diagram according to the sequence control logic. That is, input / output register 1
8. Information on the ladder sequence control circuit diagram having the interface register 22 as an element is stored.
The operation information file 38 captures information from the input / output device 46 by the operation of the operator, and stores the operation information accompanying the operation of the operator in the input / output register 18 and the interface register 22 as operation information for specifying a specific register. The information about the register number of the register to which it belongs is stored. The trace editing mechanism 40 collects data on the register whose state has changed from the trace file 32, and
For example, the data is edited as display data, and the edited data is stored in the editing file 42. The control verification mechanism 44 receives the instruction accompanying the operation of the operator from the input / output device 4.
6, an operation information file 3 in which a register number (name) by an operator's operation is stored.
8 to extract the register number information by the operation (instruction) of the operator, search the ladder sequence definition file 36 and the edit file 42 based on the extracted information,
The information on the ladder sequence control circuit diagram and the data on the register whose state has changed are compared and collated, and the operation check coverage of the registers constituting the ladder sequence control circuit diagram is calculated from the comparison and collation result. Output to the input / output device 4 in a ladder sequence circuit format or a time chart format.
6 is output.

As shown in FIG. 2, an input / output device 46 includes an operation unit 48 for inputting information by an operation of an operator.
And display units 50, 52, and 54 constituting a ladder sequence coverage verification screen as coverage ratio display means and circuit diagram display means. The display unit 50 displays the sequencer number and the total sequence coverage by numerical values, the display unit 52 displays a ladder sequence control circuit diagram, and the display unit 54 displays the numerical coverage of each control system. It has become.

As shown in FIG. 3, the input / output device 46 is provided with display units 56 and 58 constituting a ladder sequence validity verification screen as validity verification display means. The display unit 56 displays the information on the trace disclosure time in numerical values, and the display unit 58 displays the operation status of the registers related to the key register and the related registers in a time chart format.

Next, the operation of the sequencer 16 will be described with reference to the flowchart of FIG.

First, when an activation is instructed by the operator from the input / output device 46 to the trace mechanism 26 of the sequencer 16, the trace file 32 is initialized (step 101). Next, of the data input to the trace mechanism 26, the register number and the state of each register are stored as data relating to the input / output register 18 and the interface register 22 together with the activation time (steps 102 and 103). Thereafter, the trace address of the trace file 32 is updated (step 104), and then it is determined whether or not a stop command has been input from the input / output device 46 (step 105).
At this time, if there is a stop command, the processing in this routine is terminated. If there is no stop command, the register numbers of all registers and the states of all registers are stored in the memory 28 as the current state of each register (step 10).
6). Thereafter, the tracing mechanism 26 compares the previous state of each register stored in the memory 30 with the current state stored in the memory 28 to determine whether the state of each register has changed (step 107). . As a result of this comparison, when a register whose state has been changed is detected as being different, the time at which the change occurred, the register number, and the state of the register are stored in the designated trace address of the trace file 32 (step 108). next,
The trace address is updated in the trace file 32 in accordance with the trace address update command, for example, the trace address update command generated every 30 ms (step 109). Thereafter, for the next command, the state relating to the register whose state has changed this time (this state) is stored in the memory 30 as the previous state (step 110), and the processing in this routine is terminated.

Next, the operation of the trace editing mechanism 40 will be described with reference to FIG.
This will be described according to the flowchart of FIG.

First, when the trace editing mechanism 40 is started via the input / output device 46 by the operation of the operator, the data of the trace file 32 is sequentially stored in the trace editing mechanism 4.
The data is input to 0, and the data relating to the register specified by the operator among the input data is determined (step 201). For example, when the input registers REG00 and REG01 and the output registers REG02 and REG03 shown in FIG. 2 are designated as the registers, the register numbers and the contents of the designated registers, that is, the information on the register states and the change of the state The information on the performed time is stored in the edit file 42 (step 202). Thereafter, it is determined whether or not the processing for all the registers has been completed (step 20).
3), the processing of step 202 is performed until the processing for all the registers specified by the operator is completed (step 203), and when the processing for all the registers is completed, the processing in this routine is completed (step 2).
04). When the editing process for all the registers is completed, the control verification mechanism 44 verifies the coverage.

Next, the operation of the control verification mechanism 44 will be described with reference to the flowchart of FIG. First, when an activation is instructed from the input / output device 46 to the control verification mechanism 44 by an operation of the operator, the activation of the control verification mechanism 44 is started. Thereafter, when the information on the register to be verified is input by the operation of the operator, the information on the register according to the operation of the operator is sequentially input from the operation information file 38 (step 301). Subsequently, it is determined whether verification of coverage or verification of validity is designated by an operation of the operator (step 3).
02). At this time, when the coverage verification is specified,
Information relating to the sequence control logic and information relating to the ladder sequence control circuit diagram related to the register specified by the operator's operation are retrieved from the ladder sequence definition file 36 and input (step 303).
Thereafter, the ladder sequence control circuit diagram is displayed on the display unit 52 of the input / output device 46 (step 304).
Data on the state of each register constituting the ladder sequence control circuit diagram displayed on the display unit 52 is fetched from the edit file 42 (step 305). Then, according to the input data, the state of each register is displayed on the display unit 52, and the state of each register is displayed on this ladder sequence control circuit diagram (step 306).

For example, as shown in FIG.
G00, 01, 02, 03, 10, 11, 12, 13,
When the states of the registers REG16 and REG17 do not change while the states of the registers 14, 15 and 18 change,
Circuits connecting the registers whose status has changed are displayed in bold lines and in green. On the other hand, the registers whose status has not changed, that is, the circuits connecting the REGs 16 and 17 are displayed in white with thin lines.

Further, in step 306, the coverage ratio for each output unit of the ladder sequence is calculated on the basis of the data on the state of each register constituting the ladder sequence control circuit diagram and the information of the ladder sequence circuit diagram. The result is displayed on the display unit 54.

For example, the register REG02 is a register R
Since EG00 is on, register REG0
The coverage ratio of the circuit (control system) including 2 and the register REG00 is displayed as 100%. The circuit related to the register REG03 is displayed as 100% coverage because both the register REG00 and the register REG01 are on. On the other hand, the circuit relating to REG18 is a register group forming four OR conditions, REG10, 11, 12,.
Only 13, 14, 15 are turned on, and REG16, RE
Since G17 is off, that is, one of the four systems is off, the coverage rate is displayed as 75%.

Thereafter, the processing of steps 305 and 306 is performed as processing relating to other registers. When the processing relating to all registers is completed, the processing shifts to the next processing (step 307).

After the verification of the coverage is executed, if it is specified to verify the validity, a process according to the operation of the operator is started. For example, the register REG18 shown in FIG. 2 is designated as a key register, and REG10, 12,
When 4 and 16 are designated, information about the register REG 18 as a key register is input from the operation information file 38 (step 308), and information about the registers REG 10, 12, 14, and 16 as related registers is input to the ladder sequence definition file 36. Is retrieved and input (step 309). Thereafter, the data relating to each register is sequentially fetched from the edit file 42 (step 31).
0), the change state of each register is displayed on the display unit 58 of the input / output device 46 in a time chart format.

That is, as shown in FIG.
EG18, related registers REG10, 12, 14, 1
6, the changes in the state are sequentially displayed along the time axis (step 311). In this case, the name of the equipment corresponding to this register can be displayed in each register.
When the change of the state of the key register and the related register is displayed on the display unit 58, the operator can see this state and determine the validity of the sequence control. Further, by displaying the contents of the previous page and the next page (other circuits) by operating the page, a ladder sequence validity verification screen can be displayed for each equipment, and the validity of the sequence control is determined for each equipment. be able to.

According to the present embodiment, the operation check coverage of the ladder sequence can be visually verified as the state of the production equipment. Therefore, when a large-scale sequence test is performed, an invalid circuit (not required) that is not actually used is used. Effective equipment) and effective management for checking the progress of equipment. In particular,
Even when the related materials are often scarce, such as when verifying the functions of the old system, the operation status of the ladder sequence can be reliably verified. Furthermore, the operation coverage of the ladder sequence can be quantitatively grasped, and the status of the registers constituting the ladder sequence is displayed in the form of a time chart that is displayed together with the circuit diagram. It is possible to easily determine whether the control of the ladder sequence is appropriate for the production equipment.

[0035]

As described above, according to the present invention,
Tracing the operating states of the elements related to the state detecting means and the driving means as elements constituting the ladder sequence control circuit diagram based on the detection output of the state detecting means and the driving command,
Since this trace result is compared with the ladder sequence control circuit diagram to verify the operation confirmation coverage of each element, it is possible to reliably verify whether or not the elements constituting the ladder sequence are actually used. . Also, by displaying the verification result, the operation check coverage of the ladder sequence can be visually verified. Further, by displaying the operation states of the elements constituting the ladder sequence together with the ladder sequence control circuit diagram, the operation states of each element can be visually verified and quantitatively grasped.

Further, by sequentially displaying the operation states of the elements constituting the ladder sequence along the time axis, it is easy to verify the validity of the ladder sequence. Further, it is possible to easily verify which equipment is effectively controlled as a control target for production equipment such as food, chemicals, chemicals, and general machinery.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a system according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a ladder sequence coverage verification screen.

FIG. 3 is a diagram illustrating a configuration of a ladder sequence validity verification screen.

FIG. 4 is a flowchart for explaining the operation of the tracing mechanism.

FIG. 5 is a flowchart for explaining the operation of the trace editing mechanism.

FIG. 6 is a flowchart for explaining the operation of the control verification mechanism.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Production equipment 12 Sensor 14 Actuator 16 Sequencer 18 I / O register 20a-20n Equipment control ladder sequence 22 Interface register 24 Register status trace mechanism 26 Trace mechanism 28, 30 Memory 32 Trace file 34 Upper computer 36 Ladder sequence definition file 38 Operation information file 40 trace edit mechanism 42 edit file 44 control verification mechanism 46 input / output device

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takuo Kudo 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture Inside Hitachi Information & Control Systems Co., Ltd. (72) Inventor Fumiaki Miyamoto 5-chome Omikamachi, Hitachi City, Ibaraki Prefecture No. 1 In the Hitachi Information & Control System Co., Ltd. (72) Inventor Satoshi Oishi 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture F-term in the Hitachi, Ltd. Omika Plant F-term (reference) 5H220 AA04 BB09 CC05 DD04 FF07 HH01 JJ12 JJ26 JJ28 JJ34 JJ42 JJ53 KK01 LL04 5H223 AA05 CC03 CC08 DD03 EE04 EE18 FF03 9A001 JJ49 KK54 LL02 LL09

Claims (6)

[Claims] 1. A state detecting means for detecting a state of a controlled object, a driving means for driving the controlled object in accordance with an operation command, and a driving means for driving the controlled object in accordance with a detection output of the state detecting means and a sequence control logic. A sequence control unit that generates a drive command and outputs the drive command to the drive unit, and a ladder sequence control circuit diagram according to the sequence control logic, which is related to the state detection unit and the drive unit. Tracing means for tracing the operation state of the element based on the detection output of the state detecting means and the drive command; and comparing the tracing result of the tracing means with the ladder sequence control circuit diagram to control the ladder sequence control. A sequence control comprising a coverage verification means for verifying the operation verification coverage of the elements constituting the circuit diagram system. 2. A state detecting means for detecting a state of a controlled object, a driving means for driving the controlled object in accordance with an operation command, and a driving means for driving the controlled object in accordance with a detection output of the state detecting means and a sequence control logic. A sequence control unit that generates a drive command and outputs the drive command to the drive unit, and a ladder sequence control circuit diagram according to the sequence control logic, which is related to the state detection unit and the drive unit. A sequence control system comprising: a validity verification display means for sequentially displaying an operation state of an element along a time axis based on a detection output of the state detection means and the drive command. 3. A state detecting means for detecting a state of a controlled object, a driving means for driving the controlled object in accordance with an operation command, and a driving means for driving the controlled object in accordance with a detection output of the state detecting means and a sequence control logic. A sequence control unit that generates a drive command and outputs the drive command to the drive unit, and a ladder sequence control circuit diagram according to the sequence control logic, which is related to the state detection unit and the drive unit. Tracing means for tracing the operation state of the element based on the detection output of the state detecting means and the drive command; and comparing the tracing result of the tracing means with the ladder sequence control circuit diagram to control the ladder sequence control. A coverage verification means for verifying the operation verification coverage of the elements constituting the circuit diagram; and the sequence control logic. The operation states of the elements relating to the state detecting means and the driving means among the elements constituting the ladder sequence control circuit diagram according to the clock are determined along the time axis based on the detection output of the state detecting means and the driving command. A sequence control system comprising: a validity verification display means for sequentially displaying the data. 4. The ladder sequence control circuit diagram is displayed, and an operation state of an element related to the state detection unit and the drive unit among the elements constituting the ladder sequence control circuit diagram on the ladder sequence diagram. 4. The sequence control system according to claim 1, further comprising: circuit diagram display means for displaying on the basis of a detection output of the state detection means and the drive command. 5. The sequence control system according to claim 1, further comprising a coverage ratio display unit for displaying a verification result of said coverage ratio verification unit. 6. The apparatus according to claim 1, wherein production equipment for food, chemical, pharmaceutical and general machinery is controlled.
6. The sequence control system according to 3, 4 or 5.