JP2000293681A - Image filter circuit and filtering method using median filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a picture filter circuit which can be constituted by using a digital circuit, simplified in the circuit constitution and reduced in the circuit scale by simplifying processing and a filtering method. SOLUTION: In the filtering method, a region to be processed by a media filter is moved, and the histogram of pixels newly added to the region is calculated, and stored in a partial histogram memory 203A. The data of partial histogram memories 203B-203F corresponding to each column are successively shifted so that the data of pixels removed from the region are stored in the partial histogram memory 203F. Those data are added and subtracted so that the data of a history memory 2 can be updated, and the updated histogram data are cumulatively added in the order of the size so that a median can be calculated by a median selection adding circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an image filter circuit and an image filtering method using a median filter, and more particularly to an image filter circuit and an image filtering method using a median filter for removing isolated noise in digital image processing. It is about.

[0002]

2. Description of the Related Art A median filter is known as an image filter for removing spike-like solitary noise from a digital image in which each pixel is represented by multi-values without losing important information such as edges.

The median filter sets a matrix-like window on the original image as an area including a pixel of interest and its surrounding pixels, sorts the values of the pixels in the window in ascending or descending order, and The value is replaced with the median of the pixel values.

When such a median filter is constituted by a digital circuit, a comparison circuit is generally used to compare the values of each pixel.

As a technique for constructing a median filter without using a comparison circuit, a one-dimensional image having a level of M ^1/2 is used for an image in which the pixel to be processed takes a value of 0 to 2 ^M -1. approach to configuring a median filter and a detailed table with the summary table and the magnitude of the vertical and horizontal M ^1/2 is described in Japanese Patent Laid-Open No. 5-233802.

[0006]

However, when a median filter is configured using a comparison circuit, the size of the window is reduced because the size of all pixels in the window to be processed is compared to determine the order. As the size increases, a large number of comparison circuits are required, resulting in a complicated circuit configuration.

Also, the method of rearranging the pixels in the window in ascending or descending order becomes more complicated as the size of the processing target window increases, and the circuit scale becomes enormous. Is very difficult.

On the other hand, the above publication does not describe a method of creating a summary table and a detail table and a method of setting data at the time of updating, and it is not clear how to realize the method. Further, it is impossible to realize such a method using hardware such as a digital circuit in terms of a circuit scale.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has been made in consideration of the above-described circumstances. It is an object to provide an image filter circuit and an image filtering method using a filter.

[0010]

An image filter circuit using a median filter according to the present invention, which achieves the above object, inputs the value of each pixel in an area including a pixel of interest and its surrounding pixels. An image filter circuit that obtains one frame of image data by moving a median filter that replaces a value of a pixel of interest with a median of values of pixels in the region in a predetermined direction, the histogram including a pixel value in the region. A histogram memory for storing the histogram memory for storing a value of a pixel newly added to the region and a value of a pixel excluded from the region by moving the median filter, and updating the data of the histogram memory. Median selection adding means for cumulatively adding the updated data in the histogram memory in order of size to obtain a median value That.

Further, in the image filtering method using a median filter according to the present invention, which achieves the above object, a value of each pixel in an area including a pixel of interest and its surrounding pixels is inputted, and the value of the pixel of interest is changed. An image filtering method for obtaining a frame of image data by moving a median filter that replaces a median value of pixel values in the region in a predetermined direction, wherein the histogram storage stores a histogram of pixel values in the region. Updating the histogram data by determining the value of a pixel newly added to the region and the value of a pixel excluded from the region by moving the median filter; and updating the histogram. A median selection addition step of obtaining a median by accumulatively adding the data in the memory in order of size.

That is, the median filter that outputs the median of the values of the pixels in the region is moved in a predetermined direction to
In an image filter circuit that obtains image data of a frame, by moving a region to be processed to data in a histogram memory that stores a histogram of pixel values in the region, the value of a pixel newly added to the region and The value of the pixel excluded from the region is obtained, and the histogram data is updated by adding and subtracting these data, respectively, and the updated histogram data is cumulatively added in order of size to obtain a median value.

With this configuration, it is not necessary to perform a comparison operation when obtaining the median value, and only a simple operation process of addition and subtraction is required. Therefore, the circuit configuration is simplified and the processing speed is also advantageous. It is. Also, even if the size of the area to be processed by the filter increases, it is sufficient to simply increase the size of the histogram memory according to the area.
It hardly affects the processing speed.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the principle of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a median filter of the present invention. As shown, the median filter of the present invention includes a histogram update circuit 1
, A histogram memory 2, and a median selection and addition circuit 3.

In FIG. 1, the input image data is
When the size of a matrix-like window, also called a “matrix to be processed”, is N × L (N and L are natural numbers), it is N pixel values for one row or one column.

FIG. 2 is a diagram showing an example of a matrix to be processed in the present invention. The matrix to be processed in the figure is 5 ×
5 and includes a target pixel at the center. The filtering process is performed by moving such a processing target matrix one pixel at a time in the horizontal or vertical direction so that all the pixels in one frame become the target pixel.

In the present invention, by moving the matrix to be processed in this way, the pixel value of one row or one column newly added to the matrix to be processed is used as input data.

Here, the processing range of the median filter is a matrix-shaped window, but the shape is not limited to the matrix, and may be different depending on the desired filtering effect or the like. Further, the position of the target pixel is not limited to the center of the processing target range.

The histogram updating circuit 1 updates the histogram memory 2 based on the value of each pixel in one row or one column of the input image data.

The histogram memory 2 is composed of a number of storage elements corresponding one-to-one with the possible values of each pixel. The maximum value that can be represented by each storage element constituting the histogram memory 2 is an integer equal to the number of pixels in the processing target matrix.

The median value selecting and adding circuit 3 cumulatively adds data stored in each storage element of the histogram memory 2 in ascending order or descending order, and the added value is equal to or larger than the central value of the number of pixels in the processing target matrix. Then, the value corresponding to the storage element is set as the output for the pixel of interest.

Such processing is sequentially performed by moving the processing target matrix one pixel at a time in a predetermined direction so that all the pixels in the frame become the target pixel.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram showing the configuration of the first embodiment of the median filter of the present invention.

Here, for convenience of explanation, the size of the matrix to be processed is represented by 5 × 5, and the value of each pixel of the original image is represented by 6 bits (0 to 63). It is assumed that it is moved in the direction to perform filtering processing.

The median filter of this embodiment is a histogram updating circuit 1 for obtaining a partial histogram for each column.
And a histogram memory 2 for storing a histogram of the entire processing target matrix obtained from the partial histogram
And a median selection / addition circuit 3 which calculates and outputs a median from the histogram of the entire processing target matrix.

The histogram updating circuit 1 decodes the value of each pixel of the input image data by decoding 6-bit data and validating and outputting any one of the 64 signal lines. 5 corresponding to each column
A total of six histogram storage units 203A to 203F for storing partial histograms, one each corresponding to a column newly added by movement, and an addition circuit 30 for adding histogram data of a newly added column
3, and a subtraction circuit 403 for subtracting histogram data of a column that is not included in the processing target matrix due to movement.
It has.

FIG. 4 is a diagram showing a more detailed circuit configuration of the decoder 103 and the histogram storage unit 203A.
With reference to this figure, how to obtain a partial histogram from the input image data will be described.

The data of the five pixels which have newly become elements of the matrix by moving the processing target matrix set on the original image are input to the decoder 103,
The signals are input to the To64 decoder unit 104, respectively. Each of the five decoder units 104 has 64 1-bit outputs, and all 64 × 5 = 320 lines are input to the histogram storage unit 203A.

In the histogram storage unit 203A, outputs indicating the same value output from the five decoder units 104 are added by four adders, and input to the storage element 204 corresponding to each value, such as a flip-flop. Is done. Thus, the distribution of the five data newly added to the processing target matrix is stored in the histogram storage unit 20.
Set to 3A.

FIG. 4 shows only the fifteenth output among the sixty-four outputs from the five decoders in the decoder unit 103. However, the other outputs are similarly added, and then the corresponding storage elements 204 are output. Is input to That is, in the case of this example, since the pixel value can take 64 values from 0 to 63, the histogram storage unit 203A stores 64 storage elements 2
04. The number of bits that can be stored in each storage element 204 may be a number that can represent the number of pixels in one column of the processing target matrix. In this case, the number of pixels in one column is five.
Therefore, the width is 3 bits.

The histogram storage units 203B to 203F
Is a configuration in which four adders are removed from the histogram storage unit 203A, and all have the same configuration having 64 storage elements 204. Each time the matrix to be processed moves, the data in each histogram storage unit
203F data for 203F, 203D for 203E
Is sequentially shifted to the histogram storage unit on the right side in the figure and overwritten.

As described above, the histogram storage unit 203A
When each of the data of .about.203F is shifted, the data of the histogram storage unit 203F becomes data of a column which is not included in the processing target matrix due to the movement.

Accordingly, the histogram memory 2 storing the histogram of the processing target matrix before the movement is
203 which is the histogram data of the newly added column
When the data of A is added and the data of 203F is subtracted,
A histogram of the pixel values in the current processing target matrix is obtained.

Here, the histogram storage units 203A to 203A-2
The number of storage elements in 03F is 64, which is the number of possible pixel values, and the bit width is 3 bits that can represent 5 pixels in one column. However, the configuration of the storage elements in the histogram memory 2 is as follows. The number is the histogram storage unit 20
Similarly to 3A to 203F, there are 64 bits, and the bit width is a 6-bit width capable of expressing 25 pixels in the processing target matrix.

The data in the histogram storage unit 203A is
In the adding circuit 303, the output is simply added to the output of the histogram memory 2. The output from the addition circuit 303 is subtracted by the subtraction circuit 403 from the data in the histogram storage unit 203F. The output of the subtraction circuit 403 is input to the histogram memory 2.

As described above, in the present embodiment, the number of storage elements in the histogram storage units 203A to 203F is equal to the number of storage elements in the histogram memory 2, and the contents correspond to one to one. The addition and the subtraction can be simply performed as follows.

FIG. 5 is a diagram showing the above addition and subtraction processing by focusing on data from the fifteenth and sixteenth storage elements of the histogram storage units 203A and 203F.

The data of the fifteenth storage unit 204 (A15) of the histogram storage unit 203A is added to the data of the fifteenth storage element 305 (G15) of the histogram memory 2 by the fifteenth adder of the addition circuit 303. From the addition result, the data of the fifteenth storage element 204 (F15) of the histogram storage unit 203F is stored in the subtraction circuit 403.
The subtraction is performed by the fifth subtractor, and the subtraction result is overwritten and stored in the fifteenth storage element 305 (G15) of the histogram memory 2.

The updated data of the fifteenth storage element 305 (G15) of the histogram memory 2 is cumulatively added with the data of the fourteenth storage elements of the histogram memory 2 by the adder of the median selection and addition circuit 3. It is added to the signal GADD (14) representing the result, and GADD (15)
Becomes

Similarly, the histogram storage unit 203
The data of the 16th storage unit 204 (A16) of A is added to the data of the 16th storage element 305 (G16) of the histogram memory 2 by the 16th adder of the addition circuit 303, and the histogram storage is performed based on the addition result. The data of the 16th storage element 204 (F16) of the section 203F is subtracted by the 16th subtractor of the subtraction circuit 403, and the subtraction result is stored in the 16th storage element 305 (G
16) is overwritten and stored.

Then, the updated histogram memory 2
The data of the sixteenth storage element 305 (G16) is stored in the histogram memory 2 by the adder of the median selection and addition circuit 3.
Is added to a signal GADD (15) representing the result of cumulative addition of the data of the storage elements up to the fifteenth storage element.
(16).

As described above, the corresponding storage element 20
By simply adding and subtracting the data of 4 and 305, the histogram data of the pixel values in the processing target matrix is calculated as
It can be updated with the movement of the processing target matrix. Since the creation and update of the histogram can be performed only by addition and subtraction, the circuit configuration becomes very simple, which is advantageous in terms of processing speed.

The histogram storage unit 2 in the present embodiment
The number 03 is equal to the number of columns of the matrix to be processed + 1, which is 6 in the above example. However, if the processing of the addition circuit and the decoder unit 103 inside the histogram storage unit 203A can be performed in one stage, the circuit configuration can be further simplified by eliminating the histogram storage unit 203A.

Next, the configuration of the median selection and addition circuit 3 will be described. The histogram memory 2 stores the distribution of pixel values in the matrix to be processed by the above-described processing. Therefore, the median value can be obtained by adding the pixel value distribution in order from the minimum value or the maximum value to obtain the accumulated value.

As described above with reference to FIG. 5, by sequentially adding the outputs from the storage elements 305 constituting the histogram memory 2 by the adder, a signal GADD representing the cumulative addition result is obtained.

FIG. 6 is a diagram showing an internal configuration of the median value selection adding circuit 3. As shown in FIG. However, the portion for obtaining the cumulative addition shown in FIG. 5 is omitted. From the signal GADD (0) representing the number of pixels having the pixel value 0 to the number of pixels from the signal GADD (0) to the pixel value 63 (resulting in 25 as the total number of pixels in the processing target matrix)
Are input to the median value selection circuit 106 up to a signal GADD (63) representing

The median selection circuit 106 determines which signal contains the 13th pixel value, which is the center of the number of 25 pixels, from the 64 signals representing the cumulative addition result. In order to determine which signal the median value is included in, a first step of sequentially determining the signal corresponding to the minimum pixel value 0 to the signal corresponding to the pixel value 31 in ascending order, and the maximum pixel value 63 And a second step of sequentially determining in descending order from the signal corresponding to pixel signal 32 to the signal corresponding to pixel value 32.

At each stage, a signal including the median is specified under the following two conditions.

The first judgment condition is as follows: It is.

Where I is an integer from 0 to 31;
TEMP (I) is an internal signal of the median value selection circuit 106. This TEMP (I) (I = 0 to an integer of 0 to 31) is determined under the following second determination condition.

That is, IF (TEMP (L) = '0' and TEMP (L + 1) = '1') THEN X (L) <= '1'; ELSE X (L) <= '0'; END IF; It is.

Here, L = I-1 (L = 0 to 31), and X (L) is an output signal of the median value selection circuit 106.

A signal X (L) corresponding to pixel values 0 to 31 is obtained according to the first and second determination conditions. Similarly, as the second stage, the maximum pixel value 6
3 from the signal corresponding to the pixel value 32 by the first and second determination conditions.
(L) is obtained.

When the signal including the median is specified in the first stage, all signals X (32) to X (63) are set to 0.
The second step may be omitted. Also, taking into account that the pixel value does not change abruptly except at the edge of the image, the signal X for the immediately preceding processing target matrix is considered.
(L) will be implemented from the stage when it becomes 1,
If a signal including the median is specified, the other step may be omitted.

FIG. 7 is a diagram showing a detailed configuration of the address output circuit 206. The address output circuit 206 receives the output signals X (0) to X (63) of the median value selection circuit 106 as inputs, and outputs a value corresponding to the median value of the pixel values in the processing target matrix as the final output of the median filter. I do.

The output signal X of the median value selection circuit 106 is X
(0) is MUX0 indicated by 107, X (1) is 207
6 corresponding to MUX1 indicated by
The selection signal is input to one of the four multiplexers. A pixel value corresponding to 0 is input to each multiplexer, and when the selection signal X becomes 1, the pixel value is output.

There is only one selection signal X having a value of 1 corresponding to the matrix to be processed at a certain point in time. Therefore,
The final output of the median filter is obtained by ORing the outputs of the multiplexers.

Hereinafter, a second embodiment of the median filter according to the present invention will be described. FIG. 8 is a diagram showing a schematic circuit configuration of the present embodiment. However, the processing target matrix size of the median filter and the number of bits of the pixel value are the same as in the first embodiment.

The present embodiment is different from the first embodiment only in the configuration of the histogram updating circuit 1, and the description of the histogram memory 2 and the median selection adding circuit 3 is omitted.

In this embodiment, the five pixel values of the column newly included in the input matrix to be processed are first input to the same value determination circuit 108, and it is determined how many pieces of the same data exist. This same value determination circuit 108
Calculates the AND of the pixel values for all combinations of the five input pixel values, and determines how many combinations of the same data exist. As output, information about data having the largest number determined to be the same is sent to each of the adders 308 to 708.

FIG. 9 is a diagram showing a detailed circuit configuration of the adders 308 to 708. The types of signals input to the addition circuit 708 are a 6-bit signal representing a pixel value and a 3-bit signal representing the same data number.

The pixel value is input to the decoder 209,
One signal corresponding to the input pixel value is selected from 64 signals. The value represented by the output signal and the signal from the histogram memory 2 are input to the gate 709, and the number of data having the same pixel value is output. And with the internal adder,
The number of data in the newly added column is added to the number of data stored in the histogram memory 2 and output.

Here, the adder circuit 708 shown in the upper part of FIG.
, The value having the largest number of data among the five pixel values and the number of data are input. Addition circuits 608 to 308 have 2
The fifth to fifth largest values and the number of data are input.

In this embodiment, since the number of pixels in one column is five, if the number of identical data is five, the addition circuit 70
Valid data is input to only 8, and the processing in other adders is not required. When the same data number is 4, valid data is input to the adders 708 and 608.

Even if various combinations of five pixel values are considered, the maximum number of data input to the adders 308 to 508 is one. Therefore, in the present embodiment, the addition circuit 3
The number of data is not input to 08 to 508, and a constant 1 is added by an internal adder.

As described above, depending on the combination of the five pixel values, valid data may not be input to the adders 608 to 308. In order to cope with such a double, the identical value determination circuit 108 has a Valid output, and when the value of the Valid output input to each of the multiplexers 1209 to 1509 is 1, the value of the histogram memory 2 is Is output as it is.

In the present embodiment, the delay circuit 208 is provided as shown in FIG.
The processing steps are delayed by the number corresponding to the columns of the matrix to be processed, for the signal input to 8. Therefore, the signals input to the addition circuits 308 to 708 in the processing corresponding to the five previous columns are input to the subtraction circuits 808 to 1208 as they are.

The same processing as that performed by the above-described addition circuits 308 to 708 is performed by the subtraction circuits 808 to 1208, and the subtraction result is input to the histogram memory 2 to update the stored contents.

With the above configuration, the histogram data of the pixel values in the processing target matrix can be updated as the processing target matrix moves. Since the creation and update of the histogram can be performed only by addition and subtraction, the circuit configuration becomes very simple, which is advantageous in terms of processing speed.

This embodiment is advantageous in that the processing is particularly simple for image data having many pixels having the same value.

Here, the processing of the median filter of the present invention will be described again with reference to the flowchart of FIG.

First, in step S1, data of one column of pixel values newly processed in the processing target matrix is processed so as to facilitate the calculation in the subsequent process. This process is to create a histogram for one column in the first embodiment, and is a process in the same value determination circuit in the second embodiment.

In step S2, data to be newly processed is added to the histogram memory. This is performed by an adder circuit denoted by reference numeral 303 in the first embodiment, and denoted by reference numerals 308 to 708 in the second embodiment.

In step S3, the data excluded from the processing target is subtracted from the histogram memory. This is performed by an adder circuit indicated by 403 in the first embodiment and indicated by 808 to 1208 in the second embodiment.

The processing of steps S1 to S3 is performed by the histogram updating circuit 1 of the present invention.

In step S4, the updated data in the histogram memory 2 is cumulatively added in ascending order or descending order in order of magnitude to obtain data of the cumulative number up to each pixel value.
In the first and second embodiments, this is performed in the portion shown in FIG. 5 of the median selection and addition circuit.

In step S5, a median value is output as a final output value of the median filter based on the accumulated data. In the first and second embodiments, this is performed by the portion shown in FIGS. 6 and 7 of the median selection and addition circuit.

With the above processing, the median can be obtained by a simple processing of adding and subtracting only the data relating to the updated portion of the processing target matrix.

The present invention can be applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), but can be applied to a single device (for example, a copier, a facsimile). Device).

Further, an object of the present invention is to supply a storage medium (or a recording medium) recording software program codes for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer (a computer) of the system or the apparatus. It is needless to say that the present invention can also be achieved by a CPU or an MPU) reading and executing the program code stored in the storage medium. In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. Also,
When the computer executes the readout program code, not only the functions of the above-described embodiments are realized, but also the operating system (OS) running on the computer based on the instructions of the program code.
It is needless to say that a case in which the functions of the above-described embodiments are implemented by performing part or all of the actual processing.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer, the program code is read based on the instruction of the program code. Needless to say, the CPU included in the function expansion card or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

When the present invention is applied to the storage medium, the storage medium stores program codes corresponding to the above-described flowchart (shown in FIG. 10).

[0085]

As described above, according to the present invention,
When calculating the median, there is no need to perform a comparison operation, and only a simple operation process of addition and subtraction is required, so that the circuit configuration is simplified and the processing speed is also advantageous. Further, even if the size of the area to be processed by the filter is increased, it is sufficient to increase the size of the histogram memory according to the area, and there is an effect that the processing speed is hardly affected.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a median filter of the present invention.

FIG. 2 is a diagram for explaining a matrix to be processed by a median filter in FIG. 1;

FIG. 3 is a diagram showing a circuit configuration of a first embodiment of a median filter of the present invention.

FIG. 4 is a detailed circuit diagram of a decoder unit 103 and a histogram storage unit 203A of FIG.

FIG. 5 is a detailed circuit diagram of an addition circuit 303, a subtraction circuit 403, and a histogram memory 2 of FIG.

FIG. 6 is a diagram showing a configuration of a median selection and addition circuit 3 of FIG. 3;

FIG. 7 is a detailed circuit diagram of the address output circuit 206 of FIG.

FIG. 8 is a diagram showing a circuit configuration of a second embodiment of the median filter of the present invention.

9 is a circuit diagram of the adders 308 to 708 in FIG.

FIG. 10 is a flowchart showing processing in the median filter of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Histogram update circuit 2 Histogram memory 3 Median value selection and addition circuit 103 Decoder unit 104 Decoder 203A-203F Histogram storage unit 204, 305 Storage element 303 Addition circuit 403 Subtraction circuit 106 Median value selection circuit 206 Address output circuit 107, 207 Multiplexer 307 OR Circuit 108 Same value determination circuit 208 Delay circuit 308 to 708 Addition circuit 808 to 1208 Subtraction circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) PQ08 PQ12 PQ19 PQ20 PQ22 RR16

Claims (14)

[Claims] 1. A median filter that inputs a value of each pixel in a region including a target pixel and its surrounding pixels and replaces the value of the target pixel with a median value of pixels in the region in a predetermined direction. An image filter circuit that obtains image data of one frame by moving the median filter; and a histogram memory that stores a histogram of pixel values in the area; and a pixel newly added to the area by moving the median filter. Histogram updating means for calculating the value of the histogram memory and the value of the pixel excluded from the area, and updating the data of the histogram memory. An image filter circuit comprising: a selection adding unit. 2. The histogram updating means according to claim 1, wherein: an adding circuit for adding a value of a pixel newly added to said area to data of said histogram memory; 2. The image filter circuit according to claim 1, further comprising: a subtraction circuit for subtracting from the image signal. 3. The image filter circuit according to claim 1, wherein the histogram updating unit includes a partial histogram creating unit that creates a histogram of pixel values newly added to the area. . 4. The apparatus according to claim 1, wherein said histogram updating means includes an identical value judging means for outputting, when there is a pixel having the same value among the pixels newly added to said area, the value and the number thereof. 3. The image filter circuit according to 1 or 2. 5. The histogram updating means has a plurality of partial memories for storing data relating to pixels newly added to the area, and the number of the partial memories is determined when the median filter is moved. 5. The image filter according to claim 1, wherein when the data of the partial memory is sequentially shifted, data on a pixel excluded from the area is obtained. 6. circuit. 6. The histogram updating means according to claim 1, wherein said data relating to a pixel newly added to said area is a pixel which is newly excluded from said area due to movement of said median filter. The image filter circuit according to any one of claims 1 to 4, further comprising a delay unit for delaying the image filter. 7. The image filter circuit according to claim 1, wherein the area is a rectangular matrix. 8. The image filter circuit according to claim 7, wherein the pixel of interest is located at the center of the area. 9. A median filter that inputs a value of each pixel in an area including a target pixel and its surrounding pixels and replaces the value of the target pixel with a median value of the pixels in the area in a predetermined direction. And a histogram storing step of storing a histogram of pixel values in the region, and a median filter newly added to the region by moving the median filter. A histogram update step of obtaining the value of a pixel and the value of a pixel excluded from the region to update the data of the histogram; An image filtering method, comprising: a selection addition step. 10. The histogram updating step includes an adding step of adding a value of a pixel newly added to the area to the histogram data, and subtracting a value of a pixel excluded from the area from the histogram data. The image filtering method according to claim 9, further comprising: performing a subtraction step. 11. The image filtering method according to claim 9, wherein the histogram updating step includes a partial histogram creating step of creating a histogram of pixel values newly added to the area. . 12. The histogram updating step includes an identical value determining step of outputting a value and the number of pixels having the same value among pixels newly added to the area when the pixel has the same value. The image filtering method according to 9 or 10. 13. The partial histogram updating step includes a partial storing step of storing data relating to a pixel newly added to the area in one of a plurality of partial memories. 13. The method according to claim 9, wherein the number is a number by which data relating to a pixel excluded from the area is obtained when data in the partial memory is sequentially shifted with movement of the median filter. The image filtering method according to claim 1. 14. The histogram updating step may include, for the data relating to a pixel newly added to the region, a pixel newly added to the region being a pixel excluded from the region by the movement of the median filter. The image filtering method according to any one of claims 9 to 12, further comprising a delay step of delaying the image filtering.