JP2000295093A - Semiconductor integrated circuit - Google Patents

Abstract

(57) Abstract: A semiconductor integrated circuit capable of obtaining a comparison circuit with sufficient circuit calculation accuracy with a circuit scale that can be introduced into pixels of an image sensor and reducing cost. provide. SOLUTION: Seven MOS transistors 31 to 34,
36 to 38 or 6 MOS transistors 31 to 3
4, 37, 38 and one resistor 39 form a comparison circuit for comparing two input voltages whose output voltage is maximum or minimum only when the two input voltages are equal. A comparison circuit capable of accurately performing the comparison operation of the two pieces of image data with a simple circuit configuration is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a comparison circuit for comparing electric signals.

[0002]

2. Description of the Related Art At present, markets for monitoring devices and game machine interfaces using image recognition are rapidly expanding, and image sensors suitable for high-speed image recognition are being manufactured. As these image sensors, for example, Japanese Patent Application Laid-Open No. 1-12
Japanese Patent No. 4075 discloses a semiconductor integrated circuit device capable of combining a photosensor, a memory cell, and a comparison circuit and comparing and collating incident image data with a pattern stored in the device in advance for all pixels in parallel. Have been.

As a comparison circuit, Japanese Patent Laid-Open Publication No.
In Japanese Patent No. 24075, an exclusive OR gate is used. On the other hand, assuming that the comparison circuit is formed by an analog circuit, the “analog VLSI and neural system” (1)
993) Pages 99 to 101 issued by Toppan Co., Ltd.
There is an absolute value circuit described on the page.

[0004]

SUMMARY OF THE INVENTION However, Japanese Patent Laid-Open Publication No. 1-1
The comparison circuit disclosed in Japanese Patent No. 24075 has a problem that sufficient accuracy cannot be obtained because the operation accuracy is 1 bit, and the circuit scale becomes large and the cost increases when the number of bits is increased. Further, since the absolute value circuit as described above has a large circuit scale, there is a problem that the image sensor becomes too large when introduced into each pixel.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has provided a comparison circuit which can obtain sufficient comparison calculation accuracy with a circuit scale that can be introduced into the pixels of an image sensor. It is an object of the present invention to obtain a semiconductor integrated circuit which can be obtained and can reduce the cost.

[0006]

SUMMARY OF THE INVENTION A semiconductor integrated circuit according to the present invention is provided with a comparison circuit for comparing two input voltages and outputting the comparison result. When the voltages are equal, the output voltage becomes the minimum, and as the voltage difference between the two input voltages increases, the output voltage becomes larger than the minimum value.

Further, a semiconductor integrated circuit according to the present invention comprises:
In a semiconductor integrated circuit including a comparison circuit that compares two input voltages and outputs the comparison result, the comparison circuit includes:
The output voltage is maximum when the two input voltages are equal,
The output voltage becomes smaller than the maximum value as the voltage difference between the two input voltages increases.

Further, a semiconductor integrated circuit according to the present invention comprises:
In any one of claims 1 and 2, the comparison circuit converts an output voltage corresponding to a voltage difference between two input voltages into a current corresponding to the voltage value and outputs the current.

Further, a semiconductor integrated circuit according to the present invention comprises:
4. The voltage difference detection device according to claim 1, wherein the comparison circuit outputs a voltage corresponding to a voltage difference between the two input voltages and outputs a predetermined voltage Va when the two input voltages are equal. Circuit, when the voltage output from the voltage difference detection circuit is a predetermined voltage Va, the output voltage becomes minimum, and as the voltage output from the voltage difference detection circuit becomes smaller or larger than the predetermined voltage Va, And a predetermined voltage detection circuit whose output voltage becomes larger than the minimum value.

Further, a semiconductor integrated circuit according to the present invention comprises:
The voltage difference detection circuit according to claim 2 or 3, wherein the comparison circuit outputs a voltage corresponding to a voltage difference between the two input voltages and outputs a predetermined voltage Va when the two input voltages are equal. Circuit, when the voltage output from the voltage difference detection circuit is a predetermined voltage Va, the output voltage becomes maximum, and as the voltage output from the voltage difference detection circuit becomes smaller or larger than the predetermined voltage Va, And a predetermined voltage detection circuit whose output voltage becomes smaller than the maximum value.

Further, a semiconductor integrated circuit according to the present invention comprises:
The comparison circuit according to claim 4, wherein the comparison circuit includes a voltage-current conversion circuit configured to convert a voltage output from the predetermined voltage detection circuit into a current corresponding to the output voltage value and output the converted current. is there.

Further, a semiconductor integrated circuit according to the present invention is
In claim 6, the voltage-current conversion circuit controls output of the converted current according to a predetermined signal from the outside.

Further, a semiconductor integrated circuit according to the present invention is
In any one of claims 4 to 7, the predetermined voltage detection circuit has an adjustment circuit that adjusts an output voltage with respect to the voltage input from the voltage difference detection circuit.

Further, a semiconductor integrated circuit according to the present invention is
In any one of claims 4 to 8, the comparison circuit includes a Va adjustment circuit that adjusts a variation in the predetermined voltage Va output from the voltage difference detection circuit and outputs the result to the predetermined voltage detection circuit.

Further, a semiconductor integrated circuit according to the present invention comprises:
The voltage difference detection circuit according to any one of claims 4 to 9, wherein the voltage difference detection circuit outputs a voltage corresponding to a voltage difference between the two input voltages to the predetermined voltage detection circuit in response to a predetermined signal input from the outside. And a switching circuit for switching between a current obtained by converting each of the two input voltages into a current value corresponding to each of the voltage values to an external output.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. Embodiment 1 FIG. FIG. 1 is a schematic block diagram showing an example of a semiconductor integrated circuit according to the first embodiment of the present invention.
FIG. 1 shows an example of a semiconductor integrated circuit element serving as an image sensor for detecting a change in an image.

In FIG. 1, a semiconductor integrated circuit device 1 comprises:
A photoelectric conversion circuit 2 that converts an image into electrical signal data and outputs the signal; a first memory 3 and a second memory 4 that store image data input from the photoelectric conversion circuit 2; A comparison circuit that compares the stored data with the data stored in the second memory and outputs the comparison result
It is composed of

The photoelectric conversion circuit 2 includes a first memory 3 and a second memory 3.
The first memory 3 and the second memory 4 are respectively connected to the memory 4 and the comparison circuit 5. Further, the photoelectric conversion circuit 2 is connected to a reset terminal R to which a reset signal is inputted from the outside, and the first memory 3
Is connected to an input terminal W1 to which a signal for performing data writing control is externally input, and the second memory 4 is connected to an input terminal W2 to which a signal for performing data writing control is externally input. ing.

In such a configuration, the photoelectric conversion circuit 2
Is alternately stored in the first memory 3 and the second memory 4 by alternately inputting a write enable signal from the outside to the input terminals W1 and W2. The comparison circuit 5 compares the data stored in the first memory 3 with the data stored in the second memory 4,
The comparison result is output to the outside.

FIG. 2 is a diagram showing a circuit example of the photoelectric conversion circuit 2 of FIG. 2, the photoelectric conversion circuit 2 includes a photodiode 11 and an N-channel MOS transistor (hereinafter, referred to as an N-MOS) 12.
In the photodiode 11, the cathode is connected to a power supply terminal Vdd to which a positive DC power supply voltage is input from the outside, the anode is connected to the drain of the N-MOS 12,
The connection is connected to the output terminal 13. N-MOS
At 12, the source is grounded and the gate is connected to the reset terminal R.

In such a configuration, the reset terminal R
When a high-level reset signal is input from the outside to the N-MO
S12 is turned on to be in a conductive state, and a reset operation for setting the output terminal 13 to the ground level is performed. When the reset operation is not performed, the reset terminal R is at the low level, and the N-MOS 12 is turned off to be in the cutoff state.

FIG. 3 is a diagram showing a circuit example of the first memory 3 and the second memory 4. As shown in FIG. Note that the first memory 3 and the second memory 4 are the same circuit, and the case of the first memory 3 will be described as an example in FIG. In FIG. 3, the first memory 3 is formed by a write gate 15 and a memory capacitor 16. When a High-level signal is input to the input terminal W <b> 1, the first memory 3 is connected to the photoelectric conversion circuit 2 via the input terminal 17.
Is charged in the memory capacity 16. The charged voltage is applied to one input terminal of the comparison circuit 5 via the output terminal 18.

FIG. 4 is a schematic block diagram showing a configuration example of the comparison circuit 5 of FIG. In FIG. 4, the comparison circuit 5
Is a predetermined constant voltage Va when two input voltages are equal.
And a predetermined voltage detection circuit 22 that outputs a minimum value when the predetermined voltage Va is input.
And formed.

The voltage difference detection circuit 21 has two input terminals IN1 and IN2 to which voltages are respectively inputted from outside, and an output terminal is connected to an input terminal of the predetermined voltage detection circuit 22. The output forms the output OUT of the comparison circuit 5. Only when the input voltages input to the two input terminals IN1 and IN2 are equal to each other, the voltage difference detection circuit 21 determines the predetermined voltage V regardless of the voltage value of the input voltage.
a is output. Here, the voltage input to the input terminal IN1 is, for example, storage data output from the first memory 3, and the voltage input to the input terminal IN2 is, for example, storage data output from the second memory 4. It is.

The predetermined voltage detection circuit 22 outputs the minimum output voltage only when the voltage input from the voltage difference detection circuit 21 is the predetermined voltage Va. As the voltage becomes smaller than the predetermined voltage Va, the output voltage becomes smaller than the minimum value. As the voltage becomes higher, the output voltage becomes higher than the minimum value as the output voltage becomes higher.

FIG. 5 is a diagram showing a circuit example of the comparison circuit 5 shown in FIG. In FIG. 5, the voltage difference detection circuit 21
Are four P-channel MOS transistors (hereinafter P
-MOS) 31-34, and PM
The OSs 31 and 32 form a current mirror circuit and form a current source. The gate of the P-MOS 33 is connected to the input terminal I.
The gate of the P-MOS 34 is connected to the input terminal IN2 at N1.

The gates of the P-MOSs 31 and 32 are connected, and the gate and drain of the P-MOS 31 are connected. In the P-MOS 31, the source is the power supply terminal V
dd, the drain is connected to the source of the P-MOS 33, and the drain of the P-MOS 33 is grounded. In the P-MOS 32, the source is connected to the power supply terminal Vdd, the drain is connected to the source of the P-MOS 34, and the drain of the P-MOS 34 is grounded. In such a configuration, the connection A between the drain of the P-MOS 32 and the source of the P-MOS 34 forms the output of the voltage difference detection circuit 21 and the predetermined voltage detection circuit 22
It is connected to the.

The predetermined voltage detection circuit 22 has two P-MOs.
S36, S37, N-channel MOS transistor 38
And formed. In the P-MOS 36, the source is connected to the power supply terminal Vdd, the gate is connected to the bias input terminal IN3 to which a predetermined bias voltage is applied from the outside, and the drain is connected to the source of the P-MOS 37. The output of the circuit 22 is connected to the output terminal OUT of the comparison circuit 5. Also, P-MO
The gates of the S37 and the N-MOS 38 are connected to the connection portion A, respectively, and the P-MOS 37 and the N-MOS 3
8 are connected, and the source of the N-MOS 38 is grounded.

In such a configuration, the input terminal IN1
And the input voltage input to IN2 is converted into a current value corresponding to the input voltage value by P-MOSs 33 and 34, and the P-M
The subtraction is performed by the mirror circuit formed by the OSs 31 and 32. In this way, the voltage difference detection circuit 21 determines that the voltage of the connection portion A that makes an output is a predetermined value only when the respective input voltages input to the input terminals IN1 and IN2 are equal, regardless of the voltage value of each input voltage. It becomes the value Va.

On the other hand, when the connection portion A reaches the predetermined voltage Va,
P-MOS 37 and N-MOS 3 connected to connection A
8 so that the series circuit of FIG.
The gain coefficients of the MOSs 31 to 34 are set. For example, the gain coefficient of the P-MOS 31 is β31,
2 is β32, and the gain coefficient of the P-MOS 33 is β
Assuming that the gain coefficients of 33 and P-MOS 34 are β34,
The P-MOSs 31 to 34 are formed such that the gain coefficients β31 to β34 are as follows: β31: β32: β33: β34 = 1: 4: 1: 1 (1)
By doing so, the current flowing through the series circuit of the P-MOS 37 and the N-MOS 38 becomes smaller than the maximum current whether the voltage at the connection portion A is lower or higher than the predetermined voltage Va.

The P-MOS 36 is connected to the input terminal IN3
Can be regarded as having a constant resistance value between the source and the drain by a constant bias voltage input from the, and converts a current flowing through a series circuit of the P-MOS 37 and the N-MOS 38 into a voltage. From this,
When the voltage at the connection portion A reaches the predetermined value Va, the output terminal of the predetermined voltage detection circuit 22, ie, the output terminal OU of the comparison circuit 5,
The voltage of T becomes the minimum value, and the voltage of the connection A becomes the predetermined value Va.
As the voltage becomes larger or smaller, the voltage of the output terminal OUT increases from the minimum value.

As shown in FIG. 6, the P-MO of FIG.
S37 may be changed to an N-MOS and N-MOS 38 may be changed to a P-MOS. As shown in FIG.
6 may be replaced with a fixed resistor 39. As shown in FIG. 8, the gate of the P-MOS 36 in FIG.
The diode may be formed by connecting to the drain of 36.

Here, FIGS. 5 to 8 have described an example in which the predetermined voltage detection circuit 22 has a minimum output voltage only when the predetermined voltage Va is input from the voltage difference detection circuit 21. However, the predetermined voltage detection circuit 22 has the maximum output voltage only when the predetermined voltage Va is input from the voltage difference detection circuit 21, and the voltage input from the voltage difference detection circuit 21 becomes smaller than the predetermined voltage Va. As the output voltage becomes smaller than the maximum value, the output voltage becomes smaller than the maximum value as the output voltage becomes larger than the output voltage Va. FIG. 9 shows a circuit example of the predetermined voltage detection circuit 22 having such characteristics.

The difference between FIG. 9 and FIG. 5 is that in FIG. 5, the P-MOS 37 and the N-MOS 38 are connected in series, and the series circuit is connected between the output terminal OUT and the ground. However, in FIG. 9, the P-MOS 37 and the N-MO
S38 is connected in parallel, and the parallel circuit is connected to the output terminal OUT.
And the ground. That is, in FIG. 9, the source of the P-MOS 37 and the N-M
The drain of the OS 38 is connected to the drain of the P-MOS 36 and to the output terminal OUT. Further, the drain of the P-MOS 37 and the N-
The source of the MOS 38 is grounded. By doing so, the output voltage of the predetermined voltage detection circuit 22 becomes the maximum value only when the predetermined voltage Va is input from the voltage difference detection circuit 21.

As described above, the semiconductor integrated circuit according to the first embodiment has seven MOS transistors 31-34.
36 to 38 or 6 MOS transistors 31 to 3
4, 37, 38 and one resistor 39 form a comparison circuit for comparing two input voltages whose output voltage is maximum or minimum only when the two input voltages are equal. From this, it is possible to obtain a comparison circuit capable of accurately performing a comparison operation of two image data obtained from the photoelectric conversion circuit 2 with a simple circuit configuration, and to introduce the comparison circuit into the pixels of the image sensor. And cost can be reduced.

Embodiment 2 In the first embodiment, the comparison circuit 5 sets the output voltage to be the maximum or the minimum only when the two input voltages are equal. However, the output current becomes the maximum or the minimum only when the two input voltages are equal. Such a configuration may be used in Embodiment 2 of the present invention.
And

FIG. 10 is a schematic block diagram showing a configuration example of a comparison circuit of a semiconductor integrated circuit according to the second embodiment of the present invention. Note that a schematic block diagram showing an example of a semiconductor integrated circuit according to the second embodiment of the present invention includes a semiconductor integrated circuit element 1 of FIG. 1 as a semiconductor integrated circuit element 41, and a comparison circuit 5 of FIG. Since it is the same as FIG. In FIG. 10, the same components as those in FIG. 5 are denoted by the same reference numerals, and the description thereof will be omitted, and only the differences from FIG. 5 will be described.

FIG. 10 differs from FIG. 5 in that a voltage-current conversion circuit 43 is added to the comparison circuit 5 of FIG. 5, and accordingly, the comparison circuit 5 of FIG.
And that In FIG. 10, the comparison circuit 42
Voltage difference detection circuit 21, predetermined voltage detection circuit 22, and voltage-
It is formed by a current conversion circuit 43. The output of the predetermined voltage detection circuit 22 is connected to the input of the voltage-current conversion circuit 43, and the output of the voltage-current conversion circuit 43 forms the output OUT of the comparison circuit 42. Voltage-current conversion circuit 4
Reference numeral 3 converts a voltage output from the predetermined voltage detection circuit 22 into a current corresponding to the voltage. That is, when the output voltage from the predetermined voltage detection circuit 22 is minimum, the output current of the voltage-current conversion circuit 43 becomes maximum, and the output voltage from the predetermined voltage detection circuit 22 increases and the output current decreases.

FIG. 11 is a diagram showing a circuit example of the comparison circuit 42 shown in FIG. 11, the same components as those in FIG. 5 are denoted by the same reference numerals, and the description thereof will be omitted, and only the differences from FIG. 5 will be described. 11 differs from FIG. 5 in that the voltage of the P-MOS 45
That is, the current conversion circuit 43 is added.

In FIG. 11, the connection between the drain of the P-MOS 36 and the source of the P-MOS 37 is a P-MOS
The source of the P-MOS 45 is connected to the power supply terminal Vdd. The drain of the P-MOS 45 forms the output of the voltage-current conversion circuit 43 and the output of the comparison circuit 42, and the output terminal OU of the comparison circuit 42.
Connected to T. In such a configuration, PM
The OS 45 converts the voltage output from the predetermined voltage detection circuit 22 into a current corresponding to the voltage and outputs the current from the output terminal OUT.

In the second embodiment, the comparison circuit of the first embodiment shown in FIG.
3 has been described as an example, but the present invention is not limited to this, and the voltage-current conversion circuit 43 may be provided in the comparison circuit shown in FIGS. Good. When the voltage-current conversion circuit 43 is provided in the comparison circuit shown in FIGS. 6 to 9, the voltage-current conversion circuit 43 is connected to the output of each predetermined voltage detection circuit. The description is omitted because it is the same. Further, by replacing the P-MOS 45 with an N-MOS, when the output voltage from the predetermined voltage detection circuit 22 is minimum, the output current of the voltage-current conversion circuit 43 becomes minimum, and the output voltage from the predetermined voltage detection circuit 22 is reduced. Increases, and the output current of the voltage-current conversion circuit 43 increases.

As described above, the semiconductor integrated circuit according to the second embodiment has eight MOS transistors 31-34.
36 to 38, 45, or seven MOS transistors 31
34, 37, 38, 45 and one resistor 39 form a comparison circuit for comparing two input voltages at which the output current is maximum or minimum only when the two input voltages are equal. From this, when the same effect as in the first embodiment can be obtained, and it is more efficient to output the comparison operation result as a current value due to the configuration of the external circuit when connecting to an external circuit, For example, addition of comparison operation results can be facilitated.

Embodiment 3 In the second embodiment, the adjustment of the current value to be output according to the result of the comparison operation can be performed to some extent at the manufacturing process stage. However, the output current may be adjusted even after the manufacturing. This is referred to as Embodiment 3 of the present invention. FIG.
FIG. 13 is a circuit diagram illustrating an example of a comparison circuit of a semiconductor integrated circuit according to a third embodiment of the present invention. A schematic block diagram showing an example of a semiconductor integrated circuit according to the third embodiment of the present invention includes a semiconductor integrated circuit element 51 of FIG. 1 as a semiconductor integrated circuit element 51, and a comparison circuit 5 of FIG. Since it is the same as FIG. In FIG. 12, the same components as those in FIG. 11 are denoted by the same reference numerals, and the description thereof will be omitted, and only the differences from FIG. 11 will be described.

The difference between FIG. 12 and FIG. 11 is that FIG.
The circuit configuration of the predetermined voltage detection circuit 22 is changed to a predetermined voltage detection circuit 55, and the circuit configuration of the voltage-current conversion circuit 43 of FIG. 11 is changed to a voltage-current conversion circuit 56. 12, a comparison circuit 52 includes a voltage difference detection circuit 21, a predetermined voltage detection circuit 55 whose output voltage is minimized when a predetermined voltage Va is input, and a predetermined voltage detection circuit 55.
And a voltage-current conversion circuit 56 for converting the voltage output from the to a current corresponding to the voltage.

The predetermined voltage detection circuit 55 outputs the minimum output voltage only when the voltage input from the voltage difference detection circuit 21 is the predetermined voltage Va. As the voltage becomes smaller than the predetermined voltage Va, the output voltage becomes smaller than the minimum value. As the voltage becomes higher, the output voltage becomes higher than the minimum value as the output voltage becomes higher. When the output voltage from the predetermined voltage detection circuit 55 is minimum, the voltage-current conversion circuit 56 has a maximum output current, and the output voltage from the predetermined voltage detection circuit 55 increases and the output current decreases.

The predetermined voltage detection circuit 55 includes a P-MOS 61
64 and N-MOSs 65-67. P
The voltage difference detection circuit 2 including the MOS 61 and the N-MOS 65
An adjustment circuit for adjusting the voltage input from 1 is formed. In the N-MOS 65, the drain is the power supply terminal V
dd, the gate is connected to a connection portion A serving as an output of the voltage difference detection circuit 21, and the source is a P-MOS 61
Connected to the source.

In the P-MOS 61, the drain is grounded, and the gate is connected to a bias input terminal IN3 to which a predetermined bias voltage is applied from the outside. P
The -MOS 61 can be regarded as having a constant resistance between the source and the drain by a constant bias voltage input from the input terminal IN3, and the N-MOS 65
The voltage difference detection circuit 21
The input voltage is adjusted by, for example, reducing the voltage input from the controller.

The source of the N-MOS 65 and the P-MOS 61
Are connected to the P-MOS 64 and the N-MOS
The voltage adjusted by the N-MOS 65 and the P-MOS 61 is input to the gates of the P-MOS 64 and the N-MOS 66, respectively. P-MOS
64 and the drain of the N-MOS 66 are connected, and the P-
The source of the MOS 64 is connected to the drain of the P-MOS 63. The source of the P-MOS 63 is a P-MOS
The connection portion is connected to a drain of the predetermined voltage detection circuit 55, and the connection portion is connected to the bias input terminal IN3.

The P-MOS 63 can be regarded as having a constant resistance between the source and the drain by a predetermined bias voltage input from the input terminal IN3. P
-The MOS 62 and the N-MOS 67 have their gates connected to the drain to form diodes, respectively.
The source of the OS 62 is connected to the power supply terminal Vdd, and the N-MO
The source of S67 is grounded.

In such a configuration, the P-MOS 63
5 is the P-MOS 36 of FIG. 5, and P-MOS 64 is the P-MOS
-MOS 37 and N-MOS 66 are the N-MOS 3 of FIG.
8 performs the same operation. On the other hand, in the voltage output to the voltage-current conversion circuit 56, the P-MOS 62
The upper limit is made smaller than the power supply voltage input from the power supply terminal Vdd, and the N-MOS 67 makes the lower limit larger than ground. Also, the bias input terminal I
By changing the bias voltage input to N3,
The voltage output from the predetermined voltage detection circuit 55 can be adjusted.

Next, the voltage-current conversion circuit 56 is formed by two P-MOSs 71 and 72. P-MOS
At 71, the source is at the power supply terminal Vdd and the drain is P
The gate of the MOS 72 is connected to the predetermined voltage detection circuit 5
5 are connected to the connection portions of P-MOSs 62 and 63, respectively. In the P-MOS 72, the gate is connected to the bias input terminal IN3, and the drain is connected to the output terminal OUT of the comparison circuit 52. P-MO
S71 performs the same operation as the P-MOS 45 of FIG. 11, and the P-MOS 72 can be regarded as having a constant resistance between the source and the drain by a constant bias voltage input from the input terminal IN3. .

By replacing the P-MOS 71 with an N-MOS, when the output voltage from the predetermined voltage detection circuit 55 is minimum, the output current of the voltage-current conversion circuit 56 is minimum and the predetermined voltage detection circuit 55 And the output current of the voltage-current conversion circuit 55 increases.

As described above, in the semiconductor integrated circuit according to the third embodiment, the adjustment of the current value output in accordance with the result of the comparison operation can be adjusted at the manufacturing process stage, and the bias input to the bias input terminal IN3 can be adjusted. By adjusting the voltage, a comparison circuit that adjusts the voltage output from the predetermined voltage detection circuit 55 to the voltage-current conversion circuit 56 and adjusts the amount of current output from the voltage-current conversion circuit 56 is formed. Therefore, Embodiment 2
The same effect as described above can be obtained, and the output current value indicating the comparison result can be easily adjusted even after the manufacturing.

Embodiment 4 In the first to third embodiments, the case where the predetermined voltage Va varies because the ratio of the gain coefficient of the P-MOSs 31 to 34 forming the voltage difference detection circuit 21 varies due to process variation or the like. was there. Thus, a fourth embodiment of the present invention is described in which the variation of the predetermined voltage Va output from the voltage difference detection circuit 21 is adjusted to be constant.

FIG. 13 is a circuit diagram showing an example of a comparison circuit of a semiconductor integrated circuit according to the fourth embodiment of the present invention.
A schematic block diagram showing an example of a semiconductor integrated circuit according to the fourth embodiment of the present invention includes a semiconductor integrated circuit element 1 of FIG.
Is the same as that of FIG. In the fourth embodiment, the comparison circuit 52 shown in FIG. 12 of the third embodiment will be described as an example, and the same applies to the comparison circuits shown in the first and second embodiments. Therefore, the description is omitted. From this,
13, the same components as those in FIG. 12 are denoted by the same reference numerals, and the description thereof will be omitted, and only the differences from FIG. 12 will be described.

FIG. 13 differs from FIG. 12 in that FIG.
A Va adjustment circuit 85 comprising an N-MOS 86 is provided at the connection between the voltage difference detection circuit 21 and the predetermined voltage detection circuit 55, and an input terminal IN4 to which the gate voltage of the N-MOS 86 is applied from the outside is provided. Accordingly, the comparison circuit 52 shown in FIG. In FIG. 13, the drain of the N-MOS 86 is connected to the connection portion A in the voltage difference detection circuit 21, and the N-MO
The source of S86 is grounded. The gate of the N-MOS 86 is connected to a correction input terminal IN4 to which a correction voltage is externally applied.

In such a configuration, the N-MOS 86
Bypasses the current corresponding to the voltage input to the correction input terminal IN4 from the connection point A to the ground. Thereby, the voltage of the connection part A can be adjusted.

As described above, in the semiconductor integrated circuit according to the fourth embodiment, the voltage of the connection portion A is adjusted by the N-MOS 86 by inputting the correction voltage to the correction input terminal IN4. Accordingly, the manufacture of the MOS transistor constituting the voltage difference detection circuit 21 at the predetermined voltage Va output from the connection portion A when the voltages input to the two input terminals IN1 and IN2 of the voltage difference detection circuit 21 are equal. Since the variation due to the above variation or the like can be corrected and made constant, the comparison operation of the two image data obtained from the photoelectric conversion circuit 2 can be performed more accurately with a simple circuit configuration.

Embodiment 5 FIG. In the first to fourth embodiments, only the comparison result is output from the comparison circuit. However, the comparison result performed by the comparison circuit is stored in the first memory 3 and the second memory 4. The selected data may be switched and output, and such data is referred to as a fifth embodiment of the present invention. FIG.
FIG. 17 is a schematic block diagram showing an example of a semiconductor integrated circuit according to a fifth embodiment of the present invention. In FIG. 14,
A semiconductor integrated circuit device forming an image sensor for detecting a change in an image is shown as an example. In FIG. 14, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted and only the differences from FIG. 1 will be described.

The difference between FIG. 14 and FIG. 1 is that the comparison circuit 5 of FIG. 1 is stored in the first memory 3 and the second memory 4 instead of the comparison result according to a control signal input from the outside. Since each data is output, the comparison circuit 5 in FIG. 1 is used as the comparison circuit 92, and the semiconductor integrated circuit device 1 in FIG. is there.

In FIG. 14, a semiconductor integrated circuit device 91
Is a photoelectric conversion circuit 2, a first memory 3, and a second memory 4.
And compares the data stored in the first memory 3 with the data stored in the second memory, and compares the comparison result with each data stored in the first memory 3 and the second memory 4.
It is composed of a comparison circuit 92 which switches according to a control signal input from the outside and outputs it to the outside. The first memory 3 and the second memory 4 are connected to the comparison circuit 92, respectively.

FIG. 15 is a diagram showing a circuit example of the comparison circuit 92 shown in FIG. In FIG. 15, the same components as those in FIG. 13 are denoted by the same reference numerals, and the description thereof will be omitted, and only the differences from FIG. 13 will be described. FIG.
13 is different from FIG. 13 in that P-MOSs 94 to 9 for switching the output to the voltage difference detection circuit 21 in FIG.
6 and the N-MOS 97, and the input terminal IN
13 are provided by providing output terminals OUT1 and OUT2 for converting currents respectively input from IN1 and IN2 into currents and outputting the converted voltages, and by further changing the circuit configuration of the Va adjustment circuit 85 in FIG. 13. 13 voltage difference detection circuit 2
1 is a voltage difference detection circuit 98, and the Va adjustment circuit 8 in FIG.
5 is the Va adjustment circuit 101.

In FIG. 15, the comparison circuit 92 compares the input voltages input to the input terminals IN1 and IN2, that is, the data stored in the first memory 3 and the data stored in the second memory 4. And a voltage indicating the result of the comparison and each of the stored data input from the first memory 3 and the second memory 4 are switched and output according to a control signal input from the outside. Circuit 98
And a Va adjustment circuit 101 that adjusts the voltage of the output voltage indicating the comparison result output from the voltage difference detection circuit 98, a predetermined voltage detection circuit 55, and a voltage-current conversion circuit 56.

The voltage difference detection circuit 98 includes P-MOSs 31 to
34, 94, 95 and a transmission gate 96. In the P-MOS 94, the gate is connected to the bias input terminal IN3, the drain is connected to the connection between the drain of the P-MOS 31 and the source of the P-MOS 33, and the source is connected to the connection between the gates of the P-MOSs 31 and 32. . The drain of the P-MOS 33 is an output terminal O
The drain of the P-MOS 34 is connected to the output terminal OUT2. In the P-MOS 95, the gate is connected to the bias input terminal IN3, the source is connected to the connection section A, and the drain is the NM of the predetermined voltage detection circuit 55.
It is connected to the gate of OS65.

In the transmission gate 96,
The P-MOS gate 96a is connected to an input terminal IN5 to which a binary switching signal is input from the outside, and the N-MOS gate 96b is connected to a bias input terminal IN3. One input / output terminal 96c of the transmission gate 96 is connected to an input terminal IN6 to which a binary switching signal is input from the outside, and the other input / output terminal 96d.
Is connected to the connection between the gates of the P-MOSs 31 and 32.

The Va adjustment circuit 101 includes a P-MOS 102
In the P-MOS 102, the gate is connected to the connection between the gates of the P-MOSs 31 and 32, the source is connected to the power supply terminal Vdd, and the drain is connected between the drain of the P-MOS 95 and the gate of the N-MOS 65. Connected to the unit. That is, the P-MOS 102 is
When 5 is turned on and becomes conductive, it is connected in parallel with the P-MOS 32.

In such a configuration, first, the operation when the comparison result for each input voltage input to the input terminals IN1 and IN2 is output from the voltage-current conversion circuit 56 will be described. When a comparison result for each input voltage input to the input terminals IN1 and IN2 is output, a low-level signal is externally input to the bias input terminal IN3, and a high-level signal is input to the input terminals IN5 and IN6. Is entered. At the same time, output terminal O
UT1 and OUT2 are grounded externally.

The Lo input to the bias input terminal IN3
The transmission gate 9
The N-MOS 6 is turned off to be in a cutoff state, so that the input / output terminal of the transmission gate 96 is in a cutoff state. On the other hand, Lo input to the bias input terminal IN3
The P-MOS 61, 63, 7
2, 94 and 95 are turned on. In this way, a current indicating the comparison result is output from the output of the voltage-current conversion circuit 56, that is, the output terminal OUT of the comparison circuit 92.

Next, an operation in the case of outputting respective currents according to the respective input voltage values input to the input terminals IN1 and IN2 instead of outputting the current indicating the comparison result will be described. When the respective currents corresponding to the respective input voltage values input to the input terminals IN1 and IN2 are output to the outside, the High level is externally applied to the bias input terminal IN3.
A level signal is input, a low level signal is input to the input terminal IN5, and a predetermined adjustment voltage for adjusting the current value output from the output terminals OUT1 and OUT2 is input to the input terminal IN6. . At the same time, the output terminals OUT1 and OUT2 are disconnected from the external ground.

Since the bias input terminal IN3 is at a high level and the input terminal IN5 is at a low level, the transmission gate 96 is turned on and the input / output terminals 9 are turned on.
6c and 96d become conductive, and the P-MOS 61,
The switches 63, 72, 94, and 95 are turned off and are turned off. From this, the input voltages input to the input terminals IN1 and IN2 are converted into currents according to the voltage values by the P-MOSs 31 to 34, and the output terminals OUT1 and O2 are output.
Each is output from UT2. The output terminal OUT
1 and the current value output from OUT2 are input terminal IN
The adjustment can be made by changing the voltage value input to 6.

Here, a current corresponding to the input voltage inputted to the input terminals IN1 and IN2 is supplied to the output terminals OUT1 and O2.
Since it is necessary to output from the UT 2, it is better to make each gain coefficient of the P-MOSs 31 and 32 and each gain coefficient of the P-MOSs 33 and 34 equal. However, in this case, the predetermined voltage Va cannot be output to the predetermined voltage detection circuit 55 when the voltages input to the input terminals IN1 and IN2 are equal. This is P-MO
The gain coefficients β31 to β34 of S31 to S34 are as described in (1) above.
This is due to the fact that the expression is not as shown.

Therefore, the drain of the P-MOS 95 and the N-
The voltage at the connection B with the base of the MOS 65 is
The P-MOS of the Va adjustment circuit 101 is set so that the voltage becomes equal to the predetermined voltage Va when the voltages input to N1 and IN2 are equal.
The adjustment is performed using 102. For example, P-MOSs 31 to
34, all the gain factors are the same, the P-MOS
By forming the P-MOS 102 such that the gain coefficient β102 of the P-MOS 102 becomes three times the gain coefficient β32 of the P-MOS 32, the voltage of the connection portion B is reduced to the P-MOSs 31 to 3.
4 are the same as the voltages at the connection A in the above equation (1).

As described above, when the gain coefficients of the P-MOSs 31 to 34 are β31: β32: β33: β34 = 1: 1: k: k, the voltage of the connection B is input to the input terminals IN1 and IN2. The P-MOS 102 is formed in the gain coefficient β102 so that the applied voltage is equal to the predetermined voltage Va.

FIG. 15 illustrates a case where the voltage indicating the comparison result output from the voltage difference detection circuit 98 to the predetermined voltage detection circuit 55 is adjusted by using the Va adjustment circuit 101. The adjustment can also be performed using the Va adjustment circuit 85. In this case, FIG.
5 is as shown in FIG. Note that FIG.
Here, the same components as those in FIG. 15 are denoted by the same reference numerals, and the description thereof is omitted here, and only different points from FIG. 15 will be described. 16 differs from FIG. 15 in that the Va adjustment circuit 101 in FIG. 15 is replaced with a Va adjustment circuit 85 and a correction input terminal IN4 is provided.

In FIG. 16, the comparison circuit 92 includes a voltage difference detection circuit 98, a Va adjustment circuit 85, a predetermined voltage detection circuit 55, and a voltage-current conversion circuit 56. In the N-MOS 86 of the Va adjustment circuit 85, the gate is connected to the correction input terminal IN4, the drain is connected to the connection portion B, and the source is grounded. With this configuration, the voltage of the connection portion B can be adjusted by changing the voltage input to the correction input terminal IN4.

As described above, in the semiconductor integrated circuit according to the fifth embodiment, the comparison result for each of the input voltages input to the input terminals IN1 and IN2 is compared with the voltage-current conversion circuit 56.
Or whether to output from the output terminals OUT1 and OUT2 respective currents according to the respective input voltage values input to the input terminals IN1 and IN2, instead of outputting the current indicating the comparison result. Switching is performed according to a control signal input from the outside. From this, it is possible to switch and output the comparison result performed by the comparison circuit and each data stored in the first memory 3 and the second memory 4 and to output the voltage difference detection circuit 98
Can be corrected to be constant, the comparison operation of two image data obtained from the photoelectric conversion circuit 2 can be performed more accurately with a simple circuit configuration.

[0077]

According to the semiconductor integrated circuit of the present invention, the output voltage is minimized only when the two input voltages are equal.
A comparison circuit for comparing two input voltages is formed. Accordingly, it is possible to obtain a comparison circuit that can accurately perform a comparison operation of two image data obtained from a photoelectric conversion element or the like with a simple circuit configuration, and introduce the comparison circuit into the pixels of the image sensor. The cost can be reduced.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit having a comparison circuit for comparing two input voltages at which the output voltage becomes maximum only when the two input voltages are equal. Accordingly, it is possible to obtain a comparison circuit that can accurately perform a comparison operation of two image data obtained from a photoelectric conversion element or the like with a simple circuit configuration, and introduce the comparison circuit into the pixels of the image sensor. The cost can be reduced.

According to a third aspect of the present invention, in the semiconductor integrated circuit according to any one of the first and second aspects, the comparison circuit converts an output voltage corresponding to a voltage difference between two input voltages into a current corresponding to the voltage value. Converted and output. From this,
When connecting to an external circuit, if it is more efficient to output the comparison operation result as a current value depending on the configuration of the external circuit,
For example, addition of comparison operation results can be facilitated.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the comparing circuit outputs a predetermined voltage Va when the two input voltages are equal to each other; When the voltage output from the difference detection circuit is a predetermined voltage Va, a predetermined voltage detection circuit that minimizes the output voltage is provided. Accordingly, it is possible to obtain a comparison circuit that can accurately perform a comparison operation of two image data obtained from a photoelectric conversion element or the like with a simple circuit configuration, and introduce the comparison circuit into the pixels of the image sensor. The cost can be reduced.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to the second aspect, the comparison circuit is configured to output a predetermined voltage Va when two input voltages are equal to each other; When the voltage output from the difference detection circuit is a predetermined voltage Va, a predetermined voltage detection circuit that maximizes the output voltage is provided. Accordingly, it is possible to obtain a comparison circuit that can accurately perform a comparison operation of two image data obtained from a photoelectric conversion element or the like with a simple circuit configuration, and introduce the comparison circuit into the pixels of the image sensor. The cost can be reduced.

According to a sixth aspect of the present invention, in the semiconductor integrated circuit according to any one of the fourth and fifth aspects, the comparison circuit may further include a step of changing a voltage output from the predetermined voltage detection circuit into a current corresponding to the output voltage value. And a voltage-current conversion circuit that outputs the converted voltage. For this reason, when it is more efficient to output the comparison result as a current value depending on the configuration of the external circuit when connecting to an external circuit, for example, the addition of the comparison result can be facilitated.

According to a seventh aspect of the present invention, in the semiconductor integrated circuit according to the sixth aspect, the voltage-current conversion circuit controls the output of the converted current according to a predetermined signal from the outside. Therefore, it is possible to control the output of the comparison result of each data input to the voltage difference detection circuit, and to adjust the output current value indicating the comparison result.

In the semiconductor integrated circuit according to the eighth aspect, in any one of the fourth to seventh aspects, the predetermined voltage detection circuit further adjusts the output voltage with respect to the voltage input from the voltage difference detection circuit. It has a circuit. Thus, the output voltage value indicating the comparison result output from the predetermined voltage detection circuit can be easily adjusted.

According to a ninth aspect of the present invention, in the semiconductor integrated circuit according to any one of the fourth to eighth aspects, the comparison circuit further adjusts a variation of the predetermined voltage Va output from the voltage difference detection circuit to adjust the predetermined voltage. It has a Va adjustment circuit for outputting to the detection circuit. From this, it is possible to correct the variation due to manufacturing variation and the like in the predetermined voltage Va output when the voltages input to the two input terminals of the voltage difference detection circuit are equal, and to make it constant. The comparison operation of the two image data obtained from the conversion element can be performed more accurately with a simple circuit configuration.

According to a tenth aspect of the present invention, in the semiconductor integrated circuit according to any one of the fourth to ninth aspects, the voltage difference detection circuit further comprises a voltage difference detection circuit for detecting a voltage difference between the two input voltages in response to a predetermined external signal. And a switching circuit for switching between output to a predetermined voltage detection circuit of a voltage corresponding to the current and output of a current obtained by converting two input voltages into current values corresponding to the respective voltage values to the outside. From this, it is possible to switch and output the result of comparison performed by the comparison circuit and each data input to the two inputs of the voltage difference detection circuit. For this reason, two data can be compared and the two data can be obtained, and a device for detecting a change in image data obtained from a photoelectric conversion element or the like, for example, a monitoring device for monitoring an intruder or the like This is effective when used for

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating an example of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a circuit example of the photoelectric conversion circuit 2 of FIG. 1;

FIG. 3 is a diagram showing a circuit example of a first memory 3 and a second memory 4 in FIG. 1;

FIG. 4 is a schematic block diagram illustrating a configuration example of a comparison circuit 5 of FIG. 1;

5 is a diagram showing a circuit example of a comparison circuit 5 in FIG.

FIG. 6 is a diagram showing another example of the circuit in the comparison circuit 5 of FIG. 4;

FIG. 7 is a diagram showing another example of the circuit in the comparison circuit 5 of FIG. 4;

8 is a diagram illustrating another example of the circuit in the comparison circuit 5 of FIG. 4;

FIG. 9 is a diagram showing another example of the circuit in the comparison circuit 5 of FIG. 4;

FIG. 10 is a schematic block diagram showing a configuration example of a comparison circuit of a semiconductor integrated circuit according to a second embodiment of the present invention.

11 is a diagram showing a circuit example of a comparison circuit 42 in FIG.

FIG. 12 is a circuit diagram showing an example of a comparison circuit of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 13 is a circuit diagram showing an example of a comparison circuit of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 14 is a schematic block diagram illustrating an example of a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 15 is a diagram illustrating a circuit example of the comparison circuit 92 in FIG. 14;

16 is a diagram showing another example of the comparison circuit 92 in FIG. 14;

[Explanation of symbols]

1,91 semiconductor integrated circuit elements, 2 photoelectric conversion circuits,
3 First memory, 4 Second memory, 5, 42, 5
2,82,92 Comparison circuit, 21,98 Voltage difference detection circuit, 22,55 Predetermined voltage detection circuit, 43,56
Voltage-current conversion circuit, 85, 101 Va adjustment circuit.

Continued on front page F-term (reference) 5J056 AA00 AA11 BB21 BB57 CC00 CC09 DD13 DD28 EE11 FF07 FF09 5J066 AA01 AA12 AA56 CA14 CA87 CA88 CA91 CA92 CA98 FA09 HA10 HA17 HA25 HA45 KA02 KA09 KA17 KA28 KA12 SA01

Claims (10)

[Claims] 1. A semiconductor integrated circuit having a comparison circuit for comparing two input voltages and outputting a result of the comparison, wherein the comparison circuit has a minimum output voltage when the two input voltages are equal. A semiconductor integrated circuit, wherein an output voltage becomes larger than a minimum value as a voltage difference between two input voltages increases. 2. A semiconductor integrated circuit comprising a comparison circuit for comparing two input voltages and outputting the comparison result, wherein the comparison circuit has a maximum output voltage when the two input voltages are equal. A semiconductor integrated circuit, wherein an output voltage becomes smaller than a maximum value as a voltage difference between two input voltages increases. 3. The comparison circuit according to claim 1, wherein the comparison circuit converts an output voltage corresponding to a voltage difference between two input voltages into a current corresponding to the voltage value and outputs the converted current. A semiconductor integrated circuit according to any one of the above. 4. A voltage difference detecting circuit for outputting a voltage corresponding to a voltage difference between two input voltages and outputting a predetermined voltage Va when the two input voltages are equal to each other. The voltage output from the detection circuit is a predetermined voltage Va
A predetermined voltage detection circuit in which, as the output voltage becomes minimum and the voltage output from the voltage difference detection circuit becomes smaller or larger than the predetermined voltage Va, the output voltage becomes larger than the minimum value. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is provided. 5. A voltage difference detection circuit for outputting a voltage corresponding to a voltage difference between two input voltages and outputting a predetermined voltage Va when the two input voltages are equal to each other. The voltage output from the detection circuit is a predetermined voltage Va
A predetermined voltage detection circuit in which the output voltage becomes maximum, and as the voltage output from the voltage difference detection circuit becomes smaller or larger than the predetermined voltage Va, the output voltage becomes smaller than the maximum value. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is provided. 6. The comparison circuit according to claim 4, wherein the comparison circuit includes a voltage-current conversion circuit that converts a voltage output from the predetermined voltage detection circuit into a current corresponding to the output voltage value and outputs the converted current. A semiconductor integrated circuit according to claim 5. 7. The semiconductor integrated circuit according to claim 6, wherein the voltage-current conversion circuit controls output of the converted current in response to a predetermined external signal. 8. The apparatus according to claim 4, wherein the predetermined voltage detection circuit has an adjustment circuit for adjusting an output voltage with respect to a voltage input from the voltage difference detection circuit.
A semiconductor integrated circuit according to any one of the above. 9. The comparison circuit according to claim 4, wherein the comparison circuit includes a Va adjustment circuit that adjusts a variation of the predetermined voltage Va output from the voltage difference detection circuit and outputs the result to the predetermined voltage detection circuit. 9. The semiconductor integrated circuit according to any one of 8. 10. The voltage difference detection circuit outputs an output to a predetermined voltage detection circuit of a voltage corresponding to a voltage difference between two input voltages and two input voltages according to a predetermined signal input from the outside. 10. The semiconductor integrated circuit according to claim 4, further comprising a switching circuit for switching between a current obtained by converting the current value into a current value corresponding to each voltage value and an external output. .