JP2000295193A - Synchronization detection device - Google Patents

Abstract

(57) [PROBLEMS] To enable stable frame synchronization even in a fading environment and eliminate erroneous detection of a transmission mode with respect to frame synchronization of an OFDM signal. SOLUTION: A detecting means 10 performs envelope detection of a received OFDM signal. The encoding means 20 binarizes the signal after detection to generate a null signal, and encodes the null signal at predetermined time intervals. The comparing unit 30 compares the encoded data sequence with a predetermined synchronization pattern, and determines that the synchronization has been detected when the data patterns match.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization detection device for detecting a synchronization signal when a transmission signal has a frame structure including a modulated signal and a non-signal section of a fixed length.

[0002]

2. Description of the Related Art In recent years, digitalization of broadcasting technology has been rapidly advanced. For example, terrestrial digital audio broadcasting employing a transmission system called OFDM (orthogonal frequency division multiplexing) has been put to practical use. In such a broadcasting system, the following specifications are common. (1) A plurality of OFDM symbols constitute a transmission unit called a frame. (2) The encoded audio data is transmitted in frame units. (3) A special signal for establishing synchronization on the receiver side is inserted into the frame.

For example, in a digital audio broadcasting (hereinafter referred to as DAB) system in Europe, a non-signal section called a null symbol is inserted at the head of a frame. On the receiver side, this frame is established in order to establish frame synchronization. Use the null symbol.

A technique for detecting synchronization using a no-signal section (null symbol) inserted into a frame and establishing frame synchronization is described in, for example, Japanese Patent Application Laid-Open No. H8-102769, “OFD.
M synchronous demodulation circuit "and JP-A-9-214464," Synchronization detection device for orthogonal frequency division multiplex receiver ". Hereinafter, the operation of the above-described conventional synchronization detection device will be described.

First, a first conventional example, that is, Japanese Patent Application Laid-Open No. H8-102769
An example of the above publication will be described. The OFDM synchronous demodulation circuit of this publication is provided with a symbol synchronization detection circuit. When an OFDM modulated wave including a null symbol is input to this circuit, an envelope detection circuit detects the envelope of the OFDM modulated wave. In addition, the moving average circuit
A moving average is obtained by integrating the envelope waveform within the window moving on the time axis with respect to the DM signal phase. Since this moving average becomes a V-shaped waveform, the peak value of this waveform is input to a reference level comparison null detection circuit and compared with a predetermined reference level. The head of the frame is determined based on the result.

Next, a second conventional example, that is, Japanese Patent Application Laid-Open No. 9-214464 is disclosed.
An example of the above publication will be described. The synchronous detection device of this publication inputs an OFDM signal including a null signal, performs envelope detection by an envelope detector as in the first conventional example, and obtains a signal whose level has decreased during a null signal period.
This signal is input to a comparator, and is shaped into a rectangular wave having an L level during a null signal period. Basically, the rising edge of this rectangular wave is regarded as the beginning of the frame. In order to prevent erroneous synchronization, a signal called a gate signal is used. This means that when the edge of a square wave is detected,
A gate signal is generated at a frame interval, and thereafter, it is determined that a synchronization state is established only when an edge of a rectangular wave is detected within a period in which the gate signal is at the H level.

[0007]

In the case of broadcasting such as DAB, it is necessary to consider the case of receiving while moving by car or the like. However, in mobile reception on a transmission path having a multipath, a phenomenon called fading in which received power fluctuates with time occurs. For this reason, the transmission path characteristics become severe for the receiver. As a result, frame synchronization may not be achieved with the above-described conventional configuration.

[0008] FIG. 15 is a diagram showing an example of O 2 under a fading environment.
FIG. 15 schematically shows a received signal of FDM.
As shown in (a), a weak signal section longer than a null symbol appears due to fading. When an envelope is detected from this received signal, the result is as shown in FIG. When the moving average value is obtained by integrating the envelope with the window signal, the result is as shown in FIG. FIG.
In the case of, the moving average value of the envelope in the weak signal section is a value as small as the null symbol section. Therefore, the first conventional example has a problem that a weak signal section is erroneously detected as the head of a frame.

In the second conventional example, the above problem is slightly improved by using the above-mentioned gate signal, but there is another problem. In the DAB system, four different transmission modes are defined, and the frame length and the null symbol section length are set as shown in Table 1, respectively.

[Table 1] In particular, the frame length of mode 1 and mode 4 is
In the second conventional example, as shown in FIG.
However, there is a problem that the signal is synchronously detected as a signal.

SUMMARY OF THE INVENTION The present invention has been made in view of such conventional problems, and provides a synchronization detecting apparatus capable of performing stable frame synchronization even in a fading environment and free from erroneous detection of a transmission mode. The purpose is to provide.

[0011]

According to a first aspect of the present invention, there is provided a method for receiving a transmission signal in which a non-signal section having a predetermined length is inserted at a predetermined period with respect to a modulation signal, and wherein the non-signal section of the transmission signal is received. A synchronization detecting device for detecting a frame synchronization signal by detecting the envelope signal of the transmission signal, and detecting the envelope signal obtained by the detection means by 2
Coding means for converting the value into a value and coding at a predetermined clock cycle, and comparing means for comparing the coded data sequence obtained by the coding means with a predetermined synchronization pattern to determine whether or not the two match; And characterized in that:

[0012] The invention according to claim 2 of the present application is to receive a transmission signal in which a non-signal section of a fixed length is inserted into the modulation signal at regular intervals, and identify the non-signal section of the transmission signal. What is claimed is: 1. A synchronization detection device for detecting a frame synchronization signal, comprising: a detection unit for performing envelope detection on the transmission signal; and an encoding unit for binarizing the envelope signal obtained by the detection unit and encoding the binary signal at a predetermined clock cycle. Means, comparing the encoded data sequence obtained by the encoding means with a predetermined synchronization pattern, and determining whether or not the two coincide with each other; and inputting a comparison result indicating coincidence from the comparison means. Then, by counting the period of occurrence of the comparison result, a time measuring means for calculating the frame period and an encoded data string obtained by the encoding means are converted to a frame obtained by the time measuring means. A cycle of beam period, a predetermined number of times continuously checks whether coincides with the predetermined synchronization pattern, a synchronization determination means for determining a synchronization state in the case of coincidence,
It is characterized by having.

According to a third aspect of the present invention, in the synchronization detecting apparatus according to the second aspect, the synchronization determining means determines that the encoded data sequence obtained by the encoding means is a frame obtained by the time measuring means. When the predetermined synchronization pattern does not coincide with the predetermined synchronization pattern a predetermined number of times with a period as a cycle, the determination of the synchronization state is canceled.

[0014] According to a fourth aspect of the present invention, a transmission signal in which a non-signal section having a constant length is inserted into a modulation signal at regular intervals is received, and the non-signal section of the transmission signal is identified. What is claimed is: 1. A synchronization detection device for detecting a frame synchronization signal, comprising: a detection unit for performing envelope detection on the transmission signal; and an encoding unit for binarizing the envelope signal obtained by the detection unit and encoding the binary signal at a predetermined clock cycle. Means, and a plurality of comparing means for comparing the coded data sequence obtained by the coding means with a predetermined synchronization pattern corresponding to each transmission mode, and determining whether or not both match. It is characterized by the following.

According to a fifth aspect of the present invention, a non-signal section of a transmission signal in which a non-signal section having a fixed length is inserted at a predetermined cycle with respect to a modulation signal is received, and the non-signal section of the transmission signal is identified. What is claimed is: 1. A synchronization detection device for detecting a frame synchronization signal, comprising: a detection unit for performing envelope detection on the transmission signal; and an encoding unit for binarizing the envelope signal obtained by the detection unit and encoding the binary signal at a predetermined clock cycle. Means and a predetermined synchronization pattern corresponding to k kinds of transmission modes by comparing the coded data sequence obtained by the coding means with the first to k-th comparisons for determining whether or not both match. Means, said i-th
(I = 1 to k) by inputting a comparison result indicating a match from the comparison means and counting the generation cycle of the comparison result,
The ith (i = 1 to 1) for calculating the frame period of each transmission mode
k), the coded data sequence obtained by the encoding means is synchronized with the respective transmission modes by a predetermined number of times continuously with the frame period obtained by the i-th time measuring means as a cycle. And i-th (i = 1 to k) synchronization determining means for determining a synchronization state when the pattern matches.

According to a sixth aspect of the present invention, in the synchronization detecting device of the fifth aspect, the i-th synchronization judging means is configured to output the encoded data sequence obtained by the encoding means to the i-th data.
When the synchronization does not match the synchronization pattern of each transmission mode a predetermined number of times with the frame period obtained by the time measurement means as a cycle, the determination of the synchronization state is released.

According to a seventh aspect of the present invention, in the synchronization detecting apparatus of the fourth, fifth or sixth aspect, after determining the synchronization state in the specific transmission mode, the synchronization detecting operation in another transmission mode is stopped. It is characterized in that judgment operation stopping means is provided.

According to an eighth aspect of the present invention, in the synchronization detecting apparatus according to any one of the first to seventh aspects, the comparing means can arbitrarily set a synchronization pattern used for comparison with the encoded data sequence. It is characterized by being.

According to a ninth aspect of the present invention, in the synchronization detecting apparatus according to any one of the first to eighth aspects, the comparing means includes a predetermined one of the synchronization patterns used for comparison with the encoded data sequence. Are excluded from the comparison.

According to a tenth aspect of the present invention, in the synchronization detecting apparatus of the ninth aspect, the comparing means can arbitrarily set a bit to be excluded from a comparison target.

According to an eleventh aspect of the present invention, in the synchronization detecting device of the eighth aspect, the comparing means includes a shift register for temporarily holding the encoded data sequence, a register for holding the synchronization pattern, A combination circuit for determining whether or not the data held in the shift register matches the data held in the register.

According to a twelfth aspect of the present invention, in the synchronization detecting device of the tenth aspect, the comparing means includes a shift register for temporarily holding the encoded data sequence and a first register for holding the synchronization pattern. A register, a second register for specifying a position of a bit to be excluded from the comparison target, and a data value held in the shift register and data held in the first register, And a combinational circuit that determines whether or not they match except for the set bit position.

The invention of claim 13 of the present application is directed to claims 1 to 1
3. The synchronization detection device according to claim 2, wherein the modulated signal includes a plurality of OFs having a guard interval of a predetermined length.
It is a DM (orthogonal frequency division multiplex) symbol.

According to a fourteenth aspect of the present invention, in the synchronization detecting device of the thirteenth aspect, the clock cycle of the encoding means is equal to or less than 1/2 of the guard interval length. .

According to a fifteenth aspect of the present invention, in the synchronization detecting device of the fourteenth aspect, the synchronization pattern used by the comparing means is such that the no-signal section length is n and the clock cycle of the encoding means is d. When {(n / d) +2}
It is characterized by being a pattern of bits or more.

[0026]

(First Embodiment) First, a synchronization detecting device according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of the synchronization detecting device 1a according to the present embodiment. This synchronization detecting device 1a is provided with an analog or digital converted O
It receives an FDM signal and outputs a synchronization detection result. The detection means 10, the encoding means 20, and the comparing means 30
It is comprised including. The same clock is supplied to the encoding means 20 and the comparison means 30.

The detection means 10 receives the signal O
This is to detect the envelope of the FDM signal. When the OFDM signal is input in analog, the detection means 10 is configured by an analog circuit, and outputs the detection signal as an analog signal. When the OFDM signal is inputted digitally, the detecting means 10 is constituted by a digital circuit, and outputs the detected signal as a digital value.

The encoding means 20 includes a comparator (Com
p) 201 and a latch 202. If the output of the detection means 10 is an analog signal, the comparator 20
Numeral 1 compares the detection signal input from the input terminal B with a predetermined voltage value and outputs a binarized comparison result. If the output of the detection means 10 is a digital value, the comparator 20
1 outputs a binarized comparison result by comparing the digital detection signal with a predetermined value. The latch 202 receives the comparison result of the comparator 201 from the input terminal C, and converts the result of the comparison into an encoded data sequence at a clock cycle from the input terminal D.

The comparing means 30 compares the coded data string inputted from the input terminal E with a predetermined pattern, and comprises a shift register 301 and a combination circuit 302. The shift register 301 captures an encoded data sequence for each clock, and stores, for example, 8-bit data. The combinational circuit 302
When the bit pattern of the shift register 301 is a predetermined pattern, for example, “10000001”, the circuit goes to the H level.

FIG. 2 is a timing chart showing waveforms of the respective circuits shown in FIG. As shown in FIG.
When an original OFDM signal into which a no-signal section (null symbol) is inserted is input at times t1 to t2, a waveform as shown in FIG. 2B is obtained after envelope detection. When this signal is binarized, a comparison result as shown in FIG. 2C is obtained. When the comparison result is sampled with the clock of FIG. 2D, the no-signal section (null symbol) is coded to a value 0 as shown in FIG. 2E, and is coded to a value 1 in other periods. Is done. By comparing this coded data string with the synchronization pattern shown in FIG. 2 (f), a synchronization detection result is obtained at time t3 as shown in FIG. 2 (g).

FIG. 3 shows an OFDM signal in a fading environment.
FIG. 3 shows signal waveforms in a case where a weak signal section longer than a null symbol appears in a signal, in the same order as in FIG. 2.
As shown in FIG. 3A, if a signal including a weak signal section in which a normal null symbol is inserted and the amplitude of the OFDM signal sharply decreases in a certain time zone is input, after envelope detection, The waveform is as shown in FIG. When this signal is binarized, a comparison result as shown in FIG.
It becomes L level in the period from 1 to t2, and becomes L level in the period from time t3 to t4 in the weak signal section. When this comparison result is sampled by the clock of FIG.
As shown in FIG. 7, in the no-signal section, 6 bits are continuously 0, and data before and after the 6 bits is followed by a bit of value 1. In the period from time t3 to t4, 8 bits are continuously 0.
, And before and after that, bits of value 1 follow. So Figure 3
By comparing with the synchronization pattern “10000001” shown in (f), a synchronization detection result can be obtained only immediately after time t2 as shown in FIG.

Here, since the weak signal section is different from the null symbol section length, the encoded data sequence does not match the synchronization pattern, and the weak signal section does not mistake the beginning of the frame.
If the weak signal section matches the null symbol section length, erroneous detection will occur, but this is a rare phenomenon stochastically,
It can be said that there is no problem in practical use.

In the DAB standard as shown in Table 1, since the null symbol section length differs for each transmission mode, the synchronization pattern corresponding to a certain transmission mode does not match the encoded data sequence of another transmission mode. . Therefore, the synchronization detection device 1a according to the present embodiment does not synchronize in an erroneous transmission mode unlike the second conventional example.

Incidentally, in the normal OFDM signal, a guard interval is added to each symbol in order to remove inter-symbol interference in a multipath environment. In order to prevent this inter-symbol interference from occurring, 1/1 of the guard interval length is used.
It is desirable to perform frame synchronization with a time accuracy of 2 or less.
Therefore, it is effective to set the encoding interval of the encoding means 20 to 以下 or less of the guard interval length. Furthermore, in order to completely capture the null symbol by the synchronization pattern, it is preferable to use a synchronization pattern of {(n / d) +2} bits or more, where n is the null symbol length and d is the coding interval.

In the present embodiment, the frame modulation / transmission system is OFDM, but other modulation systems may be used. Further, the circuit configurations of the encoding unit and the comparing unit are not limited as in the present embodiment. For example, using a general-purpose processor, functions equivalent to those of the encoding unit 20 and the comparing unit 30 are obtained. It is also possible to realize.

(Embodiment 2) Next, a synchronization detecting apparatus according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram illustrating a configuration of the synchronization detection device 1b according to the present embodiment. Here, detection means 1
Since the functions of 0, the encoding means 20, and the comparing means 30 are the same as those of the first embodiment, their description will be omitted.
FIG. 5 is a timing chart showing the operation of each unit of the synchronization detection device according to the present embodiment.

The time measuring means 40 in FIG. 4 is a down counter with set / reset for calculating a frame period. After the reset, as shown at time t1 in FIG.
The value is set to a predetermined value by the first output pulse of the comparing means 30, and thereafter, the count value decreases as shown in FIG. The synchronization determination circuit 50b is a circuit including the coincidence counter 501, and performs a synchronization determination during a period in which the measured value of the time measuring unit 40 is within a predetermined range as shown in FIGS. 5 (c) and 5 (d). It is. The value of the coincidence counter 501 changes from 0 to 1 by the first output pulse of the comparing means 30 as shown in FIG. Subsequent measured values change with the frame period as a cycle.

When a pulse is output from the comparing means 30 during the synchronization determination period, the value of the coincidence counter 501 is changed to the value shown in FIG.
As shown in (e), it is advanced one by one, and stops when it reaches a predetermined value (3 in FIG. 5). Time t in FIG. 5B
If there is no pulse output from the comparing means 30 within the synchronization determination period shown in FIG.
0b considers that an out-of-synchronization has occurred, resets the time measuring means 40 as shown in FIG. 5C, and resets the coincidence counter 501 as shown in FIG. 5E. The synchronization determination circuit 50b outputs the output of the comparing means 30 when the coincidence counter 501 has reached a predetermined value (= 3), as shown at times t2 and t3 in FIG. As shown in FIG.

With the above-described configuration, the synchronization detecting device 1b of the present embodiment sets the synchronization state when the coded data sequence matches the synchronization pattern continuously a predetermined number of times (= 3 times) with the frame period as a cycle. The decision is made. By introducing such a backward protection process, highly reliable synchronization detection can be performed as compared with the first embodiment.

As in Embodiment 1, the null symbol length is n, the coding interval is d, the coding interval is 以下 or less of the guard interval length, and the synchronization pattern length is ｛(n
/ D) +2｝ bits or more is effective.

The frame modulation / transmission system, the time measuring means, and the circuit configuration of the synchronization determination circuit are not limited as in the present embodiment.

(Embodiment 3) Next, a synchronization detecting device 1c according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 6 is a block diagram illustrating a configuration of the synchronization detection device 1c according to the present embodiment. Among the components of the synchronization detection device 1c, the detection unit 10, the encoding unit 20, the comparison unit 30, and the time measurement unit 40 are the same as those of the second embodiment, and the description thereof will be omitted.
FIG. 7 is a timing chart showing the operation of the synchronization detection device 1c.

The synchronization determination circuit 50c shown in FIG. 6 is a circuit including a coincidence counter 501 and a non-coincidence counter 502. Similar to the second embodiment, the synchronization determination circuit 50c is a circuit that performs a synchronization determination during a period in which the value measured by the time measurement unit 40 is within a predetermined range as shown in FIG. 7C.
As shown at times t1, t2, t3, and t4 in FIG. 7B, when a pulse is output from the comparing unit 30 during the synchronization determination period in FIG. 7D, the value of the coincidence counter 501 becomes
Steps are advanced one by one as shown in FIG. And time t
When a predetermined value (= 3) is reached in step 3, the counting operation is stopped and the mismatch counter 502 is reset as shown in FIG. As shown at times t4, t5, and t6 in FIG. 7B, when there is no pulse output from the comparing unit 30 within the synchronization determination period, the value of the mismatch counter 502 becomes the value shown in FIG.
Are advanced one by one as shown in FIG. Then, when a predetermined value (= 3) is reached at time t6, the synchronization determination circuit 50c
Assuming that an out-of-synchronization has occurred, as shown in FIGS. 7C and 7E, the time measurement unit 40 and the coincidence counter 501
Reset. When the coincidence counter 501 has reached a predetermined value (= 3), the synchronization determination circuit 50 c
As shown in (g), a pulse is generated immediately after the synchronization determination period, and this is output as a synchronization detection result.

With the above-described configuration, the synchronization detecting device 1c according to the present embodiment can control the synchronization state when the encoded data sequence does not match the synchronization pattern continuously a predetermined number of times (= 3 times) with the frame period as a cycle. To cancel.
By introducing such a forward protection process, synchronous detection with higher reliability can be performed as compared with the second embodiment.

The encoding interval and the synchronization pattern length are
It is effective if the settings are made in the same manner as in the first and second embodiments. The frame modulation / transmission system, the time measuring means, and the circuit configuration of the synchronization determination circuit are not limited as in this embodiment.

(Embodiment 4) Next, a synchronization detecting apparatus according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 8 is a block diagram showing a configuration of the synchronization detection device 1d according to the fourth embodiment (part 1). Among the components of the synchronization detection device 1d, the detection means 10 and the encoding means 20 are the same as those in the third embodiment, and the description thereof will be omitted.

Each of the comparing means 30 to 33 is composed of a shift register and a combination circuit (not shown), and the circuit configuration is the same as that of the comparing means 30 of the first embodiment.
The same clock is supplied to the encoding means 20, the comparing means 30, and the frequency dividing circuit 60. The frequency dividing circuit 60 generates clocks obtained by dividing the input clock by two, four, and eight, respectively. The clock divided by two is output to the comparing means 31, the clock divided by four is output to the comparing means 32, and the clock divided by eight is output to the comparing means 33. Each comparison result of the comparison means 30 to 33 is output from the OR gate 7
0 and the output of the OR gate 70 is
This is the synchronization detection result of d.

Here, if the period of the input clock is set to 27 μs, six clocks of the clocks input to the comparing means 30 to 33 are set in the DAB transmission modes 3, 2, and 3 respectively.
It is almost equal to the null symbol section length of 4,1.

When a plurality of transmission modes are defined as in DAB, the synchronization detection device changes the input clock frequency to the comparison means after determining that synchronization is impossible in a specific transmission mode. It is necessary to try to detect synchronization in another transmission mode. In this case, it takes time to determine the transmission mode using one comparison unit. On the other hand, in the present embodiment, the determination of the transmission mode and the synchronization detection can be performed at high speed by operating the plurality of comparison means corresponding to each transmission mode in parallel.

FIG. 9 is a block diagram showing a configuration of a synchronization detecting device 1e according to the fourth embodiment (part 2). This synchronization detecting device 1e is different from the comparing devices 30 to 33 of the synchronization detecting device 1d in FIG. 8 in that a function of stopping a comparison operation when a pulse is input as a synchronization determination operation stopping means is added. 33e are provided. In this way, when the synchronization is detected in the specific transmission mode, the operation of the comparing means corresponding to another transmission mode can be stopped. This makes it possible to reduce the power consumption of the circuit after the synchronization is detected.

FIG. 10 is a block diagram showing the configuration of the synchronization detecting device 1f in the present embodiment (part 3). This synchronization detection device 1f is provided with a time measurement unit 4 for comparison units 30 to 33, which are components of the synchronization detection unit 1d in FIG.
0 to 43 and synchronization determination circuits 50 to 53 are added. According to such a configuration, it is possible to have the effects of the second and third embodiments in addition to the effects of the present embodiment. Note that it is also effective to combine the time measuring means and the synchronization determination circuit with the synchronization detection device of FIG.

Note that the coding interval and the synchronization pattern length are
It is effective if the settings are made in the same manner as in the first to third embodiments. The frame modulation / transmission system, the time measuring means, and the circuit configuration of the synchronization determination circuit are not limited as in this embodiment.

(Embodiment 5) Next, a synchronization detecting apparatus according to Embodiment 5 of the present invention will be described with reference to the drawings. FIG. 11 is a block diagram illustrating a configuration of the synchronization detection device 1g according to the present embodiment. This synchronization detection device 1g is obtained by replacing the comparison unit 30 in the synchronization detection device 1a of the first embodiment with a comparison unit 30g.

FIG. 12 is a block diagram showing the structure of the comparison means 30g. The comparison unit 30g includes a shift register 301, a synchronization pattern register 303, and a combination circuit 304. The same clock is supplied to all flip-flops included in the shift register 301 and the synchronization pattern register 303.

As in the first embodiment, the shift register 301 takes in an encoded data sequence for each clock and stores 8-bit data. When the write enable is at the H level, the synchronization pattern register 303 takes in an externally applied 8-bit synchronization pattern in synchronization with a clock. Combination circuit 304
Are the shift register 301 and the synchronous pattern register 30
A circuit that goes high when all three bits match, and this is output as a synchronization detection result.

In a multipath environment, a non-signal section (null symbol) may be shortened by adding a delayed reflected wave to a direct wave. When the no-signal section becomes short, for example, the synchronization pattern “10” used in the first embodiment is used.
In the case where the synchronization pattern cannot be detected with “000001”, the synchronization pattern can be detected by changing the synchronization pattern to “11000001”. In the synchronization detection device 1g of the present embodiment, by making the synchronization pattern variable, it is possible to flexibly cope with the time variation of the no-signal section under the multipath environment.

In the second to fourth embodiments as well, if the respective comparing means are changed as in the present embodiment, the effects of both the present embodiment and the respective embodiments can be obtained. Further, the circuit configuration of the comparing means is not particularly limited as in the present embodiment. For example, a function equivalent to that of the comparing means 30g can be realized using a general-purpose processor.

(Embodiment 6) Next, a synchronization detecting apparatus according to Embodiment 6 of the present invention will be described with reference to the drawings. FIG. 13 is a block diagram illustrating a configuration of the synchronization detection device 1h according to the present embodiment. This synchronization detection device 1h is obtained by replacing the comparison means 30 with the comparison means 30h in the synchronization detection device 1a of the first embodiment.

FIG. 14 is a block diagram showing the structure of the comparing means 30h. The comparison means 30h includes a shift register 301, a synchronization pattern register 303, a mask pattern register 305, and a combination circuit 306. Shift register 301, synchronous pattern register 3
03 and all flip-flops included in the mask pattern register 305 are supplied with the same clock.

As in the first embodiment, the shift register 301 takes in an encoded data sequence for each clock and stores 8-bit data. Synchronous pattern register 303 and mask pattern register 305
Captures an externally applied 8-bit synchronization pattern or mask pattern in synchronization with a clock when the write enable is at the H level. Combination circuit 306
Are the shift register 301 and the synchronous pattern register 30
Among the three bits, a circuit which goes to the H level when all the bits except for the bit set in the mask pattern register 305 match each other is the synchronization detection result.

In the fifth embodiment, the time variation in the no-signal section in a multipath environment is dealt with by changing the synchronization pattern. However, in the present embodiment, specific bits are excluded from the comparison with the synchronization pattern. Corresponding. For example, “11000001” including a null symbol section
Is obtained, and the synchronization pattern is “10”.
000001 ”. In this case, if the mask pattern register is set to "01000000", the seventh bit counted from the right is removed from the comparison target, and synchronization is detected.

As described above, the synchronization detecting device 1 of the present embodiment
In h, it is possible to flexibly cope with a time variation in a no-signal section under a multipath environment by not setting a predetermined bit in the synchronization pattern as a comparison target, as in the fifth embodiment.

In the present embodiment, the synchronization pattern is variable, but may be a fixed pattern. Also,
Also in the second to fourth embodiments, if the comparing means is changed as in the present embodiment, the effects of both the present embodiment and the respective embodiments can be obtained. Furthermore, the circuit configuration of the comparing unit is not particularly limited as in the present embodiment, and it is possible to realize a function equivalent to that of the comparing unit 30h using, for example, a general-purpose processor.

[0064]

As described above, according to the first to fifteenth aspects, the head of a frame can be detected even in a fading environment. Also, there is no synchronization in an incorrect transmission mode.

In particular, according to the second, third, and fifth aspects of the present invention, highly reliable synchronization can be detected by introducing the steps of rearward protection and forward protection.

In particular, according to the fourth, fifth, sixth and seventh aspects of the present invention, the determination of the transmission mode and the synchronization detection can be performed at high speed by operating the comparison means corresponding to each transmission mode in parallel. It is.

In particular, according to the eighth, ninth and tenth aspects of the present invention,
By making the synchronization pattern variable or excluding a specific bit from the comparison with the synchronization pattern, it is possible to flexibly cope with a time variation in a no-signal section under a multipath environment.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a synchronization detection device according to a first embodiment of the present invention.

FIG. 2 is a timing chart illustrating an operation of the synchronization detection device according to the first embodiment.

FIG. 3 is a timing chart showing an operation (under a fading environment) of the synchronization detection device according to the first embodiment.

FIG. 4 is a block diagram illustrating a configuration of a synchronization detection device according to a second embodiment of the present invention.

FIG. 5 is a timing chart showing the operation of the synchronization detection device according to the second embodiment.

FIG. 6 is a block diagram illustrating a configuration of a synchronization detection device according to a third embodiment of the present invention.

FIG. 7 is a timing chart showing the operation of the synchronization detection device according to the third embodiment.

FIG. 8 is a block diagram showing a configuration of a synchronization detection device (part 1) according to Embodiment 4 of the present invention.

FIG. 9 is a block diagram showing a configuration of a synchronization detection device (part 2) according to Embodiment 4 of the present invention.

FIG. 10 is a block diagram showing a configuration of a synchronization detection device (part 3) according to Embodiment 4 of the present invention.

FIG. 11 is a block diagram illustrating a configuration of a synchronization detection device according to a fifth embodiment of the present invention.

FIG. 12 is a configuration diagram of a comparison unit used in the synchronization detection device according to the fifth embodiment.

FIG. 13 is a block diagram illustrating a configuration of a synchronization detection device according to a sixth embodiment of the present invention.

FIG. 14 is a configuration diagram of a comparison unit used in the synchronization detection device according to the sixth embodiment.

FIG. 15 is a waveform diagram showing an OFDM reception signal in a fading environment.

FIG. 16 is a timing chart showing the operation of a conventional synchronous detection device.

[Explanation of symbols]

1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h Synchronous detection device 10 Detection means 20 Encoding means 30-33, 30e-33e, 30g, 33h Comparison means 40, 41, 42, 43 Time measurement means 50, 51, 52, 53, 50b, 50c Synchronization determination circuit 60 frequency divider 70 OR gate 201 comparator 202 latch 301 shift register 302 combination circuit 303 synchronization pattern register 304 combination circuit 305 mask pattern register 306 combination circuit 501 match counter 502 mismatch counter

Claims (15)

[Claims] 1. A synchronous signal for detecting a frame synchronizing signal by receiving a transmission signal in which a non-signal interval of a fixed length is inserted into a modulation signal at regular intervals, and identifying the non-signal interval of the transmission signal. A detection device, comprising: a detection unit that performs envelope detection on the transmission signal; an encoding unit that binarizes the envelope signal obtained by the detection unit and encodes the binary signal at a predetermined clock cycle; And a comparing means for comparing the coded data sequence obtained by the above with a predetermined synchronization pattern and determining whether or not the two coincide with each other. 2. A synchronous signal for detecting a frame synchronizing signal by receiving a transmission signal in which a non-signal interval of a fixed length is inserted at a constant interval with respect to a modulation signal and identifying the non-signal interval of the transmission signal. A detection device, comprising: a detection unit that performs envelope detection on the transmission signal; an encoding unit that binarizes the envelope signal obtained by the detection unit and encodes the binary signal at a predetermined clock cycle; Comparing the encoded data sequence obtained by the above with a predetermined synchronization pattern and determining whether or not the two coincide with each other; and inputting a comparison result indicating a match from the comparison unit, generating the comparison result Time counting means for calculating the frame period by counting a cycle, and an encoded data string obtained by the coding means, with the frame period obtained by the time measuring means as a cycle A predetermined number of times continuously checks whether coincides with the predetermined synchronization pattern, the synchronization detection device characterized by comprising a synchronization judging means for judging a synchronization state in the case of coincidence, the. 3. The synchronization determining means, wherein the coded data sequence obtained by the coding means is continuously synchronized with the predetermined synchronization pattern a predetermined number of times with a frame period obtained by the time measuring means as a cycle. 3. The synchronization detecting device according to claim 2, wherein when the values do not match, the determination of the synchronization state is canceled. 4. A synchronizing method comprising: receiving a transmission signal in which a non-signal section having a fixed length is inserted into a modulation signal at regular intervals, and identifying a non-signal section of the transmission signal to detect a frame synchronizing signal. A detection device, comprising: a detection unit that performs envelope detection on the transmission signal; an encoding unit that binarizes the envelope signal obtained by the detection unit and encodes the binary signal at a predetermined clock cycle; A plurality of comparing means for comparing the encoded data sequence obtained by the above with a predetermined synchronization pattern corresponding to each transmission mode, and determining whether or not the two coincide with each other. apparatus. 5. A synchronizing method for receiving a transmission signal in which a non-signal section having a predetermined length is inserted at a predetermined cycle with respect to a modulation signal and identifying a non-signal section of the transmission signal to detect a frame synchronizing signal. A detection device, comprising: a detection unit that performs envelope detection on the transmission signal; an encoding unit that binarizes the envelope signal obtained by the detection unit and encodes the binary signal at a predetermined clock cycle; First to k-th comparing means for comparing the encoded data sequence obtained by the above with a predetermined synchronization pattern corresponding to k kinds of transmission modes to determine whether or not the two coincide with each other; A comparison result indicating a match is input from the comparison means (i = 1 to k), and the generation period of the comparison result is counted to calculate the frame period of each transmission mode.
(I = 1 to k) time measuring means, and the coded data string obtained by the coding means are respectively consecutively repeated a predetermined number of times with the frame period obtained by the i-th time measuring means as a cycle. When the transmission mode matches the synchronization pattern of the transmission mode, the i-th
(I = 1 to k) synchronization determining means. 6. The i-th synchronization determination means, wherein the encoded data sequence obtained by the encoding means is continuously transmitted a predetermined number of times with a frame period obtained by the i-th time measurement means as a cycle. 6. The synchronization detecting device according to claim 5, wherein the determination of the synchronization state is canceled when the synchronization pattern does not match the synchronization pattern of each transmission mode. 7. A synchronization determination operation stopping means for stopping a synchronization determination operation in another transmission mode after determining a synchronization state in the specific transmission mode. Synchronization detection device. 8. The synchronization detection device according to claim 1, wherein the comparison unit can arbitrarily set a synchronization pattern used for comparison with the encoded data sequence. 9. The method according to claim 1, wherein the comparing unit excludes a predetermined bit from a comparison target in the synchronization pattern used for comparison with the encoded data sequence. Synchronous detection device according to the above. 10. The synchronization detecting apparatus according to claim 9, wherein said comparing means can arbitrarily set a bit to be excluded from a comparison target. 11. The comparison means includes: a shift register for temporarily holding the encoded data string; a register for holding the synchronization pattern; data held in the shift register; and data held in the register. And a combinational circuit for determining whether or not と matches.
Synchronous detection device according to the above. 12. The comparison means, comprising: a shift register for temporarily holding the encoded data string; a first register for holding the synchronization pattern; and a shift register for specifying a position of a bit to be excluded from the comparison. 2 and whether the data value held in the shift register matches the data held in the first register, except for the bit positions set in the second register. 11. The synchronization detecting device according to claim 10, comprising a combination circuit. 13. The modulation signal includes a plurality of OFDM signals having a guard interval of a predetermined length.
13. The synchronization detecting device according to claim 1, wherein the symbol is an (orthogonal frequency division multiplex) symbol. 14. The synchronization detecting apparatus according to claim 13, wherein said clock cycle of said encoding means is equal to or less than 1/2 of said guard interval length. 15. The synchronization pattern used by the comparing means is a pattern of {(n / d) +2} bits or more, where n is the no-signal section length and d is the clock cycle of the encoding means. 15. The synchronization detection device according to claim 14, wherein: