JP2000298616A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a general purpose memory controller which has a burst start end function, a jump function, a line feed function, a refresh function and a sequence control function for them, makes an SDRAM (synchronous DRAM) efficiently operate and executes all control about the SDRAM. SOLUTION: An address generating part 110 makes a designated address an initial value and generates row and column addresses of an SCRAM 104 and a line feed signal by using an address counter during burst transfer. A command generating part 108 generates a timing signal for plural commands that execute processing of start processing, jump processing, end processing and line feed processing according to a request and also holds a jump processing request or an end processing request when the jump processing request and the end processing request come during the line feed processing. A refresh generating part 109 generates the timing signal for a refresh command according to the periodical request and also holds a refresh request till a prescribed point of time when the refresh request comes during the burst transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory controller, and more particularly to a controller for burst transfer in an SDRAM (Synchronous DRAM) memory.

[0002]

2. Description of the Related Art An SDRAM memory is a DRAM memory that operates in synchronization with an externally input clock. Since the internal operation is pipelined by the clock to reduce the cycle time, the burst transfer frequency, especially in the page mode, can be improved several times as compared with a normal DRAM memory. On the other hand, short-word-length random access is sufficient to maintain the performance of a normal DRAM memory.

In order to control random access and burst transfer of the SDRAM memory, a series of SDRAMs is used.
An SDRAM controller that generates and supplies commands and addresses is required.

Conventionally, this type of SDRAM controller has
They have been individually designed according to the conditions of the SDRAM device, the data to be processed and the processing device. Where SDRA
The relationship between the type of command given to the SDRAM by the M controller and the internal operation will be described. The storage element array (each bit plane) inside the SDRAM is arranged two-dimensionally in rows and columns. First, a row address is given by an ACT (activation) command, and subsequently, a column address is given by READ or W.
When given by a RITE command, the READ or WRITE command is executed the number of times specified in advance by the MODE command. The number of times (word length) is, for example, 1, 2, 4, 8, F
You can select from five types of ULL. At this time, the row address is fixed and the column address usually changes in a direction to increase by one. FULL is a mode for reading and writing an entire row, called a burst transfer mode, and is terminated by a BST (burst stop) command or a PCG (precharge) command. PC
The G command terminates access to the row and returns to the SDRAM
Command to return to the precharge (inactive) state.
With the subsequent ACT command, the next line can be accessed (line feed operation) or restarted from any row and column (jump operation). When a REF command is given in the precharge state, the memory element is refreshed. The REF command needs to be continuously given at regular time intervals.

[0005] As an example of a memory controller using an SDRAM, there is a document: "JP-A-10-27155 (data transfer control device)". Although the memory controller described in this document is used for image processing and compression / decompression, there is no SDRAM controller widely applicable to multimedia processing including character recognition and voice recognition matching processing.

[0006]

As a design problem of the SDRAM controller, first, in a situation where a burst transfer sequence is frequently performed on the SDRAM,
It is necessary to prevent the overhead of the SDRAM command for the transfer control from deteriorating the performance.

In addition to the transfer control, it is necessary to incorporate commands for line feed operation and refresh operation required for the SDRAM itself at the correct timing to avoid conflict. Further, there is a need to provide a high-level interface that absorbs the diversity of SDRAM device specifications.

An object of the present invention is to endure a high-speed clock,
It has a burst start / end function, a jump function, a line feed function, a refresh function, and an order control function for these functions.
It is an object of the present invention to provide a general-purpose memory control device that allows an AM to operate efficiently and performs all control related to an SDRAM.

[0009]

For this purpose, a memory control device according to the present invention includes an address generation unit, a command generation unit, and a refresh generation unit, and controls a burst transfer between a data processing device and a clock synchronous SDRAM. In the memory control device, the address generating means includes:
The address specified by the data processing device is used as the initial value,
A row address, a column address and a line feed request signal of the SDRAM are generated by using an address counter that counts during the burst transfer, and the command generation means starts, jumps, and ends according to a request from the data processing device or the address generation means. In addition to generating a timing signal of a plurality of SDRAM commands for executing each of the processing and the line feed processing, if there is a jump processing request or an end processing request during the line feed processing, the timing is maintained until the line feed processing is completed. The jump processing or the end processing request is suspended, and the refresh means generates a refresh command timing signal in accordance with the periodic request, and, when there is a refresh request during the burst transfer, the start processing, the jump processing,
The refresh request is held until a line feed process or an end process is executed.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Description of First Embodiment] [Description of Configuration] (a) Overall Configuration FIG. 1 shows an SDRAM of a memory control device according to an embodiment of the present invention.
FIG. 3 is a peripheral and internal configuration diagram of a controller. A data processing device 105 stores data input from an input terminal 101 in an SDRAM 104, performs data processing, and outputs the result to an output terminal 106.

The SDRAM controller 107 is a circuit which is provided between the data processing device 105 and the SDRAM 104 and controls a burst transfer via the data bus D _31-0 103. The SDRAM controller 107 includes a command generation unit 108, a refresh generation unit 109, It comprises an address generator 110.

These interconnections will be apparent from the following description of each unit. Note that the entire configuration of FIG. 1, the configuration of the command generation unit 108 of FIG. 2, and the refresh generation unit 1 of FIG.
The configuration 09 is common to all the following embodiments.

Further, the entire system operates in synchronization with a clock CLK100 having a fixed frequency (for example, 66 MHz).

(B) Configuration of Command Generation Unit FIG. 2 is a configuration diagram of the command generation unit 108,
RT1 (start) 121, JUMP2 (jump) 122, E
A pulse signal indicating each operation request such as ND2 (end) 123 and LF1 (line feed) 124 is input, and as an output signal,
PCG (precharge) command 133, ACT (active) command 134, RWC (READ / WRITE)
E) Generate command 135 and other timing pulse signals.

The command generation unit 108 has a JUMP
REQ (jump request) 125 and ENDREQ (end request) 126 holding flag, SDBUSY0
(SDRAM busy) 127, SDBEGIN (start processing) 128, SDJUMP (jump processing) 129, LFB
Each operation display flag of USY (line feed processing) 130, 3-bit LBC counter 131, LBC decoder 132,
In addition, it comprises gates and operates as an order control circuit for generating an SDRAM command sequence.

A memory enable (MENB) 136 indicates that a burst transfer is being performed (read or write).
The BD signal 137 is a read data valid signal generated by the delay circuit 138 and transmitted to the data processing device 105. The internal configuration of the delay circuit 138 is omitted for simplicity.

(C) Configuration of Refresh Generation Unit FIG. 3 is an internal configuration diagram of the refresh generation unit 109, which is a control circuit for periodically refreshing the SDRAM. The refresh generation unit 109 includes a REF input terminal 141, a REFREQ flag 142, and a REFBU
SY flag 143, 3-bit RBC counter 14
4, RBC decoder 145, and other gates,
REF command 146 timing is generated. The refresh generation unit 109 and the command generation unit 108
The FEN signal 147 and the REFBUSY1 signal 148 are connected.

(D) Configuration of Address Generation Unit FIG. 4 is a configuration diagram of the address generation unit 110 of the SDRAM controller according to the first embodiment of the present invention.
It has a DRAM address counter ADRC151 and has 12
Bit address signal A _11-0 152, CS signal 153, R
An AS signal 154, a CAS signal 155, and a WE signal 156 are generated and supplied to the SDRAM 104.

In addition, SDRAMs include DQM, CKE
, But are omitted for simplicity. The R / W signal 167 distinguishes between READ and WRITE.

The multiplexer (MUX) 157 is a PC
The G command 133, the ACT command 134, and the RWC command 135 are each delayed by 1 CLK, and are respectively PCGA (not described) 166, ROWA (upper 12 bits of ADRC), and COLA (lower 8 bits of ADRC).
Is output to the address signal 152. 3
The DFFs 158 and the registers 159 are used as one-clock delay elements.

The ADRC counter 151 is connected to a jump address JA _19-0 161, a LOAD signal 163, a MENB signal 136, and an SDBUSY signal 165.

[Explanation of Operation] Here, the SDRAM has been initialized by an SDRAM mode command (not shown).
The operation of each part of the DRAM controller will be described.

(A) Operation of Command Generator 108 (FIG. 2) First, an outline of the operation will be described, and then a timing chart will be described. The read operation of the SDRAM will be mainly described.
The same applies to the te operation.

The burst transfer of the SDRAM is performed by a START1 (start processing) pulse 121 from the data processing device 105.
Is started by In the start process, three commands are issued to the SDRAM to start burst transfer. SDR
The head address of the AM is given to the address generator 110 as a jump destination address JA _19-0 161.

Subsequent to the start processing, for example, the SDRAM 1
Rows, 256 columns × 32 bits are read out at a burst speed of 66 MHz, and a continuous area of the SDRAM is read out row by row with line feed processing interposed. In the line feed processing, reading is normally interrupted for 8 CLK periods. Returning to the precharge state during this period, the next row (256w) is activated, and burst reading is restarted. The line feed cycle is about 4 μs. In the precharge state, a refresh cycle (8 CLK) can be inserted. The line feed processing also serving as refresh suspends reading for 16 CLK periods.

During the burst transfer, jump processing can be performed. The data processing device 105 outputs the jump pulse (JU
MP2) 122 and the jump address JA _19-0 161 are instructed to the SDRAM controller 107. The jump processing is a row update processing involving address resetting (ADRC load), and jumps to an arbitrary address (row and column) to resume burst transfer.

As described above, the SDRAM transfer starts with the start processing, proceeds while performing the line feed processing and the jump processing, and continues until the end instruction (END1 or END2) is given.

The start processing, the line feed processing, and the jump processing are each an LFBUSY sequence (period of LFBUSY = 1) consisting of eight steps (LBC = 0 to 7), for example, the following three SDRAM commands are issued. LBC = 1 PCG (precharge) command 133: Set to precharge state. LBC = 4 ACT (active) Command 134: Sends the row address. LBC = 7 RWC (READ or WRITE) command 135: Sends the column address. Each command is stored in the address generation unit 110 in the SDRAM.
And outputs the signal delayed by 1 CLK. RWC command 135
Starts burst READ or WRITE of the SDRAM. This is a READ command in SDRAM reading.

The end process is an LFB consisting of four steps.
In the USY sequence, only the PCG command is issued with LBC = 1, and the process ends when the SDRAM enters the precharge state (LBC = 3).

FIG. 5 is a timing chart of the command generation section and the address generation section.
S comprising LK start processing, 5w data read, 8CLK line feed processing, 3w data read, and 4CLK end processing
21 shows 21 signal waveforms in a DRAM read sequence.

In the start processing and the line feed processing, three SDRA
The M command is issued, and 5 w data is read while counting ADRC during the 5 CLK period during which (LFBUSY = 0). It is the MENBD signal after DL = 3CLK that the read data becomes valid in the data processing device.

Line feed processing is started by the LF1 signal from the address generator 110. After line feed processing LFBUSY =
When it becomes 0, it returns to burst transfer again.

The end processing is started by the END1 signal 181. For example, if the number of words to be transferred is the end condition, this E
The termination process is started from the ND1 signal. The transfer word number counter is omitted for simplicity.

The SDBUSY0 signal 127 is START1
A flag which is set by the signal 121 and reset by the END1 signal 181 is used for end control.

The SDBUSY signal 165 is a High level signal from the start of the start process to the end of the end process, and is generated by the following equation. SDBUSY = SDBUSY0 | LFBUSY In the logical expressions, | represents a logical sum, & represents a logical sum,
￣ indicates negation.

(B) Operation of Refresh Generation Unit (FIG. 3) The REF command 146 is issued periodically for refreshing the SDRAM. A REF2 pulse 141 is input once every 14 μs using a timer, and REFREQ
The flag 142 is set to 1. The timer circuit is omitted for simplicity. At this time, the REFSTART signal 1 of the following equation
A refresh start condition is given by 49. REFSTART = REFREQ & REFEN = REFREQ & (~ SDBUSY | L
BC = 2)

If not during SDBUSY, REFSTA
Since RT = 1, the REFBUSY =
1 and the RBC counter 144 sets the RE for 8 CLK periods.
Activate the FBUSY sequence (RBC = 0-7),
A REF command 146 is issued when BC = 1.
After that, during the 7 CLK period, the command generation unit 108 is set to LBC = 0 and held in a hold state by the REFBUSY1 signal 148.

A refresh request during a burst is waited until the SDRAM is brought into a precharge state (LBC = 2) by line feed processing, jump processing, and termination processing, and between a precharge command and an active command (LBC = 2).
In step 3), the refresh processing for 8 CLK is inserted.

This waiting time is set at the timer interval (14 μs).
Not to exceed. In the case of a 256-column SDRAM, line feed processing is performed 3.5 times on average during the timer interval (14 μs), so line feed processing also serving as refresh is executed once every 3.5 times.

FIG. 6 is a timing chart of the refresh generation unit.
This shows how three refreshes are performed when the REF2 pulse 141 is given three times in a row, regardless of the timer.

At the first REFREQ = 1, still SDBU
Since SY is not 1, REFBUSY 143 is immediately activated. During the refresh period, SDBUSY, LFB
Each flag of USY is set, but since the LBC counter is REFBUSY1 = 1, LBC = 0 of the start processing
And waits for the end of REFBUSY. 7CLK
After returning to REFBUSY1 = 0 later, the process proceeds to LBC = 1 and executes the start processing.

When REFREQ = 1 for the second time, SDBU
Since SY = 1, the process waits until the start process is approved by LBC = 2, holds the command generation unit by the next LBC = 3, and executes the refresh again.

In the third REFREQ = 1, SDBU
Since SY = 1, the process waits until the end processing is approved by LBC = 2, and the refresh is executed from the next LBC = 3. In this case, the command generator is not held,
SDBUSY and LFBUSY are reset and the process ends.

(C) Operation of Address Generation Unit (FIG. 4) During data reading (or writing), the SDRAM address counter (ADRC) counts with the SDRAM head address set in the address input JA _19-0 161 as an initial value. Each time an end of line is detected, a line feed process is started by the LF1 signal 124. Line feed processing in progress (LFBUSY =
In 1), MENB = 0, and the ADRC suspends counting. In a 256 column SDRAM, the column number 255 is at the end of the row.

In the jump processing, the ADRC suspends the counting operation and sets the jump destination address JA _19-0.
Is loaded into the ADRC. When data reading resumes, the address count also resumes.

The following signals are used for controlling the address counter ADRC [19: 0].・ CLRN = SDBUSY: Release clear only during transfer processing. LDAD = LOAD: Loads JADR with LBC = 1 for start processing and jump processing. • ENP = MENB = SDBUSY0 & ~ LFBUSY: Counts during burst transfer.

The value of ADRC is the number of device rows (here, 2
56) is divided into a row address and a column address according to
The row address ROWA is changed to READ / W by the ACT command.
Column address COLA is output from the A _11-0 at RITE command.

The transmission of the SDRAM command is performed by the CS signal 15.
3 is set to Low level, and the type of command is coded into 3 bits of RAS, CAS, and WE, and SDR
When given to AM, it is taken in synchronization with CLK.

(D) Operation to Avoid Competition between Jump Processing / End Processing and Line Feed Processing FIG. 7 is a timing chart of the conflict between the jump processing / end processing and line feed processing. SDRAM during line feed processing
If there is a jump request (JUMPREQ = 1), the line feed processing ends (LFBUSY = 0), and the jump processing is executed. That is, the jump processing start condition is given by the logic of the LFSTART signal 139 in the following equation. LFSTART = JUMPREQ & ~ LFBUSY

After the line feed processing is completed, the jump processing (SDJUMP = 1) starts from the next CLK in which LFBUSY = 0, and LFBUSY = 1 again. There is a 1w read between these two processes. During the jump process, the read data is invalidated by applying an AND gate to the MENBD signal 137 to the data processing device 105. This operation is performed by the delay circuit 1
38.

The right part of FIG. 7 is a timing chart of the conflict between the line feed processing and the end processing. If there is a burst end request during SDRAM line feed processing, the LFS of the following equation is used.
The end signal is activated by the logic of the TART signal 139. LFSTART = ENDREQ & ~ LFBUSY

After the end of the line feed processing, the end processing starts from the next CLK when LFBUSY = 0. There is a 1w read between these two processes, but this is ignored by the data processing device.

As described above, S in the first embodiment
In the DRAM controller, the address counter of the address generation unit tracks and counts the SDRAM address in real time, and a line feed process is automatically executed each time the end of a line is detected.
Facilitates DRAM read / write control.

Also, by loading an arbitrary value to the address counter, it is possible to jump to an arbitrary address of the SDRAM, so that unnecessary data portions of the SDRAM can be skipped, and block data scattered in various places can be efficiently read and written.

When a jump request or end request of the SDRAM occurs during a line feed process, control is made to wait until the first word of the next line is accessed, and then execute the jump process or the end process. Does not generate a complicated sequence.

Note that the SDRAM is used between the line feed processing and the jump processing.
Since an extra word read from is masked during the jump processing, it is not misused by the data processing device.

A refresh command is automatically issued at regular time intervals by the refresh generator. SD
While the RAM is busy, the refresh is executed until the pre-charge state of the start processing, the line feed processing, and the jump processing is executed, so that the control from the data processing device becomes easy.

[Explanation of Second Embodiment] [Description of Configuration] In the SDRAM controller of the first embodiment, when the clock cycle is short, the number of bits of the ADRC counter is as large as 20 bits, so that the count-up (increment) is increased. There is a risk that time will be insufficient. Also, since the value of ADRC is sent to the _A11-0 terminal of the SDRAM without register, there is a possibility that the setup time is insufficient in the SDRAM device.

FIG. 8 is a block diagram of the address generator 110 of the SDRAM controller of the second embodiment, which differs from the first embodiment in the following points. ADRC is divided into lower 10 bits and upper 10 bits, and counted up by two consecutive clocks. (Hereinafter referred to as double-length count) The count enable signal of the lower 10 bits of the ADRC is advanced by 1 CLK. (Hereinafter prior referred to as counts) adding a delay register 184 before the A _11-0 output 152.

The ADRC preceding count is obtained by counting the lower 10 bits of the ADRC counter as “Enable”.
Use the next MENBA signal 182 instead of the next MNB signal 136, MENB = SDBUSY0 & ~ LFBUSY. MENBA = (1 CLK ahead of MENB) = MENB & ~ LFSTART |
LBC7

The method of ADRC double counting is ADRC
In the load, increment, and hold CLK synchronous operations, the increment is changed to the 2CLK operation.

The lower 10 bits of ADRC are MENBA
= 1 and increment carry by ADRCRY18
5 at the next CLK (with MENB = 1)
Add ADRCRY to the bit. During this 2CLK period,
Since SDBUSY = 1 and LOAD = 0, no count error occurs.

The LF signal generated from the lower ADRC is 1
CLK is advanced, so that signal is used as the LF2 signal 183,
A signal that is delayed by 1 CLK is issued as a LF1 signal 124 to the command generator 108 to request a line feed.

[Description of Operation] FIG. 9 is a timing chart of the second embodiment. As in the timing chart of the first embodiment shown in FIG. 5, start processing, data reading 5w, line feed processing, data reading 3w, 21 shows 21 signal waveforms in an SDRAM read sequence including a termination process.

In FIG. 9, the 1CLK preceding signal M of the MENB
Lower 10 bits of ADRC counter with ENBA, 1CL
K counts earlier. ADRC is 0 from 003ff
It temporarily becomes 00000 while changing to 0400. At this time, the intermediate carry bit is in the transient state of ADRCRY = 1.

Since the 8 bits of the column address are counted in advance, the SDR is delayed by 1 CLK in the buffer register 184.
Send to AM. Therefore, the shortage of the setup time of the address terminal A _11-0 is solved.

Further, the counting operation of the upper 10 bits of the ADRC does not involve carry propagation of the lower 10 bits, so that the shortage of time is solved.

Since the line end detection signal LF2 is advanced by 1 CLK, a line feed instruction is issued by the LF1 signal delayed by 1 CLK.
Therefore, the counting operation of the lower 10 bits of the ADRC can be executed with a margin.

As described above, the SDR of this embodiment
The AM controller operates with a high-speed clock even if the number of bits of the SDRAM address counter increases, since the counter is divided into lower and upper bits and counting is performed in a pipeline with the subsequent 2CLK.

Since the lower part of the address counter counts 1 CLK ahead, if all or part of the lower part of the counter is used as the column address of the SDRAM, one stage of register buffer can be inserted in the path for transmitting _A11-0 . There is no danger of running out of setup time.

The line feed instruction signal for starting a line feed is also advanced by 1 CLK. Therefore, if one flip-flop is inserted, there is no possibility that the command generator 108 fails to start. Therefore, the clock frequency can be increased, and the performance can be improved.

[Explanation of Third Embodiment] [Description of Configuration] Although the first and second embodiments use the full page mode SDRAM, there are some SDRAM devices that do not support the full page mode. For example, 8
In word burst mode, Read / Write every 8 words
The address must be supplied by the command.

FIG. 10 shows an address generator of the SDRAM controller according to the third embodiment. The following BST signal 191 is generated and added to the RWC signal 135 of the address generation unit of the second embodiment by performing a logical OR operation. BST = BL4 & ~ ADRC [0] & ~ ADRC [1] & MENB | BL8 & ~ AD
RC [0] & ~ ADRC [1] & ~ ADRC [2] & MENB Here, in the mode of burst length = 4, BL4 = 1, B
In a mode in which L8 = 0 and burst length = 8, BL4
= 0, BL8 = 1, and in the full page mode, BL
4 = 0, BL8 = 0.

The full page mode has the same logic as in the second embodiment. The MENB signal 136 is a signal indicating that the burst transfer is being performed, and is a signal used for the count enable of the upper ADRC. The input signals other than the MENB signal 136 to the ADRC counter 151 in FIG.
It is omitted because it is the same as.

[Description of Operation] FIG. 11 is a timing chart of the third embodiment.
Attempt to read 16w during K period. In the full page mode, a READ command may be issued during the first CLK period. In that case, addresses from address e2 to address f1 are read.

Here, considering the operation in the mode of burst length = 4, e2, e3, e0,
Each address of e1 is read out in this order, and the subsequent 12CLK
Does not read anything. That is, the lower 2 of the column address
The bit is counted modulo 4 and 4 w is read. Therefore, it is necessary to give another address e4 at the third CLK (address e0).

Therefore, BL4 = 1 and BL8 = 0 in FIG.
And a burst length of 4, the BST signal 19 in FIG.
One generates four pulses every 4 CLK. This is S
The addresses e4, e8, ec, and f0 are sent to the DRAM together with the four READ commands, and addresses e4 to f1 are continuously read.

Since the READ command by the first RWC pulse is replaced on the way by the READ command by the BST pulse 191, addresses from address e2 to address f1 are read as expected.

When BL4 = 0 and BL8 = 1 and the burst length is set to 8 in FIG. 10, the BST signal generates two pulses every 8 CLK. This is because e8,
Each address of f0 is sent out with two READ commands, which has the same result.

As described above, S in the third embodiment
When using the SDRAM in the mode in which the burst length is 4 or 8, the address generation unit of the DRAM controller sends a READ command every 4 CLK and every 8 CLK, respectively, to the lower 2 bits and 3 bits of the ADRC counter 151 respectively.
The same result can be read out at the same timing as in the full page mode.

Since the lower part of the ADRC counts 1 CLK ahead of the SDRAM address, the address value can be transmitted with a margin by delaying in the buffer register.

[Explanation of Fourth Embodiment] [Description of Configuration] In the above embodiments, the column address is 8
Only the SDRAM device having a 12-bit row address and a 12-bit row address is handled, but the column address COLA is 8, 9, 10b
row address ROWA is 12,14 bits
There are two kinds of changes. Consider an address generator that can be applied to any of these SDRAMs. It is also considered to extend the chip in the address direction.

FIG. 12 is a block diagram of the address generator 110 of the SDRAM controller according to the fourth embodiment. This is different from the second embodiment in that the address generator ADR
The point that the shifter SFT201 is added after the C counter,
The point that the ADRC 151 is increased to 23 bits, the column address COLA is increased to 10 bits, the row address ROWA is increased to 14 bits, the generation logic of the LF2 signal is changed, CS
The difference is that the number of signals is increased to two.

The CS-0 signal 202 and the CS-1 signal 203
Is connected to each CS terminal of two SDRAMs of the same type,
Other signals (address, data, control signals) are assumed to be commonly connected to the two SDRAMs.

The C1 signal 205 and the C2 signal 206 are SDR
Decide which of the following three types of AM columns to use. When C1 = 1, C2 = 0: 256 columns SDRAM: New line at 255: SFT
2-bit shift When C1 = 0, C2 = 1: 512 columns SDRAM: 511, line feed: SFT
1-bit shift When C1 = 0, C2 = 0: 1024 columns SDRAM: 511, line feed: SFT
0 bit shift

The R1 signal 207, the R2 signal 208,
The R3 signal 209 outputs two CS-0 and CS-1 signals as A
Which bit of the DRC is selected is determined as follows. When R1 = 1, R2 = 0, R3 = 0: Chip selection by ADRC [20]. When R1 = 0, R2 = 1, R3 = 0: Chip selection by ADRC [21]. When R1 = 0, R2 = 0, R3 = 1: Select the chip by ADRC [22]. When R1 = R2 = R3 = 0: Only CS-0 is selected.

[Description of Operation] When the column address COLA is 8,
The description will be made separately for each of three cases of 9, 10 bits. However, the clock frequency is 66 MHz. (A) Operation of 256-column SDRAM When using a 256-column SDRAM, C1 = 1, C2
= 0. Since the output of the OR gate 210 is 1, A
When the lower 8 bits of the DRC are 1, that is, 255, the line feed signal LF2 = 1, and LF1 = 1 at the next CLK to start line feed processing. The line feed period of a continuous burst that spans a line is about 4 μS.

The shifter enters the 2-bit shift mode. This sends ADRC [8] to ROWA [0], and similarly sends ADRC [21] to ROWA [13]. CO
The upper two bits of LA may be anything. ADRC [19] comes out to ROWA [11], which was the most significant bit up to the previous embodiment. Therefore, A _11-0 ignoring COLA, the upper respective 2bit of ROWA is the same as before embodiment.

Further, it can be expanded in the address direction by using a plurality of chips. In this case, R1 = R2 = R3 =
If it is set to 0, CS-0 is the same as CS up to the previous embodiment.

If R1 = 1, R2 = 0, R3 = 0,
While ADRC [20] = 0, CS-0 is the same as the previous embodiment CS, and CS-1 has a PCG command and REF
Only send commands. When ADRC [20] = 1, CS-1 is the same as the previous CS, and CS-0 is
Only G command and REF command are transmitted. Thus, a chip is selected by ADRC [20].

In the same 256-column SDRAM, an SDRAM having a column address of 8 bits and a row address of 14 bits,
If R1 = 0, R2 = 0, and R3 = 1, ADRC [2
2] can select a chip.

(B) Operation of 512-column SDRAM When a 512-column SDRAM is used, C1 = 0, C2
= 1. The output of the OR gate 210 is ADRC [8]
Therefore, the lower 9 bits of ADRC are all 1, that is, 5
At the time of 11, a line feed signal LF2 = 1 is output, and LF is output at the next CLK.
1 = 1 is issued and the line feed processing is started. The line feed period of a continuous burst over a line is about 8 μS.

The shifter enters the 1-bit shift mode. This puts ADRC [8] into COLA [8] and ADR
C [9] is output to ROWA [0], and ADRC is similarly performed.
[22] is sent to ROWA [13]. Top 1 in COLA
The bit can be anything.

FIG. 13 uses 512 columns of SDRAMs.
This is an SDRAM read sequence when CS-0 and CS-1 are selected in ADRC [22]. Start address ADRC = 3ffffb to ADRC = 400002
Up to 8 words are accessed. The first five words are CS-0
The SDRAM on the side and the last three words access the SDRAM on the CS-1 side.

Of the 23 bits of ADRC, the lower 9 bits are in the column address, the highest 1 bit is in CS, and the middle 13
bit is used for the row address. Also, 3ffffff
When counting up from 00000 to 400 000, double-length counting is performed.

(C) Operation of 1024-column SDRAM When a 1024-column SDRAM is used, C1 = 0 and C
2 = 0. The output of OR gate 210 is ADRC
[8] So, 9 bits out of the lower 10 bits of ADRC
Are all 1, that is, at two places where the column numbers are 511 and 1023, a line feed signal LF2 = 1 is output, and LF1 = is output at the next CLK to start line feed processing. This is a line feed twice in one line in order to make the line feed cycle, which is originally 16 μS, shorter than the refresh interval (14 μS).

The shifter enters the 0-bit shift mode. This sends ADRC [8: 9] to COLA [8: 9], sends ADRC [10] to ROWA [0], and so forth, and sends ADRC [22] to ROWA [12]. RO
The highest 1 bit of the WA is set to 0. 1024 rows of SDR
Even in AM, chip selection can be performed using the remaining ADRC bits in the higher order, and the number of words can be doubled.

As described above, S in the fourth embodiment
In the SDRAM address generator of the DRAM controller, since a shifter is inserted between the ADRC and the multiplexer, one row has 256 columns, 512 columns, and 1024 columns.
It can also be used in DRAM devices.

As can be seen from the description of each of the above embodiments, the SDRAM controller of the present invention stores a standard pattern in character recognition, voice recognition and the like in the SDRAM, and reads out the reference pattern while skipping unnecessary portions of the standard pattern. Suitable to perform. Further, it is suitable to be used as an interface for coupling an LSI data processing device and an SDRAM device.

[0100]

As described in detail above, according to the first aspect of the present invention, in a memory control device for controlling a burst transfer between a data processing device and a clock synchronous SDRAM, Using a designated address as an initial value and a row address of the SDRAM using an address counter counting during the burst transfer,
Address generation means for generating a column address and a line feed request signal; and start processing, jump processing, end processing,
A plurality of SDRAM command timing signals for executing each of the line feed processing are generated, and during the line feed processing, if the jump processing request or the end processing request is issued, the line feed processing is terminated. Command generation means for suspending the jump processing or the termination processing request, and generating a refresh command timing signal according to a periodic request, and during the burst transfer,
When the refresh request is issued, the refresh request is held until the start processing, the jump processing, the line feed processing, or the end processing is executed. The address counter of the means tracks and counts the SDRAM address in real time, and a line feed process is automatically executed each time the end of a line is detected. This facilitates read / write control of the SDRAM over a plurality of lines from the data processing device. Also, by loading an arbitrary value to the address counter, it is possible to jump to an arbitrary address of the SDRAM.
There is an effect that unnecessary data portions can be skipped and block data scattered in various places can be efficiently read and written.

According to the second aspect of the present invention, the address counter is divided into at least a lower half of the counter including the column address and an upper half of the remaining counter. Since the counter is counted one clock ahead of the upper half of the counter, if all or part of the lower part of the counter is used as the column address of the SDRAM, one stage of register buffer can be inserted into the address transmission path. Therefore, there is no danger of running out of setup time. Further, since a line feed instruction signal for starting line feed is also advanced by 1 CLK, the flip-flop is set to 1
If the stage is inserted, there is no danger that the command generation means will fail to start, and the clock frequency can be increased.

Further, according to the third aspect of the present invention, in the mode where the burst length is N (where N is 2 to the power of n),
When the RAM is used, the column address is sent to the SDRAM every time the lower n bits of the address counter become 0 during the burst transfer, so that the same result is obtained at the same timing as in the full page mode. There is an effect that reading can be performed.

According to the fourth aspect of the present invention, when using the SDRAM having 256, 512, and 1024 columns, respectively, the value excluding the lower 8 bits of the address counter is set to 2, 1 , 0 bits are shifted upward to generate the row address.
There is an effect that any of the SDRAM devices in 56 columns, 512 columns, and 1024 columns can be used.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an SDRAM controller according to an embodiment.

FIG. 2 is a configuration diagram of a command generation unit 108.

FIG. 3 is a configuration diagram of a refresh generation unit 109;

FIG. 4 shows an address generator 110 according to the first embodiment.
FIG.

FIG. 5 is a timing chart of a command generator and an address generator.

FIG. 6 is a timing chart of a refresh generation unit.

FIG. 7 is a timing chart of jump and end during a line feed.

FIG. 8 shows an address generator 110 according to the second embodiment.
FIG.

FIG. 9 is a timing chart according to the second embodiment.

FIG. 10 shows an address generator 11 according to the third embodiment.
FIG.

FIG. 11 is a timing chart in the third embodiment.

FIG. 12 shows an address generator 11 according to a fourth embodiment.
FIG.

FIG. 13 is a timing chart in the fourth embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Input terminal 103 Data bus 104 SDRAM 105 Data processing device 106 Output terminal 107 SDRAM controller 108 Command generation part 109 Refresh generation part 110 Address generation part

Claims (4)

[Claims] 1. A data processing device and a clock synchronous SD
A memory control device for controlling a burst transfer with a RAM, wherein an address specified by the data processing device is used as an initial value, and a row address, a column address and a line feed request of the SDRAM are determined by using an address counter counting during the burst transfer. An address generating means for generating a signal; and generating a timing signal of a plurality of SDRAM commands for executing start processing, jump processing, end processing, and line feed processing in accordance with a request from the data processing device or the address generating means. And during the line feed processing,
When the jump processing request or the termination processing request is received, a command generating means for suspending the jump processing or the termination processing request until the line feed processing is terminated, and a timing signal of a refresh command according to a periodic request. And a refresh generation means for suspending the refresh request until any of the start processing, the jump processing, the line feed processing, and the end processing is executed when the refresh request is generated during the burst transfer. A memory control device comprising: 2. The address counter is divided into a lower half of the counter including at least the column address and an upper half of the remaining counter, and the lower half of the counter is one clock ahead of the upper half of the counter. 2. The memory control device according to claim 1, wherein the memory control device counts the data. 3. When the SDRAM is used in a mode having a burst length of N (where N is 2 to the power of n), each time the lower n bits of the address counter become 0 during the burst transfer, the column is read out. 3. The memory control device according to claim 2, wherein an address is sent to said SDRAM. 4. When the SDRAM having 256, 512, and 1024 columns is used, the value of the address counter excluding the lower 8 bits is shifted upward by 2, 1, 0 bits, respectively, and 3. The memory control device according to claim 2, wherein the address is generated.