JP2000298628A - Method for expanding logic card and common bus system using the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid a situation where a device is made down due to a fault of a cord undergoing live wire insertion. SOLUTION: A logic card 11 undergoing live wire insertion is tested before being incorporated in a common bus 7, and only when it is confirmed as normal, control for incorporating an inserted logic card in a bus is performed. A card extension control circuit 5 secures the safety of normal logic by performing control that makes a normal request wait while the card is tested, depreciates all checkers around a bus whose faulty section is defined as a critical heavy fault into an uncritical light fault with this as a condition and relieves a situation in which a device gets down due to a fault of the inserted logic card. Also, the fault existing during the test and a test abnormal end are notified to a diagnostic processor as a light fault.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for adding logical cards and a common bus system using the method.

[0002]

2. Description of the Related Art From the viewpoint of mounting information devices such as computers, a common bus structure in which a plurality of logic cards (hardware) for controlling input / output devices are commonly connected to bus lines on a back panel via connectors. Is often used. In the information equipment described above, if a failure or abnormality occurs during the operation of the equipment, the operation for inserting or removing the logical card such as removing or inserting the logical card at the failed part from the back panel in the process of recovery from the failure is required. Done. This is called hot-swapping.In this case, noise etc. may occur, which may adversely affect the normal logical card or the device itself during operation that is not related to insertion and removal.
Conventionally, various proposals have been made to prevent this.

[0003]

For example, Japanese Patent Application Laid-Open No.
An example is shown in 31033. According to this publication, a hot-inserted logic card is controlled so as not to adversely affect an operating electronic circuit by executing a reset, but the logic card is tested without being tested after the reset. Built into the bus. This means that a logical card that has been hot-plugged will only be reset and process normal jobs, and if the inserted logical card has failed, a fatal error will occur during the job execution. there's a possibility that.

The present invention has been made in order to solve the above-mentioned problems, and a test is performed on a logical card with a hot-plug inserted before it is incorporated into a bus, and only when it is confirmed that the logical card is normal. The control of incorporating the inserted logical card into the bus is performed, and during the test of the card, the safety of the normal logic is ensured by controlling the normal request to wait.
Under this condition, all checkers around the bus where the failure classification is fatal serious failure are downgraded to non-fatal minor failures, and the situation where the equipment goes down due to the failure of the inserted logic card is rescued. It is an object of the present invention to provide an extension method and a common bus system using the method. Also,
The faults that occurred during the test and the abnormal termination of the test are reported to the diagnostic processor as minor faults, so that the operator can recognize them.All the above controls are realized by hardware, and the work of adding cards can be completed quickly. It is another object of the present invention to provide a method of adding a logical card capable of reducing the operation burden on maintenance personnel and reducing operation errors, and a common bus system using the method.

[0005]

According to a first aspect of the present invention, there is provided a method for adding a logical card, comprising: connecting a plurality of logical cards including a logical card serving as a bus master to a bus line on a back panel; In a common bus system commonly connected via a bus, the logical card serving as the bus master detects that a new logical card is connected to the common bus while the system is operating,
A bus request issued by another logical card including itself is made to wait, and the logical card is tested and confirmed to be normal, and the card is incorporated into the common bus. According to a second aspect of the present invention, in the method of adding a logical card according to the first aspect, a fault occurring during the test and an abnormal termination by the test are externally connected as non-fatal faults. And notifying the diagnostic processor.

According to a third aspect of the present invention, there is provided a common bus system in which a plurality of logical cards including a logical card serving as a bus master are commonly connected to a bus line on a back panel via a connector. The new logical card detects that the new logical card has been connected to the common bus, performs a test, and notifies the bus control circuit and the card expansion control circuit of another logical card that the test is being performed. When the test is completed normally, the card valid flag of its own and the card valid flag of another logical card are set and the logical card is taken into the common bus system. When a failure occurs, a card addition control circuit that notifies the error detection circuit of the logic card as a failure to its own error detection circuit; Perform read write test data in accordance with an instruction de additional control circuit, normal or by its content comparison
A bus control circuit having a test data register for determining an abnormality and controlling not to output a bus request generated during the test to the common bus; a failure occurring during the test and abnormal termination by the test; An error detection circuit that notifies a diagnostic processor externally connected as a non-fatal fault, receives information unique to each logical card via the common bus, and refers to the valid flag of each logical card to refer to the bus. And a bus master determining circuit for determining a logical card to be a bus master in accordance with a predetermined rule for determining a bus master among the logical cards incorporated in the system.

In the above-described configuration, a test is performed on a logical card having a live line inserted therein before being incorporated into the bus, and only when it is confirmed that the logical card is normal, control is performed to incorporate the inserted logical card into the bus. During the test of the card, the normal logic is secured by controlling the normal request to wait, and under this condition, all the checkers around the bus whose fault classification is fatal and severe are all non-fatal It is downgraded to a failure to remedy the situation where the equipment goes down due to the failure of the inserted logic card. In addition, a fault that occurred during the test and an abnormal termination of the test are reported as minor faults to the diagnostic processor so that the operator can recognize the fault. By implementing all of the above-mentioned control by hardware, the operation of adding a card can be completed quickly, so that the operation burden on maintenance personnel can be reduced and operation errors can be reduced.

[0008]

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, reference numerals 1 and 11 denote logic cards in which electronic circuits are incorporated, which are commonly connected via a back panel 7. Hereinafter, the logical cards 1 and 11 are referred to as a card A and a card B, respectively. The card (A) 1 includes a bus control circuit 2, a card valid flag 3, a bus master determination circuit 4, a card expansion control circuit 5, and an error control circuit 6. The bus control unit 2 has a card valid signal (line 105) generated by the card valid flag 3 and a test instruction signal (line 1) generated by the card expansion control circuit 5.
02) is input and the read data signal (line 103)
Is output to the card addition control circuit 5, and bus protocol control, such as bus contention and release, not directly related to the present invention, is performed with the back panel 7 described later. A card built-in signal (line 104) is input to the card validity flag 3 from the card addition control circuit 5, where a card validity signal is generated and output to the bus control circuit 2 and the bus master determination circuit 4 via the line 105. . The bus master determination circuit 4 receives the card valid signal (line 105), obtains a card number as a fixed value from each card via the back panel 7, generates a bus master signal, and generates the bus master signal via the line 107. It is output to the card extension control circuit 5. The card addition control circuit 5 includes a bus master signal (line 107) and a read data signal (line 103)
To generate a test command signal (line 102), an error signal (line 106), and a card built-in signal (line 104), and supply them to the bus control circuit 2, the error control circuit 6, and the card valid flag 3, respectively. . The error control circuit 6 receives an error signal (line 106) generated by the card addition control circuit 5, and has a reporting path to a diagnostic processor (not shown). The card (B) 11 also has the same configuration as the card (A) 1,
It includes a card valid flag 13, a bus master determination circuit 14, a card expansion control circuit 15, and an error control circuit 16. The functions and connection relations of each block are the same as those of the card (A) 1, and the description is omitted to avoid duplication.

Next, the connection relationship via the back panel 7 will be described. The bus signal propagating through the common bus (line 111) is a bidirectional signal, and the bus control circuits 2 and 1
2 is connected. The extension control signal (line 101) is also a bidirectional signal, and includes bus control circuits 2 and 12, card extension control circuits 5 and 15, and error control circuits 6 and 16.
Connected to. The bus stop signal (line 110) is input to the bus control circuits 2 and 12. The card A mounting signal (line 108) is supplied from the card (A) 1 to the card addition control circuits 5 and 15 by fixedly outputting a "1" level signal. The card B mounting signal (line 109) is supplied to the card expansion control circuits 5 and 15 by fixedly outputting a "1" level signal from the card (B) 11.

Hereinafter, the operation of the embodiment of the present invention will be described in detail. It is assumed that the card (A) 1 is already mounted on the device and is operating by being incorporated in the bus, and the card (B) 11 is newly added. Prior to the description of the operation, it is necessary to determine a card (referred to as a bus master) that mainly performs the extension control according to the embodiment of the present invention. Here, a plan is adopted in which the card having the lowest number among the cards currently incorporated in the common bus 111 is determined as the bus master. Therefore, card valid flags 3 and 13 for displaying cards incorporated in the common bus 111 are provided,
The card number is notified to each card via the back panel 7, and the bus master determining circuits 4 and 14 determine the bus master. In the embodiment of the present invention, the card (B) 11
Since the card (A) 1 is the younger one, and the card incorporated in the common bus 111 is only the card (A) 1 under the above assumption, the bus master is the card (A) 1. Yes, in the following description, it is assumed to be unchanged.

First, the card (B) 11 is newly inserted into the back panel 7 and the card (B) 11 is connected to the common bus 111. First, when the bus stop signal (line 110) becomes "1" (active), the bus stops. During this time, each signal pin of the card (B) 11 is connected to the back panel 7, and immediately thereafter, the card (B) 11 performs initialization (reset) by itself. The card addition control circuit 5 recognizes that the card (B) 11 has been added by the change of the card B mounting signal (line 109) from “0” to “1”, and determines that the card is the bus master. Under the conditions, the test of the card (B) 11 is started, and this is notified to the bus control circuits 2 and 12, the error control circuits 6 and 16, and the expansion control circuits 5 and 15 by the additional control signal (line 101). The extension control signal (line 101)
Is a bidirectional signal line, and the card for driving this is negotiated with the bus master.

During testing, the bus control circuits 2 and 12 keep normal instructions out of the bus, and the error control circuits 6 and 16 downgrade all fault categories to minor faults. Here, the timing for returning the bus stop signal (line 110) to "0" is set after the control for not issuing the normal instruction to the common bus 111 is performed. In this state, the card addition control circuit 5 sets the card (B)
The test for the card 11 is performed. First, a test write command for the card (B) 11 is output to the bus control unit 2, whereby the bus control circuit 12 receives the bus write signal (line 111). The data is stored in a built-in test register, and then the card expansion control circuit 5 reads out the content stored in the test register by a test read command, and compares it with the data at the time of the test write. Note that the test write instruction and the test read instruction are dedicated to the test.

When the test is completed normally, the card addition control circuit 5 sends a notification of the test completion and an instruction to install the bus to all the cards to the addition control signal 101. Here, if the data comparisons do not match, or if a failure occurs during the test, no bus installation instruction is issued as an end notification only. If there is a bus installation instruction, the card expansion control circuits 5 and 1
5 sets the value of the card A mounting signal 108 and the value of the card B mounting signal 109 ("1" when the card is inserted into the back panel 7) to the card valid flags 3 and 13 to set the card (A). 1 and the card (B) 11 are incorporated into the bus. In response to the test termination instruction, the bus control circuits 2 and 12 start outputting normal instructions to the common bus 111, and the common bus 111 returns to normal operation.

As described above, according to the present invention, the card (A) 1 and the card (B) 11 shown in the embodiment have the same function and configuration, and are inserted into the back panel 7 to perform bus operation. Assumed to be performed. The card (A) 1 has already been inserted into the back panel 7 and connected to the common bus 111, and is in charge of the bus master. Therefore, when the card (B) 11 is newly inserted, the card addition control circuit 5 Indicates that the card B mounting signal (line 109) is "0"
Card (B) 11 by detecting the change from "1" to "1".
Is started and the extension control signal (line 101) notifies the bus control circuits 2 and 12, the error control circuits 6 and 16, and the card extension control circuit 15 that the test is being performed. During the test, the bus control circuits 2 and 12 hold normal instructions so as not to output them to the bus, and
And 16 downgrade all fault categories to minor faults.
When the card addition control circuit 5 issues a test write command to the card (B) 11 to the test command 102, the bus control circuit 2 sends the test data of the bus control circuit 12 via the bus signal (line 111). After the data is stored in the register, the card addition control circuit 5 issues a test read command to the same route to read the data from the register, and compares the read data with the data at the time of the test write. Subsequently, the card addition control circuit 5 notifies the end of the test by an addition control signal (line 101). If the data comparison does not match or a failure occurs during the test, the card (B) 11 is reset. This signal is used to notify the diagnosis processor that the test has been abnormally terminated and that the test has ended abnormally, and to report a minor fault to the diagnostic processor via the error control circuit 6.

When the test is normally completed, the card addition control circuits 5 and 15 send the card A mounting signal (line 108) and the value of the card B mounting signal (line 109) to the card valid flags 3 and 13 (when the card is on the back panel). When the card is inserted into the card 7, "1") is set, and both cards are incorporated in the bus. The bus master determining circuits 4 and 14 are an example for determining a bus master. The bus master determining circuits 4 and 14 receive the individual number of each card from the back panel 7 and refer to the card valid flags 3 and 13 among the cards incorporated in the bus. The youngest one is decided as the bus master. As a result, it is possible to avoid a situation in which the equipment is down due to the failure of the card that is hot-plugged.

[0016]

As described above, according to the present invention, a test is performed on a hot-inserted logical card before assembling it into a bus, and only when it is confirmed that the logical card is normal, the logical card is inserted. Is incorporated into the bus. During the test of the card, the normal logic is secured by controlling the normal request to wait, and under this condition, all the checkers around the bus whose fault classification is fatal and severe are all non-fatal By downgrading to a failure, it is possible to relieve a situation where the equipment goes down due to a failure of the inserted logic card.
In addition, by reporting a fault during the test and an abnormal termination of the test as a minor fault to the diagnostic processor, the operator can recognize the fault. All of the above-described control is realized by hardware, whereby the work of adding a card can be performed quickly, and the operation burden on maintenance personnel can be reduced and operation errors can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 (11) Card A (B) 2 (12) Bus control circuit 3 (13) Card valid flag 4 (14) Bus master determination circuit 5 (15) Card expansion control circuit 6 (16) Error control Circuit 7: Back panel 111: Common bus

Claims (3)

[Claims] 1. In a common bus system in which a plurality of logical cards including a logical card serving as a bus master are commonly connected to a bus line on a back panel via a connector, the logical card serving as a bus master is provided during operation of the system.
By detecting that a new logical card has been connected to the common bus, a bus request issued by another logical card including itself is waited, and the logical card is tested and confirmed to be normal. A method of adding a logical card, wherein the card is incorporated into a common bus only when the logical card is used. 2. The method according to claim 1, wherein a failure occurring during the test and an abnormal termination by the test are notified to a diagnostic processor externally connected as a non-fatal failure. 3. A common bus system in which a plurality of logical cards including a logical card serving as a bus master are commonly connected to a bus line on a back panel via a connector, wherein the logical card serving as a bus master is a new logical card. The test is performed by detecting that the card is connected to the common bus, and the fact that the test is being performed is notified to its own bus control circuit and the card addition control circuit of another logical card. When the processing is completed, the own card valid flag and the card valid flag of another logical card are set, the logical card is taken into the common bus system, the processing is abnormally terminated, and when a failure occurs during the test,
A card extension control circuit for notifying the error detection circuit of the logic card as a defect to its own error detection circuit; and test data for reading and writing test data in accordance with instructions from the card extension control circuit, and comparing the contents to determine normal / abnormal. A bus control circuit having a register and controlling not to output a bus request generated during the test to the common bus, and externally connecting a fault occurring during the test and an abnormal termination by the test as a non-fatal fault An error detection circuit for notifying a diagnosis processor to be executed, and a logic card received in the bus system by receiving information unique to each logic card via the common bus and referring to a valid flag of each logic card Out of the buses that determine the logical card to be the bus master in accordance with the predetermined rules for determining the bus master. A common bus system, comprising a master decision circuit.