JP2000298655A - Information processor and bus system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor which allows a user to easily construct an appropriate bus system, to secure needed bus bandwidth and to perform normal data transfer. SOLUTION: An interconnection state acquiring means 1111 acquires the interconnection state of plural information processors constituting a bus system, and a topology grasping means 1112 analyzes the interconnection state and grasps the topology of the bus system. The number of maximum interconnections calculating means 1113 calculates the number of maximum interconnections being the maximum value among the numbers of interconnections in each communication path respectively of the bus system on the basis of the topology of the bus system. An information processor specifying means 1114 specifies an information processor to which a new information processor can be interconnected and also where the number of maximum interconnections is not increased when the new information processor is interconnected among the plural information processors on the basis of the interconnection state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to any one of a plurality of information processing apparatuses which are interconnected via an interconnecting means via a bus to form a bus system and communicate with each other. It relates to a bus system.

[0002]

2. Description of the Related Art Generally, information processing apparatuses such as a personal computer, a printer, and a scanner are interconnected via a bus to form a bus system. In this bus system, a plurality of information processing apparatuses communicate with each other. An IEEE 1394 serial bus is known as such a bus. When configuring a bus system using an IEEE 1394 serial bus, loops must not be included in the topology of the bus system, the total number of information processing devices connected to the bus must be 63 or less, and And the number of interconnections (hereinafter also referred to as “hop number”) in a communication path from one information processing apparatus to another information processing apparatus must be 16 or less. It is necessary. Then, the information processing apparatuses can be freely interconnected while observing these rules.

[0003] Therefore, it is important for the user to grasp the state of the bus system using the IEEE 1394 serial bus. For example, Japanese Patent Application Laid-Open No. 9-331342
In this publication, a bus status management device for notifying a user of the status of the IEEE 1394 bus system is disclosed. With this bus state management device, the user can use IEEE 1394.
The topology of the bus system can be easily grasped.

[0004]

As the maximum number of hops of the IEEE 1394 bus system increases, the bus bandwidth available for communication, that is, data transfer, decreases. Therefore, when a new information processing device is interconnected to the IEEE 1394 bus system, the
In some cases, the maximum value of the number of hops of the E1394 bus system becomes large, so that a necessary bus bandwidth cannot be secured and normal data transfer cannot be performed.

[0005] In order to avoid the above-mentioned inconvenience, the user must interconnect information processing apparatuses or change the topology after understanding the IEEE 1394 standard. However, it is difficult for a user to understand the IEEE 1394 standard. It is also difficult for a user to always grasp the topology of the IEEE 1394 bus system.

By using the bus state management device disclosed in the above publication, the user can grasp the topology of the IEEE 1394 bus system. However, it is determined whether or not the topology is appropriate, whether or not there is a problem when a new information processing device is interconnected to the IEEE 1394 bus system, and which information processing device in the IEEE 1394 bus system is used. It is up to the user to determine whether or not a new information processing device should be interconnected.
These determinations are indispensable for securing a necessary bus bandwidth and performing normal data transfer, but are difficult for the user. Therefore, if the user has the appropriate IE
It is difficult to construct an EE1394 bus system.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and enables a user to easily construct an appropriate bus system, secure a necessary bus bandwidth, and perform normal data transfer. An object of the present invention is to provide an information processing apparatus that can perform the above-described processing and a bus system including the information processing apparatus.

[0008]

A first information processing apparatus according to the present invention comprises a plurality of information processing apparatuses which are interconnected via an interconnecting means via a bus to form a bus system and communicate with each other. Any of the information processing devices,
(1) an interconnect status acquisition means for acquiring the interconnect status of the interconnect means of each of the plurality of information processing devices; and (2) a bus system by analyzing the interconnect status acquired by the interconnect status acquisition means. (3) the maximum number of interconnections, which is the maximum value among the number of interconnections in each communication path of the bus system, based on the topology of the bus system identified by the topology identification means. Means for calculating the maximum number of interconnects to obtain, (4) among the plurality of information processing devices, it is possible to interconnect a new information processing device and when the new information processing device is interconnected The one that does not increase the maximum number of interconnections calculated by the maximum number of interconnections calculation means is specified based on the interconnection state acquired by the interconnection state acquisition means. And an information processing device specifying unit.

According to the first information processing apparatus of the present invention, the interconnection state of the interconnection means of each of the plurality of information processing apparatuses constituting the bus system is acquired by the interconnection state acquisition means, and the topology is grasped. By means,
The acquired interconnection state is analyzed to grasp the topology of the bus system. The maximum number of interconnections, which is the maximum value among the number of interconnections in each communication path of the bus system, is obtained by the maximum number of interconnections calculating means based on the grasped topology of the bus system. Then, the information processing device identifying means can interconnect a new information processing device among the plurality of information processing devices, and when the new information processing device is interconnected, the maximum number of interconnections Those for which the maximum number of interconnects obtained by the calculating means does not increase are specified based on the interconnect state acquired by the interconnect state acquiring means.

The first information processing apparatus according to the present invention is further characterized by further comprising an information processing apparatus information notifying means for notifying a user of the information processing apparatus specified by the information processing apparatus specifying means. Further, the first information processing apparatus according to the present invention is characterized by further comprising an information processing apparatus information transmitting means for transmitting the information processing apparatus specified by the information processing apparatus specifying means to another information processing apparatus. In these cases, the user who is notified of the information processing device specified by the information processing device specifying means can easily construct an appropriate bus system, secure a necessary bus bandwidth, and perform normal data transfer. It can be performed.

A second information processing apparatus according to the present invention is any one of a plurality of information processing apparatuses interconnected via a bus by an interconnecting means to constitute a bus system and communicate with each other. And (1) an interconnection status acquisition unit for acquiring an interconnection status of the interconnection unit of each of the plurality of information processing devices, and (2) analyzing an interconnection status acquired by the interconnection status acquisition unit. Topology grasping means for grasping the topology of the bus system by
(3) a maximum number of interconnections calculating means for obtaining a maximum number of interconnections which is a maximum value among the number of interconnections in each communication path of the bus system based on the topology of the bus system grasped by the topology grasping means; (4) An improved topology grasping means for analyzing the interconnect state acquired by the interconnect state acquiring means and finding a new topology in which the maximum interconnect number calculated by the maximum interconnect number calculating means is reduced. It is characterized by.

According to the second information processing apparatus according to the present invention, the interconnection state of the interconnection means of each of the plurality of information processing apparatuses constituting the bus system is acquired by the interconnection state acquisition means, and the topology is grasped. By means,
The acquired interconnection state is analyzed to grasp the topology of the bus system. The maximum number of interconnections, which is the maximum value among the number of interconnections in each communication path of the bus system, is obtained by the maximum number of interconnections calculating means based on the grasped topology of the bus system. Then, the improved topology grasping means analyzes the interconnect state acquired by the interconnect state acquiring means, and finds a new topology in which the maximum interconnect number obtained by the maximum interconnect number calculating means decreases.

Further, the second information processing apparatus according to the present invention is characterized by further comprising an improved topology information notifying means for notifying a user of a new topology obtained by the improved topology grasping means. Further, the second information processing apparatus according to the present invention is further characterized by further comprising an improved topology information transmitting means for transmitting a new topology obtained by the improved topology grasping means to another information processing apparatus. In these cases, the user who is notified of the new topology obtained by the improved topology grasping means can easily construct an appropriate bus system, secure a necessary bus bandwidth, and perform normal data transfer. It can be carried out.

A third information processing apparatus according to the present invention is any one of a plurality of information processing apparatuses which are interconnected via an interconnecting means via a bus to form a bus system and communicate with each other. And (1) an interconnection status acquisition unit for acquiring an interconnection status of the interconnection unit of each of the plurality of information processing devices, and (2) analyzing an interconnection status acquired by the interconnection status acquisition unit. Topology grasping means for grasping the topology of the bus system by
(3) a bus bandwidth insufficiency determining means for determining whether or not a bus bandwidth required for communication by each of the plurality of information processing devices is insufficient; and (4) a bus bandwidth by the bus bandwidth insufficiency determining means. When it is determined that the width is not insufficient, the topology storage means for storing the topology of the bus system grasped by the topology grasping means, and (5) based on the topology of the bus system grasped by the topology grasping means, An additional information processing device interconnection detecting means for detecting that a new information processing device has been added to the bus system and being interconnected; and (6) a new information processing device having been added to the bus system by the additional information processing device interconnection detecting means. Is added to the topology, and the topology grasped by the topology grasping means and the topology stored by the topology storage means are detected. And an additional information processing device specifying unit that specifies the new added information processing device by comparing with the information processing device.

According to the third information processing apparatus of the present invention, the interconnection state of the interconnection means of each of the plurality of information processing apparatuses constituting the bus system is acquired by the interconnection state acquisition means, and the topology is grasped. By means,
The acquired interconnection state is analyzed to grasp the topology of the bus system. The bus bandwidth insufficiency determining means determines whether or not the bus bandwidth required for each of the plurality of information processing devices for communication is insufficient. When the bus bandwidth insufficiency determining means determines that the bus bandwidth is not insufficient, the topology of the bus system grasped by the topology grasping means is stored by the topology storage means. On the other hand, the additional information processing device interconnection detecting means detects that a new information processing apparatus has been added to the bus system and interconnected based on the bus system topology grasped by the topology grasping means. Then, when the additional information processing device interconnection detecting means detects that a new information processing device has been added to the bus system and has been interconnected, the additional information processing device identifying means has grasped by the topology grasping means. The topology is compared with the topology stored by the topology storage means, and the new information processing apparatus added is specified.

In the third information processing apparatus according to the present invention, the new information processing apparatus specified by the additional information processing apparatus specifying means when the bus bandwidth shortage determining means determines that the bus bandwidth is insufficient. The information processing apparatus further includes an additional information processing apparatus information notifying unit that notifies a user of the information processing apparatus. The third information processing apparatus according to the present invention includes a new information processing apparatus specified by the additional information processing apparatus specifying means when the bus bandwidth shortage determining means determines that the bus bandwidth is insufficient. It is characterized by further comprising additional information processing device information transmitting means for transmitting to the information processing device. In these cases, the user who has been notified of the new information processing device specified by the additional information processing device specifying means when the bus bandwidth shortage determining means has determined that the bus bandwidth is insufficient is to be given an appropriate A bus system can be easily constructed, a necessary bus bandwidth can be secured, and normal data transfer can be performed.

Further, the third information processing device according to the present invention provides a new information processing device specified by the additional information processing device specifying means when the bus bandwidth shortage determining means determines that the bus bandwidth is insufficient. The information processing apparatus further includes an additional information processing apparatus disconnecting unit that disconnects the information processing apparatus from the bus system. In this case, when the bus bandwidth shortage determining unit determines that the bus bandwidth is insufficient, the new information processing device identified by the additional information processing device identifying unit is output by the additional information processing device disconnecting unit. Disconnected from the bus system. Therefore, in this case, an appropriate bus system can always be constructed,
The required bus bandwidth can be secured and normal data transfer can be performed.

Further, the third information processing apparatus according to the present invention provides: (1) a bus bandwidth required for each of the plurality of information processing apparatuses for communication, and a total of the acquired bus bandwidths; A required bus bandwidth calculating means for calculating the required bus bandwidth, and (2) a required bus bandwidth securing means for securing the required bus bandwidth calculated by the required bus bandwidth calculating means, further comprising: 3) The bus bandwidth shortage determination means determines that the bus bandwidth is insufficient when the required bus bandwidth securing means cannot secure the required bus bandwidth. Is preferred.

Further, a third information processing apparatus according to the present invention is characterized in that the topology storage means is rewritable. In this case, the storage of the topology of the bus system can be updated. Further, a third information processing apparatus according to the present invention is characterized in that the topology storage means is nonvolatile. In this case, the storage of the topology of the bus system is retained even when the power is turned off.

Each of the first to third information processing apparatuses according to the present invention is characterized in that the bus is an IEEE 1394 serial bus. In this case, a plurality of information processing apparatuses including any of the above-described first to third information processing apparatuses according to the present invention are interconnected via an IEEE 1394 serial bus to form a bus system. And communicate with each other.

A bus system according to the present invention is a bus system in which a plurality of information processing devices are interconnected via an interconnecting means via a bus and communicate with each other. Is the first type according to the present invention.
To any one of the third information processing apparatus. According to this bus system, a plurality of information processing apparatuses including any one of the above-described first to third information processing apparatuses according to the present invention are interconnected via a bus to constitute a bus system. In this bus system, a plurality of information processing devices communicate with each other.

[0022]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description.

(First Embodiment) First, a first embodiment of an information processing apparatus and a bus system according to the present invention will be described. FIG. 1 is a block diagram illustrating a schematic configuration of the bus system according to the first embodiment. Hereinafter, the information processing device may be referred to as a “node”.

In the bus system according to the present embodiment, a plurality of nodes 100 and 200a to 200h
IEEE 13 is interconnected via a 94 serial bus.
A 94 bus system 1 is configured. The node 200a has a port P1 as an interconnecting means. Node 2
00b has a port P2 as an interconnection means.
Node 200c is connected to ports P3-P6
have. Node 200d has ports P7 and P8 as interconnection means. The node 200e has ports P9 to P11 as interconnecting means. The node 200f has ports P12 to P1 as interconnecting means.
Four. The node 200g has a port P17 as an interconnection means. Node 200h has ports P18 and P19 as interconnection means. Node 100 has ports P15 and P15 as interconnecting means.
16.

The port P1 of the node 200a, the port P3 of the node 200c, the port P2 of the node 200a, the port P4 of the node 200c, and the node 20
0c port P5 and node 200d port P7,
Port P8 of node 200d and port P9 of node 200e, port P10 of node 200e and port P12 of node 200f, port P1 of node 200e
1 and port P15 of node 100, node 200f
Port P13 of the node and port P17 of the node 200g,
And the port P14 of the node 200f and the node 2
00h ports P18 are interconnected via an IEEE 1394 serial bus. On the other hand, the port P6 of the node 200c and the port P19 of the node 200h
And the port P16 of the node 100 are not connected.

The plurality of nodes 100 and 200a
A node identification number (node ID) is assigned to each of ~ 200h by a bus configuration at the time of initialization of the IEEE 1394 bus system 1. Here, the node ID of the node 200a is set to 0,
The node ID of the node 200b is set to 1 and the node 200c
The node ID of the node 200d is 2, the node ID of the node 200e is 8, the node ID of the node 200f is 6, the node ID of the node 200g is 4, and the node ID of the node 200h is 5. And the node ID of the node 100 is 7.

FIG. 2 is a block diagram showing a schematic configuration of the information processing apparatus 100 according to the first embodiment. The information processing device (node) 100 according to the present embodiment includes a CPU 11
0, RAM 120, ROM 130, IEEE 1394 interface unit 140, output unit 150, internal bus 16
0 and ports P15 and P16 which are interconnecting means.

The CPU 110 is a central processing unit that controls the whole of the node 100.
The instruction is executed according to the program stored in the OM 130. The RAM 120 is used as a work memory when the CPU 110 controls the node 100.
It is also used as a buffer memory for storing data transmitted and received between the other nodes 200a to 200h via the EE1394 interface unit 140. ROM1
Reference numeral 30 stores a program executed by the CPU 110 and node-specific information. The IEEE 1394 interface unit 140 is used for the IEEE 1394 serial bus 30.
0 controls data transmission and reception. The output unit 150 provides various information to the user through characters and images. The internal bus 160 includes a CPU 110, a RAM 120, a ROM 13,
0, the IEEE 1394 interface unit 140 and the output unit 150 are mutually connected.

FIG. 3 is a diagram showing functional blocks in the CPU 110 of the information processing apparatus 100 according to the first embodiment. Information processing device (node) 10 according to the present embodiment
0 of the CPU 110
Topology grasping means 1112, maximum interconnection number calculating means 1
113, an information processing device specifying unit 1114, an information processing device information notifying unit 1115, and an information processing device information transmitting unit 1116.

The interconnection state acquisition means 1111 stores the interconnection state of each port of each of the nodes 100 and 200a to 200h, that is, the topology map, in the IEEE.
In the E1394 bus system 1, it is obtained from a node called a bus manager via the IEEE1394 interface unit 140. Then, the topology grasping means 1
Reference numeral 112 analyzes the topology map acquired by the interconnection state acquiring unit 1111 to grasp the topology of the IEEE 1394 bus system 1. Based on the topology of the IEEE 1394 bus system 1 grasped by the topology grasping means 1112, the maximum number of interconnects calculating means 1113 calculates the maximum value among the number of interconnects (the number of hops) in each communication path of the IEEE 1394 bus system 1. A certain maximum number of interconnections (maximum number of hops) is obtained.

The information processing device specifying means 1114 is capable of interconnecting a new information processing device among the nodes 100 and 200a to 200h, and has a maximum value when the new information processing device is interconnected. The one that does not increase the maximum hop number calculated by the number-of-interconnects calculation unit 1113 is specified based on the topology map acquired by the interconnection state acquisition unit 1111. The information processing device information notifying unit 1115 notifies the user of the node specified by the information processing device specifying unit 1114 by using the output unit 150. The information processing device information transmitting unit 1116 transmits the node specified by the information processing device specifying unit 1114 to any of the other nodes 200a to 200h via the IEEE 1394 interface unit 140.

The information processing apparatus 10 according to the present embodiment
0 does not necessarily need to include both the information processing device information notifying unit 1115 and the information processing device information transmitting unit 1116, and may be one of them. For example, when the information processing apparatus 100 includes the display unit 150, the information processing apparatus information transmitting unit 1116 does not need to be included. If the node specified by the information processing apparatus information notifying unit 1115 is displayed on the display unit 150, Good. When the information processing apparatus 100 does not include the display unit 150, the information processing apparatus information transmission unit 1116 does not include the information processing apparatus information notification unit 1115. To be displayed on the other node.

FIGS. 4 and 5 are flowcharts for explaining the operation of the information processing apparatus 100 according to the first embodiment. The operation described below is based on the RAM 120, IEEE
1394 interface section 140 and output section 150
Is performed by the CPU 110 in accordance with the program stored in the ROM 130.

In step S 1, the interconnection status acquisition unit 1111 of the CPU 110 determines whether the nodes 100 and 20
A node ID for identifying each of the nodes 0a to 200h, and an interconnection state, that is, a topology map including information such as a state of a port in each of the nodes 100 and 200a to 200h. To get through. Step S2
Then, the topology grasping unit 1112 analyzes the topology map acquired by the interconnection state acquiring unit 1111 and grasps the entire topology of the IEEE 1394 bus system 1.

In steps S3 to S7, the maximum number-of-interconnects calculation means 1113 determines the hops in each communication path of the IEEE1394 bus system 1 based on the topology of the IEEE1394 bus system 1 grasped by the topology grasping means 1112 in step S2. The maximum hop number which is the maximum value of the numbers is obtained.

More specifically, in step S3, the value of the variable i indicating the node ID is initialized to 0, and the
The maximum value of the number of hops in the 394 bus system 1, that is, the value of a variable MaxHop1 that stores the maximum number of hops is initialized to 0. In step S4, the number of hops from the node whose node ID is the value of the variable i (hereinafter, referred to as “node i”) to each of all other nodes is determined, and the maximum value of the hop numbers is set to the variable Hop1. Stored as the value of [i]. Then, in step S5, the larger value of each of the variables MaxHop1 and Hop1 [i] is set to the variable MaxHop.
Newly stored in p1. In step S6, the value of the node ID variable i is compared with the number of nodes to determine whether or not the processing in steps S4 and S5 has been performed for all nodes. If processing is not performed for all nodes,
In step S7, the value of the variable i is incremented, and the processes in steps S4 and S5 are repeated. If the processing has been performed for all nodes, the processing from step S8 is performed. At the start of the process in step S8, the variable MaxH
op1 stores the maximum number of hops in the IEEE 1394 bus system 1.

In steps S8 to S13, the information processing device specifying means 1114 determines whether the nodes 100 and 200a-2
00h, it is possible to interconnect a new information processing device, and when the new information processing device is interconnected, the maximum hop calculated by the maximum interconnection number calculating means 1113 in steps S3 to S7. Those whose number does not increase are specified based on the topology map acquired by the interconnection state acquiring means 1111 in step S1. And information processing device information notifying means 1
Reference numeral 115 notifies the user of the information processing device specified by the information processing device specifying unit 1114 using the output unit 150. Further, the information processing device information transmitting unit 1116 includes:
The information processing device specified by the information processing device specifying unit 1114 is transferred to the IEEE 1394 interface unit 140.
To any of the other nodes 200a to 200h.

More specifically, in step S8, the value of the variable i indicating the node ID is initialized to 0 again. In step S9, the values of the variable MaxHop1 and the variable Hop1 [i] are compared to determine whether the maximum hop number does not increase when a new node is connected to the node i.
When the value of the variable Hop1 [i] is smaller than the value of the variable MaxHop1, the process of step S10 is performed.

In step S10, it is determined whether or not an empty port exists in the node i, that is, whether or not a new node can be connected to the node i.
If there is a free port in the node i, step S11
Process. In step S11, the output unit 150 is used to notify the user of a node i in which the maximum hop number of the IEEE 1394 bus system 1 does not increase even if new nodes are interconnected. At this time, this node i is connected to IE
The information may be transmitted to any of the other nodes 200a to 200h via the EE1394 interface unit 140 and displayed on the other nodes.

In step S12, the value of the node ID variable i is compared with the number of nodes to determine whether or not the processing in steps S9 to S11 has been performed for all nodes. If the processing has not been performed on all the nodes, the value of the variable i is incremented in step S13, and steps S9 to S10
The process up to is repeated. When the processing has been performed for all the nodes, the processing ends.

FIG. 6 is a diagram showing an IEEE1 according to the first embodiment.
3 is a table showing a state of each information processing device (node) in the 394 bus system 1; In this chart, a field F1 indicates a node ID of the node. Field F2 indicates the node ID of a node interconnected to the node. Field F3 is a variable Hop1 of the node.
Indicates the value of [i]. A field F4 indicates the number of empty ports of the node. When the value of the field F4 is 0, the node has no empty port.

For example, the node 200c is the node 200
a, the node 200b and the node 200d are interconnected with each other.
The value of 2 is the node ID of these nodes, 0, 1,
It becomes 3. In addition, the hop count of the communication route starting from the node 200c has a maximum value of 4 when the end point of the communication route is the node 200g or the node 200h. Therefore, the value of the field F3 of the node 200c is 4.

From FIG. 6, Hop1 for each node i
Since the maximum value of [i] is 5, the value of the variable MaxHop1 storing the maximum number of hops is 5. Therefore, Hop1
[i] As a node with <5 and an empty port,
The node 200c and the node 100 are specified. That is, even if a new node is interconnected to the node 200c or the node 100, the IEEE 1394 bus system 1
Does not increase.

FIG. 7 is a view for explaining a display example on the display unit 150 of the information processing apparatus 100 according to the first embodiment. As shown in this figure, the information processing device (node) 1
00 is displayed on the IEEE 139 shown in FIG.
The connection configuration of each node in the 4-bus system 1 is displayed. In this display, each of the nodes 200c and 100 specified as nodes capable of interconnecting a new node and not increasing the maximum hop number when interconnected is different from the other nodes. It is displayed in a color and a different display mode (dot display in the figure), and is notified to the user.

As described above, according to the information processing apparatus and the bus system according to the present embodiment, a new information processing apparatus can be interconnected among a plurality of information processing apparatuses constituting the bus system. Further, it is possible to specify a bus system in which the maximum number of hops does not increase when interconnected. Therefore, the user who is notified of the specified information processing apparatus can easily construct an appropriate bus system, and can perform a normal data transfer while securing a necessary bus bandwidth.

(Second Embodiment) Next, an information processing apparatus and a bus system according to a second embodiment of the present invention will be described. The schematic configuration of the bus system according to the second embodiment is substantially the same as that described with reference to FIG. 1 in the first embodiment. The schematic configuration of the information processing apparatus according to the second embodiment is substantially the same as that described with reference to FIG. 2 in the first embodiment. However, the processing content of the CPU 110 of the information processing device (node) 100 according to the second embodiment is different from that of the first embodiment.

FIG. 8 is a diagram showing functional blocks in the CPU 110 of the information processing apparatus 100 according to the second embodiment. Information processing device (node) 10 according to the present embodiment
0, the CPU 110 is an interconnection status acquisition unit 1121,
Topology grasping means 1122, maximum interconnection number calculating means 1
123, an improved topology grasping means 1124, an improved topology information notifying means 1125, and an improved topology information transmitting means 1126.

The interconnection status acquisition means 1121 stores the interconnection status of each port of each of the nodes 100 and 200a to 200h, that is, the topology map, into the IEEE.
In the E1394 bus system 1, it is obtained from a node called a bus manager via the IEEE1394 interface unit 140. Then, the topology grasping means 1
Reference numeral 122 analyzes the topology map acquired by the interconnection state acquisition unit 1121 to grasp the topology of the IEEE 1394 bus system 1. Based on the topology of the IEEE 1394 bus system 1 grasped by the topology grasping means 1122, the maximum interconnection number calculation means 1123 calculates the maximum value of the interconnection number (hop number) in each communication path of the IEEE 1394 bus system 1. A certain maximum number of interconnections (maximum number of hops) is obtained.

The improved topology grasping means 1124 analyzes the topology map acquired by the interconnect state acquiring means 1121 and finds a new topology in which the maximum hop number obtained by the maximum interconnect number calculating means 1123 decreases. The improved topology information notifying unit 1125 notifies the user of the new topology obtained by the improved topology grasping unit 1124 using the output unit 150. The improved topology information transmitting means 1126 transmits the new topology obtained by the improved topology grasping means 1124 to the IE.
The data is transmitted to any of the other nodes 200a to 200h via the EE1394 interface unit 140.

The information processing apparatus 10 according to the present embodiment
0 does not necessarily need to include both the improved topology information notifying unit 1125 and the improved topology information transmitting unit 1126, and may be either one. For example, when the information processing apparatus 100 includes the display unit 150, it is not necessary to include the improved topology information transmitting unit 1126, and the improved topology information notifying unit 1125 may display a new topology on the display unit 150. When the information processing apparatus 100 does not include the display unit 150, the new topology is transmitted to any of the other nodes by the improved topology information transmitting unit 1126 without including the improved topology information notifying unit 1125. Then, it may be displayed at the other node.

FIGS. 9 to 11 are flowcharts for explaining the operation of the information processing apparatus 100 according to the second embodiment. The operation described below is performed in the RAM 120, the IEEE1
This is performed by the CPU 110 using the 394 interface unit 140 and the output unit 150 in accordance with a program stored in the ROM 130.

In step S20, the interconnection status acquisition means 1121 of the CPU 110
A node ID for identifying each of the nodes 00a to 200h and an interconnection state, that is, a topology map including information such as a port state in each of the nodes 100 and 200a to 200h, are transmitted from a node called a bus manager in the IEEE1394 to the IEEE1394 interface unit 140. To get through. Step S
In 21, the topology grasping means 1122 analyzes the topology map acquired by the interconnection state acquiring means 1121, and grasps the entire topology of the IEEE 1394 bus system 1.

In step S22, the value of a variable k indicating a node ID is initialized to 0. In step S23,
It is determined whether or not only one other node is interconnected to a node whose node ID is the value of the variable k (hereinafter referred to as “node k”). If one other node is interconnected to node k, steps S26-S46
Process. If two or more other nodes are interconnected to node k, step S24 is processed. In step S24, the value of the node ID variable k is compared with the number of nodes, and it is determined whether or not the processing in steps S23 to S46 has been performed for all nodes. If processing has not been performed for all nodes, the value of the variable k is incremented in step S25, and the process returns to step S23. If the processing has been performed for all nodes, the processing ends.

In steps S26 to S31, the maximum number-of-interconnects calculating means 1123 checks the IEEE139 obtained by the topology detecting means 1122 in step S21.
IEEE 13 based on the topology of the 4-bus system 1
The maximum hop number which is the maximum value among the hop numbers in each communication path of the 94 bus system 1 is obtained.

More specifically, in step S26, the value of a variable i indicating the node ID is initialized to 0, and
Is initialized with the value of a variable MaxHop2 storing the maximum value of the number of hops in the communication path starting from the parameter “0” as 0. In step S27, the number of hops from the node k to the node i is obtained, and the number of hops is held as the value of the variable Hop2 [i].
Then, in step S28, the variable MaxHop2 and the variable
The larger value of each value of Hop2 [i] is newly stored in the variable MaxHop2. In step S29, the value of the node ID variable i is compared with the number of nodes to determine whether or not the processing in steps S27 and S28 has been performed for all nodes. If processing is not performed for all nodes,
In step S30, the value of the variable i is incremented, and the processes in steps S27 and S28 are repeated. If the processing has been performed for all the nodes, the value of the variable MaxHop2 is stored in the variable h in step S31, and the processing from step S32 is performed. At the time when the process of step S32 is started, the maximum value of the number of hops in the communication path starting from the node k is stored in the variables MaxHop2 and h.

In steps S32 to S46, the improved topology grasping means 1124 analyzes the topology map acquired by the interconnect state acquiring means 1121 in step S20, and determines the maximum hop number obtained by the maximum interconnect number calculating means 1123. Find a decreasing new topology.
Then, the improved topology information notifying unit 1125 notifies the user of the new topology obtained by the improved topology grasping unit 1124 using the output unit 150. Also,
The improved topology information transmitting means 1126 transmits the new topology determined by the improved topology grasping means 1124 to the I
The data is transmitted to any of the other nodes 200a to 200h via the EEE1394 interface unit 140.

More specifically, in step S32, the value of the variable i indicating the node ID is initialized to 0 again. In step S33, the value of the variable SumNode indicating the number of nodes (hereinafter referred to as “mobile nodes”) that must move to another port to reduce the maximum value of the number of hops of the IEEE 1394 bus system 1 is set to 0. Initialization is also performed by setting the value of a variable SumPort indicating the number of empty ports (hereinafter, referred to as “destination ports”) to which nodes may be interconnected to reduce the number of hops to 0.

In step S34, it is determined whether the values of the variable Hop2 [i] and the variable h are equal to each other.
Also, in step S35, node i is Hop2 [j] = MaxHo
It is determined whether or not it exists on the communication path between the node j and the node k, which is p2.

In step S34, it is determined that Hop2 [i] = h, and in step S35, node i is Hop2 [j] = Max.
If it is determined that the variable SumNode is present on the communication path between the node j and the node k that is Hop2, the variable SumNode is determined in step S36.
Is incremented, and the node i, which is the mobile node, is stored in the RAM 120 in step S37. And
Proceed to step S41.

If it is determined in step S34 that Hop2 [i] ≠ h, in step S38, 0 <Hop2 [i] <h-1.
Is determined. 0 <Hop2 in step S38
If it is determined that [i] <h−1, step S39
And the number of vacant ports of the node i, which is the destination port, is a variable
In step S40, the free port information of the node i, which is the destination port, is stored in the RAM 120 in addition to the value of SumPort. Then, the process proceeds to step S41.

In step S35, node i is Hop2 [j] = Max
If it is determined that it does not exist on the communication path between the node j and the node k, which is Hop2, and if it is determined that 0 <Hop2 [i] <h−1 is not satisfied in step S38, the process immediately proceeds to step S38. Proceed to S41.

In step S41, the value of the node ID variable i is compared with the number of nodes, and it is determined whether or not the processing in steps S34 to S40 has been performed for all nodes.
If processing has not been performed for all nodes, step S
At step S42, the value of the variable i is incremented.
Return to If the processing has been performed on all nodes, the processing from step S43 is performed.

In step S43, the values of the variables SumNode and SumPort are compared. If it is determined that the value of the variable SumNode is equal to or less than the value of the variable SumPort, the process proceeds to step S44. In step S44, if the mobile node saved in step S37 is interconnected with the destination port saved in step S40, the maximum value of the number of hops of the IEEE 1394 bus system 1 is reduced. Notify the destination port to the user. At this time, the mobile node and the destination port are set to the IEEE 1394 interface unit 140.
May be transmitted to any of the other nodes 200a to 200h via the other node and displayed on the other node. After that, the process ends.

On the other hand, if it is determined in step S43 that the value of the variable SumNode is larger than the value of the variable SumPort, step S45 is performed. In the step S45, it is determined whether or not the variable h is larger than the value 0. If h> 0, the value of the variable h is decremented in step S46, and the processing in steps S32 to S43 is repeated. If h ≦ 0, the process proceeds to step S24.

FIG. 12 shows an IEEE standard according to the second embodiment.
3 is a table showing the state of each information processing device (node) in the 1394 bus system 1; This table shows the node IDs in the IEEE 1394 bus system 1 shown in FIG.
Shows the state of each node when the value of the variable k indicating 0 is 0. Field F5 shows the node ID of the node. The field F6 indicates the number of hops Hop2 [i] from the node to the node 200a having the node ID value of 0. From this chart, Max indicates the maximum value of the variable Hop2 [i].
The value of Hop2 is 5.

FIG. 13 shows an IEEE standard according to the second embodiment.
3 is a chart showing a state of the 1394 bus system 1; This chart also shows the IEEE 1394 bus system 1 shown in FIG.
2 shows the state of the IEEE 1394 bus system 1 when the value of the variable k indicating the node ID is 0. Field F7 indicates the value of a variable h indicating the number of hops. Field F8 indicates a mobile node. Field F
Reference numeral 9 denotes a value of a variable SumNode indicating the number of mobile nodes. Field F10 indicates a destination port. Field F11
Indicates the value of the variable SumPort indicating the number of destination ports.

For example, when h = 4, Hop2 [i] = 4, and the nodes 200f and 200f both exist on the communication path from the node 200a to the node 200g and on the communication path from the node 200a to the node 200h. 100 is a mobile node. Also, 0 <Hop2 [i] <
The vacant port P6 of the node 3 is the destination port. As shown in FIG. 13, the mobile node and the destination port that satisfy the condition of SumNode ≦ SumPort
0e, port P6.

FIG. 14 is a view for explaining a display example on the display unit 150 of the information processing apparatus 100 according to the second embodiment. As shown in this figure, the information processing device (node)
The upper part of the display unit 150 of the IEEE 100 shown in FIG.
The connection configuration of each node in the E1394 bus system 1, that is, the current topology is shown. Node 10
In the lower part of the display unit 150 of 0, the connection configuration of each node when the mobile node 200e is connected to the destination port P6, that is, an improved topology is shown.

As described above, according to the information processing apparatus and the bus system according to the present embodiment, a new topology that can reduce the maximum value of the number of hops of the bus system can be obtained. Therefore, the user who is notified of the requested new topology can easily construct an appropriate bus system, and secure a necessary bus bandwidth and perform normal data transfer.

(Third Embodiment) Next, an information processing apparatus and a bus system according to a third embodiment of the present invention will be described. The schematic configuration of the bus system according to the third embodiment is substantially the same as that described with reference to FIG. 1 in the first embodiment. The schematic configuration of the information processing apparatus according to the third embodiment is substantially the same as that described with reference to FIG. 2 in the first embodiment. However, the processing content of the CPU 110 of the information processing device (node) 100 according to the third embodiment is different from that of the first embodiment.

FIG. 15 is a diagram showing functional blocks in the CPU 110 of the information processing apparatus 100 according to the third embodiment. Information processing device (node) 1 according to the present embodiment
00, the CPU 110
1, topology grasping means 1132, bus bandwidth shortage judging means 1133, topology storing means 1134, additional information processing apparatus interconnection detecting means 1135, additional information processing apparatus specifying means 1136, additional information processing apparatus information notifying means 113
7 and additional information processing device information transmitting means 1138.

The interconnection status acquisition means 1131 converts the interconnection status of each port of each of the nodes 100 and 200a to 200h, ie, the topology map, into an IEEE
In the E1394 bus system 1, it is obtained from a node called a bus manager via the IEEE1394 interface unit 140. Then, the topology grasping means 1
132 analyzes the topology map acquired by the interconnection state acquisition means 1131 and grasps the topology of the IEEE 1394 bus system 1.

The bus bandwidth shortage determination means 1133 determines whether the bus bandwidth required for communication by each of the nodes 100 and 200a to 200h is insufficient. Preferably, nodes 100 and 200a-200
h. Calculate the required bus bandwidth, which is the sum of the bus bandwidths required for each communication, and attempt to secure the calculated required bus bandwidth. If not, it is determined that the bus bandwidth is insufficient.

When the bus bandwidth shortage determination unit 1133 determines that the bus bandwidth is not insufficient, the topology storage unit 1134 stores the topology information in the topology storage unit 1132.
Is stored in the RAM 120. Topology storage means 11
34 is preferably rewritable. In this case, it is possible to update the storage of the topology of the IEEE 1394 bus system. Also, the topology storage means 113
Preferably, 4 is non-volatile. In this case, the storage of the topology of the IEEE 1394 bus system is retained even when the power is turned off.

Additional information processing device interconnection detection means 113
5 is the IE grasped by the topology grasping means 1132.
Based on the topology of the EE1394 bus system, the IE
It detects that a new node has been added to the EE1394 bus system and interconnected. The additional information processing device specifying means 1136 is provided by the additional information processing device
When it is detected by 135 that a new node has been added to the IEEE 1394 bus system and interconnected, the topology grasped by the topology grasping means 1132 and the topology stored by the topology storage means 1134 are compared, Identify the added new node.

Additional information processing device information notifying means 1137
Notifies the user of the new node specified by the additional information processing device specifying unit 1136 when the bus bandwidth shortage determining unit 1133 determines that the bus bandwidth is insufficient. Further, the additional information processing device information transmitting unit 1138 transmits the new node specified by the additional information processing device specifying unit 1136 to another node when the bus bandwidth shortage determining unit 1133 determines that the bus bandwidth is insufficient. To the node.

The information processing apparatus 10 according to the present embodiment
0 does not necessarily need to include both the additional information processing device information notifying unit 1137 and the additional information processing device information transmitting unit 1138, and may be one of them. For example, when the information processing apparatus 100 includes the display unit 150, it is not necessary to include the additional information processing apparatus information transmitting unit 1138, and the new node specified by the additional information processing apparatus information notifying unit 1137 is displayed on the display unit 150. Should be displayed on the screen. If the information processing apparatus 100 does not include the display unit 150, the additional information processing apparatus information notifying unit 1
The additional node may transmit the specified new node to any one of the other nodes, and display the new node on the other node without providing the additional node 137.

FIGS. 16 and 17 are flowcharts for explaining the operation of the information processing apparatus 100 according to the third embodiment. The operation described below is based on the RAM 120, IE
EE1394 interface section 140 and output section 1
This is performed by the CPU 110 according to a program stored in the ROM 130 using the program 50.

In step S60, the interconnection state acquiring means 1131 of the CPU 110
The node ID for identifying each of the nodes 00a to 200h and the interconnection information, that is, the topology map including information such as the status of the ports in each of the nodes 100 and 200a to 200h, are transmitted from the node called the bus manager in IEEE1394 to the IEEE1394 interface unit 140 To get through. Step S
In 61, the topology grasping unit 1132 analyzes the topology map acquired by the interconnection state acquiring unit 1131, and grasps the entire topology of the IEEE 1394 bus system 1. This grasped topology is referred to as Topology1.

In steps S62 to S65, the additional information processing apparatus interconnection detecting means 1135 detects the IE detected by the topology detecting means 1132 in step S61.
Based on the topology of the EE1394 bus system, the IE
It detects that a new node has been added to the EE1394 bus system and interconnected. The additional information processing device specifying means 1136 detects the topology by the topology information detecting means 1132 when the additional information processing apparatus interconnection detecting means 1135 detects that a new node has been added to the IEEE 1394 bus system and interconnected. The added topology is compared with the topology stored by the topology storage unit 1134, and the added new node is specified.

More specifically, in step S62, IE
The bus bandwidth required for performing the isochronous transfer defined by EE1394 (hereinafter, referred to as "isochronous bus bandwidth") can be secured by all nodes, and the data transfer is normally performed. Topology sometimes stored by the topology storage unit 1134
logy0 and the topology Topolog ascertained in step S61
Compare with y1. In step S62, Topology0 and Topolog
If it is determined that y1 is different, To
New node is IE in Topology1 for pology0
It is determined whether or not the EE1394 bus system is interconnected.

If it is determined in step S63 that the new nodes have been interconnected, in step S64 the newly interconnected nodes are specified, the node ID of the specified nodes is substituted into a variable m, and the new nodes are replaced. The value of the variable newNode indicating that has been interconnected is set to True, and the process proceeds to step S66. Topolo in step S62
When it is determined that gy0 and Topology1 are the same, and when it is determined in step S63 that the new nodes are not interconnected, the variable newNode is determined in step S65.
Is set to False, and the process proceeds to step S66.

In steps S66 to S75, bus bandwidth shortage determination means 1133 determines whether nodes 100 and 200
It is determined whether the bus bandwidth required for communication for each of a to 200h is insufficient. When the bus bandwidth insufficiency determining unit 1133 determines that the bus bandwidth is not insufficient, the topology storage unit 1134 stores the topology of the IEEE 1394 bus system grasped by the topology grasping unit 1132 in step S61. On the other hand, when the bus bandwidth shortage determination unit 1133 determines that the bus bandwidth is insufficient, the additional information processing device information notifying unit 1137 sends the new node specified by the additional information processing device specifying unit 1136 to the new node. The user is notified using the output unit 150. Further, the additional information processing device information transmitting unit 1138 transmits the new node specified by the additional information processing device specifying unit 1136 to any of the other nodes 200a to 200h via the IEEE1394 interface unit 140.

More specifically, in step S66, the value of the variable i indicating the node ID is initialized to 0, and the variable SumBandWidth indicating the total isochronous bus bandwidth used by nodes other than the newly interconnected nodes.
Is initialized to 0. In step S67, the variable
It is determined whether or not the value of newNode is True, and whether or not the values of the variable i and the variable m are equal. If the value of the variable newNode is True and i = m, the process proceeds to step S69; otherwise, the process proceeds to step S68. In step S68, the isochronous bus bandwidth required by the node i which is not a newly interconnected node is cumulatively added to the value of the variable SumBandWidth. In step S69, the value of the variable i is compared with the number of nodes to determine whether or not the processing in steps S67 and S68 has been performed for all nodes. If the processing has not been performed on all nodes, the variable i is determined in step S70.
Is incremented, and the process returns to step S67. If processing has been performed for all nodes, step S71 is performed.

In step S71, the IEEE 1394 is called an isochronous resource manager and
For the node that manages the isochronous bandwidth that can be used in the entire EE1394 bus system, the variable SumBandWid
Attempt to obtain an isochronous bus bandwidth of th value.
In step S72, it is determined whether or not the acquisition of the isochronous bus bandwidth in step S71 has been successful. If the isochronous bus bandwidth is successfully obtained, Topoloy1 is newly set as Topology0 in step S73, and this new Topology0 is stored in the RAM 120,
finish. On the other hand, if acquisition of the isochronous bus bandwidth has failed, the value of the variable newNode is set to T in step S74.
Determine if it is rue. If the value of the variable newNode is True, process the step S75; otherwise,
The process ends. In step S75, the user is notified of the node m using the output unit 150 because the isochronous bus bandwidth required by the nodes other than the newly interconnected node m is insufficient. At this time, the node m is connected to the IEEE 1394 interface unit 140.
May be transmitted to any of the other nodes 200a to 200h via the other node and displayed on the other node. Thus, the process ends.

FIG. 18 is a diagram showing an example of the configuration of an IEEE 1394 bus system. IEEE13 shown in this figure
The 94 bus system, compared to that shown in FIG.
A new node 200i is connected to the port P19 of the node 200h.
Are interconnected. In the following, this new node 2
00i, the nodes 100 and 200a
It is assumed that it is no longer possible to secure the isochronous bus bandwidth required for each of H.about.200 h.

FIG. 19 is a view for explaining a display example on the display unit 150 of the information processing apparatus 100 according to the third embodiment. As shown in this figure, the information processing device (node)
The display unit 150 of the IEEE 100 displays the IEEE1 shown in FIG.
The connection configuration of each node in the 394 bus system is displayed. In this display, the nodes 100 and 200a are connected because the nodes 200i are interconnected.
To 200 h could not secure the isochronous bus bandwidth, the node 200 i
The user is notified by a cross on the node 200i that it should be disconnected from the 94 bus system.

Note that, in the third embodiment, the IEEE
The new interconnecting node for the 1394 bus system is 1
Although the description has been given of the case where the number of nodes is one, even when a plurality of nodes are newly interconnected, a plurality of newly interconnected nodes can be specified by the same processing.

In the third embodiment, the node 200i may be logically separated from the IEEE 1394 bus system while notifying the user of the newly interconnected node i. In P1394a, which is one of the IEEE 1394 standards, a register for controlling the physical layer (hereinafter, referred to as a “PHY register”) is defined.
By appropriately setting the contents of this PHY register, the node 200i
Can be logically separated.

FIG. 20 is a view for explaining the format of the PHY register defined by the P1394a standard. Upper 3 of address 0111 ₂ of this PHY register
Set the value of the bit (PageSelect field) 000 _2, by setting the value of the lower 4 bits (PortSelect field) the port number, corresponding to the port PortStatus
You can refer to the page. FIG. 21 is a view for explaining the format of the PortStatus page corresponding to the port specified by the PHY register. Logical disconnection of the port is
The value 1 may be set to the least significant bit (Disabled field) of the address 1000 ₂ of the PortStatus page for the port in the PHY register.

In the third embodiment, the node 1
00, Topology 0 is stored in the volatile memory RAM 120, but may be stored in a non-volatile memory. Since Topology0 is not erased even if the power of the node 100 is turned off by storing it in the nonvolatile memory, the new node can be specified even when the new node is interconnected after the power is turned off.

As described above, according to the information processing apparatus and the bus system according to the present embodiment, it is possible to secure the bus bandwidth required by other nodes due to the connection of a new information processing apparatus to the bus system. When the information processing cannot be performed, the new information processing apparatus can be specified.
Therefore, the user who has been notified of the specified new information processing apparatus can easily construct an appropriate bus system, and secure a necessary bus bandwidth and perform normal data transfer. .

The present invention is not limited to the above embodiment, and various modifications are possible. For example, the above first to first
In each of the third embodiments, the output unit 150 in the node 100 may be any device that can notify the user of information, such as a liquid crystal display or a printer. The output unit 150 of the node 100 is not always necessary. When the node 100 does not have the output unit 150, the node 100 transmits the node information specified in each embodiment or the obtained topology information to another node having the output unit, and the node having the output unit receives the node information. The user may be notified of the information.

In each of the first to third embodiments, the node 100 analyzes the topology map obtained from the bus manager to grasp the topology.
Receives a Self ID packet transmitted by each node at the time of initialization of the IEEE 1394 bus system, and grasps a topology by analyzing a node ID of the node included in the Self ID packet and a connection state of a port of the node. Is also good.

[0095]

As described in detail above, according to the first information processing apparatus of the present invention, a new information processing apparatus among a plurality of information processing apparatuses constituting a bus system can be interconnected. Are possible and the maximum number of hops in the bus system does not increase when they are interconnected. Therefore, the user who is notified of the specified information processing apparatus can easily construct an appropriate bus system, and can perform a normal data transfer while securing a necessary bus bandwidth.

Further, according to the second information processing apparatus of the present invention, it is possible to obtain a new topology that can reduce the maximum value of the number of hops of the bus system. Therefore, the user who is notified of the requested new topology can easily construct an appropriate bus system, and secure a necessary bus bandwidth and perform normal data transfer.

According to the third information processing apparatus of the present invention, the bus bandwidth required by other nodes cannot be secured due to the connection of a new information processing apparatus to the bus system. Then, the new information processing device can be specified. Therefore, the user who has been notified of the specified new information processing apparatus can easily construct an appropriate bus system, and secure a necessary bus bandwidth and perform normal data transfer. .

Also, in the third information processing apparatus according to the present invention, when the bus bandwidth shortage determining means determines that the bus bandwidth is insufficient, the new information specified by the additional information processing apparatus specifying means. When an additional information processing device disconnecting means for separating the information processing device from the bus system is further provided, an appropriate bus system can always be constructed, a necessary bus bandwidth is secured, and normal data transfer is performed. Can be.

Further, according to the bus system of the present invention, a plurality of information processing apparatuses including any one of the above-described first to third information processing apparatuses of the present invention are interconnected via a bus. Since the bus system is configured by being connected, the user can easily construct an appropriate bus system, and secure a necessary bus bandwidth to perform normal data transfer.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a bus system according to a first embodiment.

FIG. 2 is a block diagram illustrating a schematic configuration of the information processing apparatus according to the first embodiment.

FIG. 3 is a diagram showing functional blocks in a CPU of the information processing apparatus according to the first embodiment.

FIG. 4 is a flowchart illustrating an operation of the information processing apparatus according to the first embodiment.

FIG. 5 is a flowchart illustrating an operation of the information processing apparatus according to the first embodiment.

FIG. 6 is a table showing states of each information processing device in the bus system according to the first embodiment.

FIG. 7 is a diagram illustrating a display example on a display unit of the information processing apparatus according to the first embodiment.

FIG. 8 is a diagram illustrating functional blocks in a CPU of an information processing apparatus according to a second embodiment.

FIG. 9 is a flowchart illustrating an operation of the information processing apparatus according to the second embodiment.

FIG. 10 is a flowchart illustrating an operation of the information processing apparatus according to the second embodiment.

FIG. 11 is a flowchart illustrating an operation of the information processing apparatus according to the second embodiment.

FIG. 12 is a table showing states of information processing devices in the bus system according to the second embodiment.

FIG. 13 is a chart showing a state of a bus system according to the second embodiment.

FIG. 14 is a diagram illustrating a display example on a display unit of the information processing device according to the second embodiment.

FIG. 15 illustrates a CPU of an information processing apparatus according to a third embodiment.
FIG. 3 is a diagram showing functional blocks in FIG.

FIG. 16 is a flowchart illustrating an operation of the information processing apparatus according to the third embodiment.

FIG. 17 is a flowchart illustrating an operation of the information processing apparatus according to the third embodiment.

FIG. 18 is a diagram illustrating a configuration example of a bus system.

FIG. 19 is a diagram illustrating a display example on a display unit of the information processing device according to the third embodiment.

FIG. 20 is a diagram illustrating the format of a PHY register defined by the P1394a standard.

FIG. 21 is a diagram illustrating a format of a PortStatus page corresponding to a port specified by a PHY register.

[Explanation of symbols]

1 IEEE1394 bus system, 100 information processing device (node), 110 CPU, 120 RAM, 1
30 ROM, 140 IEEE 1394 interface unit, 150 output unit, 160 internal bus, 200a
To 200i: information processing device (node), 300: IEEE
E1394 serial bus.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yoshinobu Terui 2274 Hongo, Ebina-shi, Kanagawa Prefecture Fuji Xerox Co., Ltd. F-term (reference) 5B045 BB11 BB12 BB49 JJ08 5K032 BA04 5K033 BA04 DA13

Claims (15)

[Claims] 1. An information processing apparatus, comprising: a plurality of information processing apparatuses interconnected via a bus by an interconnecting means to constitute a bus system and communicate with each other; Interconnection status acquisition means for acquiring an interconnection state of the interconnection means, respectively; and topology grasping means for analyzing the interconnection state acquired by the interconnection state acquisition means to grasp the topology of the bus system. A maximum number of interconnections calculating means for obtaining a maximum number of interconnections which is a maximum value among the number of interconnections in each communication path of the bus system based on the topology of the bus system grasped by the topology grasping means; A new information processing device among the plurality of information processing devices can be interconnected and the new information Information processing apparatus specifying, based on the interconnect state acquired by the interconnect state acquiring means, the one in which the maximum interconnect number calculated by the maximum interconnect number calculating means does not increase when the logical devices are interconnected. An information processing apparatus comprising: means. 2. The information processing apparatus according to claim 1, further comprising an information processing apparatus information notifying unit that notifies a user of the information processing apparatus specified by the information processing apparatus specifying unit. 3. The information processing apparatus according to claim 1, further comprising an information processing apparatus information transmitting unit that transmits the information processing apparatus specified by the information processing apparatus specifying unit to another information processing apparatus. 4. An information processing apparatus, comprising: a plurality of information processing apparatuses interconnected via a bus by an interconnecting means to form a bus system and communicate with each other; Interconnection status acquisition means for acquiring an interconnection state of the interconnection means, respectively; and topology grasping means for analyzing the interconnection state acquired by the interconnection state acquisition means to grasp the topology of the bus system. A maximum number of interconnections calculating means for obtaining a maximum number of interconnections which is a maximum value among the number of interconnections in each communication path of the bus system based on the topology of the bus system grasped by the topology grasping means; Analyzing the interconnect state acquired by the interconnect state acquiring means, and calculating the maximum by the maximum interconnect number calculating means. The information processing apparatus according to claim maximum and improved topology grasping means the number of interconnections seek new topology to reduce, further comprising a being. 5. The information processing apparatus according to claim 4, further comprising an improved topology information notifying means for notifying a user of a new topology obtained by said improved topology grasping means. 6. The information processing apparatus according to claim 4, further comprising an improved topology information transmitting means for transmitting a new topology obtained by said improved topology grasping means to another information processing apparatus. 7. An information processing apparatus of any of a plurality of information processing apparatuses which are interconnected via an interconnecting means via a bus to form a bus system and communicate with each other, wherein the plurality of information processing apparatuses Interconnection status acquisition means for acquiring an interconnection state of the interconnection means, respectively; and topology grasping means for analyzing the interconnection state acquired by the interconnection state acquisition means to grasp the topology of the bus system. A bus bandwidth shortage determination unit that determines whether a bus bandwidth required for communication by each of the plurality of information processing devices is insufficient, and a bus bandwidth shortage by the bus bandwidth shortage determination unit. Topology storage means for storing the topology of the bus system grasped by the topology grasping means when it is determined that there is no An additional information processing apparatus interconnection detecting means for detecting that a new information processing apparatus has been added to the bus system and interconnected based on the topology of the bus system grasped by the topology grasping means; When the information processing device interconnection detecting means detects that a new information processing apparatus has been added to the bus system and has been interconnected, the topology grasped by the topology grasping means and the topology stored by the topology storage means are stored. And an additional information processing device specifying unit that specifies the added new information processing device by comparing the topology with the added topology. 8. The user is notified of the new information processing device specified by the additional information processing device specifying means when the bus bandwidth shortage determining means determines that the bus bandwidth is insufficient. The information processing apparatus according to claim 7, further comprising an additional information processing apparatus information notifying unit. 9. The new information processing apparatus specified by the additional information processing apparatus specifying means when the bus bandwidth shortage determining means determines that the bus bandwidth is insufficient, to another information processing apparatus. 8. The apparatus according to claim 7, further comprising: an additional information processing device information transmitting unit that transmits the information to the device.
An information processing apparatus according to claim 1. 10. The new information processing device specified by the additional information processing device specifying means is disconnected from the bus system when the bus bandwidth shortage determining means determines that the bus bandwidth is insufficient. 8. The apparatus according to claim 7, further comprising an additional information processing device disconnecting unit.
An information processing apparatus according to claim 1. 11. A required bus bandwidth calculating means for obtaining a bus bandwidth required for communication by each of the plurality of information processing devices and calculating a required bus bandwidth which is a total of the obtained bus bandwidths. And a required bus bandwidth securing means for securing the required bus bandwidth calculated by the required bus bandwidth calculating means, further comprising: a bus bandwidth shortage determining means, wherein the required bus bandwidth securing means is The information processing apparatus according to claim 7, wherein when the required bus bandwidth cannot be secured, it is determined that the bus bandwidth is insufficient. 12. The information processing apparatus according to claim 7, wherein said topology storage means is rewritable. 13. The information processing apparatus according to claim 7, wherein said topology storage means is nonvolatile. 14. The information processing apparatus according to claim 1, wherein the bus is an IEEE 1394 serial bus. 15. A bus system in which a plurality of information processing apparatuses are interconnected via an interconnecting means via a bus and communicate with each other, and any one of the plurality of information processing apparatuses is provided. 8. A bus system, which is the information processing apparatus according to any one of claims 7 and 8.