JP2000299627A - Load current derivative detection / control circuit - Google Patents

Abstract

(57) [Problem] To provide a load current differential detection / control circuit that can cut off current at high speed only when the load current increases rapidly. SOLUTION: First, second and third semiconductor elements QA, Q
B, QC, a first comparator CMP1 having input terminals connected to the first and third semiconductor elements QA, QC, a resistor R22 connected to an output terminal of the first comparator CMP1, and a resistor R22. A connected capacitor C23, a fifth semiconductor element Q21 in which a first main electrode is connected to the third semiconductor element QC, a control electrode is connected to the resistor R22, and a second ground resistor R24 is connected to the second main electrode; The second semiconductor element QB includes at least a first main electrode, and the fifth semiconductor element Q21 includes a fourth semiconductor element Q22 having a control electrode connected to the second main electrode. Only when the time derivative di / dt of the abnormal current is equal to or more than a predetermined value, the first semiconductor element QA is turned on / off to generate a current oscillation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit capable of detecting a time change of a load current which does not respond to a gradual change in load current but responds only to a sudden change in load current. It relates to a control circuit.

[0002]

2. Description of the Related Art An abnormal current detection / control circuit shown in FIG.
This circuit selectively supplies power from a battery to each load in an automobile, and controls power supply to the load by a switching element QF with a built-in temperature sensor. In the abnormal current detection / control circuit shown in FIG. 5, one end of a shunt resistor RS is connected to a power supply 101 that supplies an output voltage VB, and the other end is connected to a drain terminal D of a switching element QF with a built-in temperature sensor. Further, a load 102 is connected to the source terminal S of the switching element QF with a built-in temperature sensor. Here, the load 102 corresponds to a headlight of an automobile, a drive motor of a power window, and the like.
The abnormal current detection and control circuit shown in FIG. 5 further includes a driver 901 for detecting the current flowing through the shunt resistor RS to control the driving of the switching element QF with a built-in temperature sensor, and a temperature based on the current value monitored by the driver 901. A / D converter 902 for controlling on / off of the drive signal of switching element QF with built-in sensor, and microcomputer (CPU) 903
And

A first example of the abnormal current detection / control circuit shown in FIG.
A switching element QF with a built-in temperature sensor that operates as a semiconductor element is a monolithic power IC as shown in FIG.
It has the following structure. That is, the main MOS transistor Q
M, a resistor RG, a temperature sensor 121, a latch circuit 122, and an overheat cutoff MOS transistor QS are mounted on the same semiconductor chip. Has an overheat cutoff function for forcibly turning off the switching element QF with a built-in temperature sensor by a gate cutoff circuit integrated on the same semiconductor chip. That is, when the temperature sensor 121 detects that the temperature of the main MOS transistor QM has risen to a temperature equal to or higher than the specified value,
The detection information to that effect is held in the latch circuit 122, and the overheat cutoff MOS transistor QS as the gate cutoff circuit
Is turned on, the main MOS transistor QM is forcibly turned off. Here, the temperature sensor 12
Reference numeral 1 denotes a serial connection of four diodes made of polysilicon or the like, and the temperature sensor 121 is integrated near the main MOS transistor QM. As the temperature of the main MOS transistor QM increases, the forward voltage drops of the four diodes of the temperature sensor 121 decrease, and the nMOS
When the gate potential of the transistor Q51 drops to the potential that is set to the “L” level, the nMOS transistor Q51 transitions from the on state to the off state. Thereby, the nMOS
The gate potential of the transistor Q54 is pulled up to the potential of the gate control terminal G of the switching element QF with a built-in temperature sensor, the nMOS transistor Q53 is turned off, the nMOS transistor Q52 transitions from the off state to the on state, and the latch circuit 122 "1" is latched. At this time, the output of the latch circuit 122 becomes “H” level and the overheat cutoff MOS transistor Q
Since S transitions from the off state to the on state, the true gate TG and the source S _{0 of} the main MOS transistor QM are short-circuited, the main MOS transistor QM transitions from the on state to the off state, and is overheated. It will be.

In FIG. 5, ZD1 maintains 12 V between the gate terminal G and the source terminal S of the switching element QF with a built-in temperature sensor, and an overvoltage is applied to the true gate TG of the main MOS transistor QM integrated in the switching element QF. This is a Zener diode that bypasses this when it is about to be applied. The driver 901 includes a differential amplifier 911, 913 as a current monitor circuit, a differential amplifier 912 as a current limiting circuit, and a charge pump circuit 91
5 based on the on / off control signal from the microcomputer 903 and the overcurrent determination result from the current limiting circuit.
A drive circuit 914 for driving the true gate G of the switching element QF with a built-in temperature sensor through G is provided. If an overcurrent is detected via the differential amplifier 912 based on the voltage drop of the shunt resistor RS and the current exceeds the determination value (upper limit), the drive circuit 914 turns off the switching element QF with a built-in temperature sensor. age,
Thereafter, when the current drops below the judgment value (lower limit), the switching element QF with a built-in temperature sensor is turned on. On the other hand, the microcomputer 903 includes a current monitor circuit (differential amplifier 9).
11, 913), the current is constantly monitored, and if an abnormal current exceeding the normal value flows, the drive signal of the switching element QF with a built-in temperature sensor is turned off to turn off the switching element QF with a built-in temperature sensor. Let it. If the temperature of the switching element with built-in temperature sensor QF exceeds the specified value before the drive signal for the off control is output from the microcomputer 903, the switching element with built-in temperature sensor QF is turned off by the overheating cutoff function of the switching element QF itself. It turns off.

[0005]

However, the above-mentioned conventional abnormal current detection / control circuit has a configuration that requires a shunt resistor RS connected in series to a power supply path in order to perform current detection. However, due to the recent increase in load current, there is a problem that the heat loss of the shunt resistor cannot be ignored.

The overheat cutoff function and the overcurrent control circuit described above function when an almost complete short circuit occurs in the load 102 or wiring and a large current flows. When a small short-circuit current flows due to a rare short-circuit such as a short-circuit, it does not function, and the microcomputer 903 must detect an abnormal current through the current monitor circuit and control the switching element QF with built-in temperature sensor to be turned off. However, there has been a situation that the response by the microcomputer to such an abnormal current is poor.

Further, the shunt resistor RS and the A / D converter 9
02, the microcomputer 903 and the like are required, so that a large mounting space is required, and there is also a problem that these relatively expensive articles increase the apparatus cost.

Further, the load current increases due to the gradual change of the friction coefficient with time as in driving a power window of an automobile, and the load current increases sharply as in the case where an arm is pinched in the power window. There is no known overcurrent control circuit capable of instantaneously discriminating and preventing an accident.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and circumstances, and does not respond to a gradual change in load current but responds only to a sudden change in load current with a simple configuration. An object of the present invention is to provide a circuit capable of detecting the time derivative di / dt of the load current, that is, a load current derivative detection / control circuit.

Another object of the present invention is to provide a load current differential detection / control circuit which does not require a shunt resistor directly connected to a power supply path for current detection and can suppress heat loss of the device. It is in.

Still another object of the present invention is to detect a rare short circuit such as an incomplete short circuit having a certain short-circuit resistance or to detect a time derivative di / dt of a load current and to have a large time derivative di / dt. An object of the present invention is to provide a load current differential detection / control circuit that can respond at high speed only in the case.

Still another object of the present invention is to provide an inexpensive load current differential detection / control circuit which can be easily integrated.

[0013]

In order to achieve the above object, the present invention provides a first semiconductor element having first and second main electrodes and a control electrode, and a first main electrode of the first semiconductor element. ,
A second semiconductor element having a first main electrode, a control electrode, and a second main electrode respectively connected to the control electrode, and a second main element, a first main electrode of the first semiconductor element, connected to the control electrode, respectively. A third semiconductor element having a first main electrode, a control electrode, and a second main electrode; a first input terminal connected to a second main electrode of the first semiconductor element; A first comparator in which a second input terminal is connected to the main electrode of the first and second comparators, a second comparator for comparing the respective second main electrode voltages of the first and second semiconductor elements, and a second comparator A drive circuit for supplying a control voltage to each control electrode of the first to third semiconductor elements in accordance with an output of the first semiconductor element; a first signal terminal for a second main electrode of the second semiconductor element; The second signal terminal was connected to the second main electrode of the element, and the third signal terminal was connected to the output terminal of the first comparator. Characterized in that it is a load current differential sensing and control circuit having at least a flow rate of rise discrimination circuit. The load current derivative detection / control circuit according to the present invention detects the time derivative of the current flowing through the load connected to the second main electrode of the first semiconductor element, and sets the time derivative to a predetermined value. Only in the above case, the first semiconductor element is turned on / off to generate current oscillation, and the current oscillation interrupts the conduction state of the first semiconductor element. Here, MOSFETs and MOSs are used as the first to third semiconductor elements.
A MOS transistor (insulated gate transistor: IGT) such as an electrostatic induction transistor (SIT) can be used. In addition, emitter-switched thyristors (ES
T), a MOS composite device such as a MOS control thyristor (MCT) or another insulated gate power device such as an IGBT can be used. These semiconductor elements may be of an n-channel type or a p-channel type. The “first main electrode” means either the emitter electrode or the collector electrode in an IGBT, or the source electrode or the drain electrode in a MOS transistor such as a MOSFET or a MOSSIT. The “second main electrode” is one of an emitter electrode and a collector electrode that does not become the first main electrode in an IGBT, and one of a source electrode and a drain electrode that does not become the first main electrode in a MOS transistor. Mean one. That is, if the first main electrode is an emitter electrode, the second main electrode is a collector electrode, and if the first main electrode is a source electrode, the second main electrode is a drain electrode. The “control electrode” obviously means the gate electrodes of the IGBT and the MOS transistor.

As a first semiconductor element constituting the load current differential detection / control circuit of the present invention, for example, a power MOSFET
Is used, the power MO that forms part of the power supply path
The voltage between the terminals (drain-source voltage) of the SFET is
In the voltage characteristics at the time of transition from the off state to the on state (for example, falling in the case of an n-channel FET),
It changes according to the impedance of the power supply path and the load, that is, the wiring inductance of the path and the time constant based on the wiring resistance and the short-circuit resistance. For example, in a normal operation in which a short circuit does not occur, the voltage quickly decreases to a predetermined voltage or less, but when a complete short circuit occurs, the voltage does not decrease to a predetermined voltage or less. In addition, when an incomplete short circuit having a certain short-circuit resistance occurs, although the voltage converges to a predetermined voltage, it takes a long time to converge.

The load current differential detection / control circuit of the present invention comprises:
The transitional voltage characteristics of the semiconductor element when transitioning from the off state to the on state are used. That is, the first
By detecting the difference between the voltage between the terminals of the semiconductor element and the voltage between the terminals of the second semiconductor element (reference voltage), the voltage between the terminals of the first semiconductor element that forms a part of the power supply path (ie,
Power supply path current) deviates from the normal state in consideration of whether the degree of deviation from the normal state is a sudden change or a gentle change,
The conduction state of the first semiconductor element is cut off only when it is determined that the change is a sudden change. That is, if the change in the current is gentle, the potential of the second main electrode of the first semiconductor element constituting the current mirror circuit and the potential of the second main electrode of the second semiconductor element are changed.
However, in the case of a sudden change, the conduction state of the first semiconductor element is cut off by preventing the potential of the current mirror circuit from matching. In the load current differential detection / control circuit of the present invention, a conventional shunt resistor connected in series to a power supply path for performing current detection is unnecessary.
In addition, not only the overcurrent due to a complete short circuit but also the abnormal current when a rare short circuit such as an incomplete short circuit having a certain short resistance occurs occurs, the current is differentiated over time (current rise rate) d.
It can be easily detected in consideration of i / dt.

Specifically, the load current differential detection and
The “current rise rate discrimination circuit” used for the control circuit includes a parallel circuit including a diode having one end connected to the third signal terminal and a second resistor connected in parallel to a series circuit of the first resistor; A capacitor connected between the other end of the parallel circuit and the ground potential, a first main electrode connected to the first signal terminal, and a first ground resistance connected between the second main electrode and the ground potential. A fourth semiconductor element connected thereto, a first main electrode connected to a second signal terminal,
A control electrode is connected to the other end of the parallel circuit, a second main electrode is connected to a control electrode of the fourth semiconductor element, and a second ground resistor is connected between the second main electrode and a ground potential. And the fifth semiconductor element described above. Here, the second resistor may be a variable resistor, and the capacitor may be a variable capacitor.

The "first semiconductor element" used in the load current differential detection / control circuit according to the present invention includes a temperature sensor, a latch circuit connected to the temperature sensor, and an overheat shut-off circuit having a control electrode connected to the latch circuit. It is possible to comprise a switching element with a built-in temperature sensor comprising a transistor and a main transistor in which a control electrode is connected to the overheating cutoff transistor.

[0018] Further, an on / off frequency integrating circuit connected to the second main electrode of the first semiconductor element and the temperature sensor may be provided. With this configuration, it is possible to configure the first semiconductor element to be turned off when the number of times of on / off control of the first semiconductor element reaches the predetermined number by the on / off number integration circuit.

The first, second, and third semiconductor elements used in the load current differential detection / control circuit of the present invention may be semiconductor elements having the same transmission conductance per unit length (unit channel width). The current mirror circuit may be configured such that the rated current capacity of the first semiconductor element is n times the rated current capacity of the second and third semiconductor elements, where n is a positive integer of 2 or more. .

The fourth semiconductor element of the current rise rate discrimination circuit can be constituted by an npn-type bipolar transistor, and the fifth semiconductor element can be constituted by a pnp-type bipolar transistor.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a load current differential detection / control circuit according to an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals.

As shown in FIG. 1, the load current differential detection / control circuit according to the embodiment of the present invention has a first main electrode connected to an input terminal T1, and a first main electrode connected to an output terminal T3. Semiconductor device Q having two main electrodes and a control electrode
A, a second semiconductor element QB having a first main electrode, a control electrode, and a second main electrode respectively connected to the first main electrode and the control electrode of the first semiconductor element QA; A third semiconductor element QC having a first main electrode, a control electrode, and a second main electrode respectively connected to the first main electrode and the control electrode of the element QA, and a second semiconductor element QC of the first semiconductor element QA. A first comparator C having a first input terminal connected to the main electrode and a second input terminal connected to the second main electrode of the third semiconductor element QC;
MP1 is compared with a second comparator CMP2 that compares the second main electrode voltage of each of the first and second semiconductor elements, and the first to third semiconductor elements QA are output in accordance with the output of the second comparator CMP2. , QB, QC control electrodes GA, GB,
A driving circuit 111 for supplying a control voltage to the GC, and a first signal terminal T27 connected to the second main electrode SB of the second semiconductor element QB.
A current rise rate discrimination circuit 31 in which the second signal terminal T26 is connected to the second main electrode SC of the third semiconductor element QC, and the third signal terminal T25 is connected to the output terminal of the first comparator CMP1.
1 is a power IC. Here, the current increase rate discrimination circuit 311 is a parallel circuit including a diode D21 having one end connected to the third signal terminal T25 and a second resistor R22 connected in parallel to a series circuit of the first resistor R21. A capacitor C23 connected between the other end of the parallel circuit and the ground potential (GND), and a first signal terminal T
27, a first main electrode is connected to the second main electrode, a first ground resistor R25 is connected between the second main electrode and the ground potential, and a first main electrode is connected to the second signal terminal T26. The control electrode is connected to the other end of the electrode and the parallel circuit, and the second main electrode is connected to the fourth
The fifth semiconductor element Q21 is connected to the control electrode of the semiconductor element Q22, and further has a second ground resistor R24 connected between the second main electrode and the ground potential.

With such a circuit configuration, the load current differential detection / control circuit according to the embodiment of the present invention detects the time differential di / dt of the abnormal current flowing through the load 102 connected to the output terminal T3. Only when the time differential value is equal to or greater than a predetermined value, the first semiconductor element (first semiconductor element) QA is turned on / off to generate a current oscillation, and the number of times of the current oscillation is integrated to thereby obtain an input. Terminal T1
And the output terminal T3 is disconnected. In the load current differential detection / control circuit according to the embodiment of the present invention, a first semiconductor element (power device) QA and a control circuit for shutting off the first semiconductor element QA are integrated on the same substrate. It has a power IC configuration.

In order to integrate the number of current oscillations, the load current differential detection / control circuit of the present invention further includes an on / off number integration circuit 304 shown in FIG. In other words, the on / off count integrating circuit 304 is a circuit that can shut off the first semiconductor element QA after a predetermined time (after the count has reached a predetermined number) when an abnormality occurs in the load. The on / off times integration circuit 304 includes a node N51 in FIG.
And nodes N52, N53, N54, N55, N in FIG.
56. With this configuration, for example, when a load abnormality such as a pinch between the power windows occurs and the load current suddenly increases, the first semiconductor element QA turns on / off. The driving force of the motor is limited by turning on / off the first semiconductor element QA. Then, when the entrapment state continues for a certain period of time, the motor corresponding to the load 102 is stopped, so that an increase in the entrapment force due to the rise of the glass of the power window can be prevented.

In the on / off frequency integration circuit 304,
The diode D32 is connected to the node N51 in FIG. The diode D32 has an nMOS
The transistor Q31 is connected, and a capacitor C31 and a resistor R33 are connected in parallel between the gate electrode of the nMOS transistor Q31 and the ground potential (GND). A resistor R30 is connected to the node N53 in FIG. 1, and a resistor R31 is connected between the resistor R30 and the nMOS transistor Q31. Node N55 and nMO of FIG.
Pnp between the gate electrode of S transistor Q31
-Type bipolar transistors Q32 and Q34 and a resistor R
32 is inserted. pnp
A resistor R36 and a reverse current blocking diode D3 are provided between the base electrode of the bipolar transistor Q32 and the resistor R31.
1 is inserted. A series connection circuit composed of a resistor R35 and an npn bipolar transistor Q33 is inserted between the base electrode of the pnp bipolar transistor Q34 and the ground potential (GND). The node N54 in FIG. 1 is connected to a connection point between the collector electrode of the pnp bipolar transistor Q32 and the emitter electrode of the pnp bipolar transistor Q34. Further, between the node N54 and the base electrode of the npn-type bipolar transistor Q33,
A series connection circuit including a Zener diode ZD31, a resistor R34, and a diode D33 is inserted.
The resistor R37 is connected between the base electrode and the emitter of the npn-type bipolar transistor Q33.

The on / off frequency integrating circuit 304 shown in FIG.
In the on / off operation, when the gate drive is off, a potential is generated at the source electrode of the first semiconductor element QA, and this is detected and the duration is integrated. When the gate drive is off, the pnp bipolar transistor Q32 turns on. At this time, the first semiconductor element Q
When a potential is generated at the source electrode of A, Zener diode ZD31, resistor R34, diode D33 and resistor R
37 and the ground potential (GN)
A current flows through D), and the npn-type bipolar transistor Q33 is turned on. When the npn-type bipolar transistor Q33 turns on, the pnp-type bipolar transistor Q34 turns on. When the pnp bipolar transistor Q34 is turned on, pn
p-type bipolar transistors Q32 and Q34, resistor R
32 and a capacitor C31, a current flows to the ground potential (GND) through a series connection circuit,
31 is charged.

Although the gate potential of the nMOS transistor Q31 is initially lower than the threshold value, it is in an off state. However, when the gate potential rises with the charging of the capacitor C31, nM
OS transistor Q31 transitions to the ON state. nMO
When the S-transistor Q31 transitions to the ON state, the node N51 on the anode side of the temperature sensor 121 shown in FIG. 6 is pulled down. ,
The first semiconductor element QA is shut off.

Various forms can be adopted as the power IC constituting the load current differential detection / control circuit of the present invention. For example, the first to third semiconductor elements QA, QB, Q
C, the first and second comparators CMP1 and CMP2 and the drive circuit 111 are integrated on the same semiconductor chip 110,
A configuration of a monolithic power IC may be used. Furthermore, the first
To third semiconductor elements QA, QB, QC, first and second
The comparators CMP1 and CMP2, the drive circuit 111, and the current increase rate identification circuit 311 are all the same semiconductor chip 11.
If integrated on a chip, an extremely lightweight and small monolithic power IC can be realized. Alternatively, the first to third semiconductor elements QA, QB, QC, the first and second comparators CMP
, CMP2, and the drive circuit 111 are integrated on the same semiconductor chip 110, and the current increase rate identification circuit 311 is
A multi-chip module (MCM) configuration or hybrid IC in which the semiconductor chip 110 and another semiconductor chip 311 are integrated on another semiconductor chip 311 different from this semiconductor chip and mounted on the same circuit board (mounting board) The configuration of is also acceptable. In this case, as the circuit board (mounting board), an insulating substrate such as ceramic or glass epoxy, an insulating metal substrate, or the like can be used. Input terminal T
1 and the output terminal T3 may be connected in the form of primary mounting with a bonding wire or the like on a mounting wiring on a circuit board (mounting board), and the semiconductor chip 110 is mounted on a ceramic substrate. After connecting to the wiring on the ceramic substrate with a bonding wire or the like, the wiring may be connected to the mounting wiring in the form of secondary mounting such as soldering. Further, as the hybrid IC, the first to third semiconductor elements QA, QB, Q
C, the first and second comparators CMP1 and CMP2, and the driving circuit are monolithically integrated on the same semiconductor chip 110, and the fourth semiconductor element Q22 and the fifth semiconductor element Q22 are integrated.
21 is the same circuit board (mounting board) as an individual element
A configuration in which it is mounted together with the semiconductor chip 110 may be used.

The first to third semiconductor elements QA, QB, QC, the first and second comparators CMP1, C
The semiconductor chip 1 in which all of the MP2 and the drive circuit are the same
There is no need to be on 10. For example, the first and second comparators CMP1 and CMP1 may be mounted on a circuit board (mounting board) by using the first to third semiconductor elements QA, QB, and QC as individual elements.
2, and a configuration in which the driving circuit is mounted together with the integrated semiconductor chip 110 may be used. For example, if the first semiconductor element (first semiconductor element) QA is a high power device of 100A class to several thousands A class or more, the first semiconductor element QA is independently mounted as an individual element in terms of heat dissipation design. May be preferred.

As the first semiconductor element (power device) QA of the load current differential detection / control circuit of the present invention, a semiconductor switching element having a thermal cutoff function is preferable. As the first semiconductor element QA having the heat-sensitive shut-off function,
For example, it is also possible to use an individual element having a circuit configuration equivalent to the switching element QF with a built-in temperature sensor shown in FIG. 6 (however, in this case, the first semiconductor element QA is strictly more than an individual element. , A monolithic power IC having the circuit configuration shown in FIG. 6). Therefore, this first
The semiconductor element QA is mounted on a circuit board (mounting board) together with another semiconductor chip on which the control circuit of the first semiconductor element QA is mounted.
The configuration of the hybrid IC mounted on the device may be used.

In the configuration of the hybrid IC, the power supply voltage VB is supplied from the power supply 101 to the input terminal T1 via the input lead terminal of the circuit board (mounting board). Further, the output terminal T is output via an output lead terminal or the like.
3, a predetermined load 102 is connected. In the case of a monolithic IC configuration, the input terminals T are connected via input lead terminals of a package having a ceramic substrate or the like.
1, a power supply voltage VB is supplied from a power supply 101, and a predetermined load 10 is applied to an output terminal T3 via an output lead terminal or the like.
2 are connected. Of course, in these hybrid ICs and monolithic ICs, a resin mold or a metal case may be used.

In the monolithic power IC constituting the load current differential detection / control circuit of the present invention, the layout configuration of the circuit elements required for the thermal cutoff function depends on the width of the surface wiring on the semiconductor chip and the width of the element isolation region. It is determined by comprehensive layout design including the structure. In other words, the circuit elements required for the thermal cutoff function shown in FIG. 6 are optimized on the same semiconductor chip together with the layout of the circuit elements required for other functions such as the on / off frequency integration circuit 304 shown in FIG. . In the case where the on / off frequency integration circuit 304 is provided, a temperature sensor is not necessarily required for the first semiconductor element QA, and thus a simple individual element may be used.

The first semiconductor element QA used in the load current differential detection / control circuit of the present invention is, for example, DM
A power MOSFET having an OS structure, a VMOS structure, or a UMOS structure, or a MOSSIT having a structure similar thereto can be used. Further, a MOS composite device such as EST or MCT or another insulated gate power device such as IGBT can be used. Furthermore, if the gate is always used with a reverse bias, a junction FET, a junction SIT, an SI thyristor, or the like can be used. In any case, the first semiconductor element QA may be an n-channel type or a p-channel type. Therefore, the power IC according to the embodiment of the present invention shown in FIG. 1 has both an n-channel type and a p-channel type.

In the following, the same semiconductor chip 110
An n-channel power IC in which predetermined circuit elements such as the first semiconductor element QA as shown in FIG. 1 are monolithically integrated will be described above. That is, the first semiconductor element Q
A is, for example, a main element (power device) QM as shown in FIG. 6, a resistor RG connected to a true gate of the main MOS transistor QM, a temperature sensor 121, a temperature sensor 1
An nMOS transistor Q51 having a gate connected to 21;
This is a circuit on the semiconductor chip 110 including a latch circuit 122 connected to the output side of the nMOS transistor Q51 and an overheat cutoff MOS transistor QS having a gate connected to the output side of the latch circuit 122. Therefore, the first
The first and second main electrodes of the semiconductor element QA are connected to the first and second main electrode regions of a main element (power device) constituting the first semiconductor element QA, respectively. The “first main electrode region” means one of an emitter region and a collector region in an IGBT, and one of a source region and a drain region in a power MOS transistor such as a power MOSFET or a power MOSSIT. The "second main electrode region" means either an emitter region or a collector region that does not become the first main electrode region in an IGBT, or a source region or a drain that does not become the first main electrode region in a power MOS transistor. Means one of the areas. That is, the first
If the main electrode region is an emitter region, the second main electrode region is a collector region, and if the first main electrode region is a source region, the second main electrode region is a drain region. Also,
Of course, the “control electrode” means the gate electrode of the IGBT and the power MOS transistor. Second and third transistors having current-voltage characteristics similar to those of the first semiconductor element QA.
Similarly, “main electrodes” and “control electrodes” are defined for the semiconductor elements QB and QC. This first semiconductor element QA
For example, a power device having a multi-channel structure in which a plurality of unit cells (unit cells) are connected in parallel may be used as the main element QM.

As the main element QM, an MO as shown in FIG.
A case where an S transistor is used will be described as an example.
In FIG. 6, the true gate of the main element (main MOS transistor) QM is connected to the output side of the overheat cutoff MOS transistor QS. The main MOS transistor QM
This is a power MOS transistor having a multi-channel structure in which a plurality of unit cells (unit cells) are connected in parallel. The second and third semiconductor elements QB and QC are arranged at adjacent positions so as to be connected in parallel to the main MOS transistor (power device) QM. As a result, the first semiconductor element QA and the second and third semiconductor elements QB and QC are integrated on the same semiconductor chip 110. The second and third semiconductor elements QB and QC do not require a circuit for overheating a reference device such as a temperature sensor, a latch circuit, or a MOS transistor QS for overheating. Second and third semiconductor elements QB, Q
C is the first semiconductor element QA (main MOS transistor Q
Since they are arranged at adjacent positions in the same process as in the case of M), it is possible to remove (reduce) variations in electrical characteristics due to the influence of temperature drift and non-uniformity between lots. Second
The number of unit cells connected in parallel constituting the second and third semiconductor elements QB and QC is adjusted so that the current capacity of the third semiconductor elements QB and QC is smaller than the current capacity of the main MOS transistor QM. . For example, the second and third
By configuring the unit cell number n of the first semiconductor element QA (main MOS transistor QM) to be 1000 for the unit cell number of the semiconductor elements QB and QC, the second and third semiconductor elements QB, The ratio between QC and the channel width W of the first semiconductor element QA is set to 1: n (n = 1000). The temperature sensor 121 includes a pn junction diode formed of a polysilicon thin film deposited on an interlayer insulating film formed on the second and third semiconductor elements QB and QC and the first semiconductor element QA. ing. That is, the temperature sensor 121 in which a plurality of polysilicon diodes are connected in series is integrated at a position near the channel region of the main MOS transistor QM.

In such a configuration, if the junction temperature of the main MOS transistor QM rises and the temperature of the surface of the semiconductor chip 110 rises, the forward voltage drop of the temperature sensor 121 decreases in accordance with this rise in temperature. That is, since the voltage across both ends of the diodes connected in series drops, the gate potential of the nMOS transistor Q51 becomes "L".
The potential drops to a level, and the nMOS transistor Q51 transitions from the on state to the off state. As a result, the gate potential of the nMOS transistor Q54 is pulled up to the potential of the gate control terminal G of the first semiconductor element QA, the nMOS transistor Q54 transitions from the off state to the on state, and "1" is latched in the latch circuit 122. Will be done. At this time, the output of the latch circuit 122 becomes “H” level and the overheat cutoff MOS transistor Q
S transitions from the off state to the on state. As a result, the main M
OS transistor is short-circuited between the true gate TG and the source S ₀ of QM, mainly MOS transistor QM is shifted from the ON state to the OFF state, so that the overheat cut-off operation of the first semiconductor element QA is complete.

The load current differential detection / control circuit of the present invention comprises:
More specifically, as shown in FIG. 1, the second and third semiconductor elements QB and QC, the resistors R1, R2, R5, R14, R
G, Zener diode ZD1, diode D1, second
Comparator CMP2, drive circuit 111, first semiconductor element Q
A first comparator in which the first input terminal is connected to the second main electrode (source electrode) of A, and the second input terminal is connected to the second main electrode (source electrode) of the third semiconductor element QC CMP1
Are monolithically mounted on the same semiconductor substrate (semiconductor chip) 110 together with the first semiconductor element QA. In FIG. 1, ZD1 is a Zener that keeps the voltage between the gate terminal G and the source terminal S of the first semiconductor element QA at 12 V and bypasses the overvoltage when the overvoltage is applied to the true gate TG of the main MOS transistor QM. It is a diode. Further, on the peripheral portion of the semiconductor chip 110, an input / output terminal T16 connected to the second input terminal of the first comparator CMP1, and an input / output terminal T15 connected to the output terminal of the first comparator CMP1. The input / output terminal T17 connected to the second main electrode (source electrode) of the second semiconductor element QB and the input / output terminal T2 connected to the input terminal of the drive circuit 111 are arranged as bonding pads. I have.
These bonding pads are made of silicon oxide (Si)
O ₂ film), PSG film, BPSG film, a silicon nitride film (S
i ₃ N ₄ ) is an aluminum (Al) film or an aluminum alloy film having a thickness of 1 to 10 μm provided on an interlayer insulating film such as i ₃ N ₄ ), and is formed on a circuit board by gold (Au) or aluminum bonding wire. Connected to the mounting wiring.

As shown in FIG. 1, the input / output terminal T15 has a third signal terminal T25 of the current increase rate discrimination circuit 311.
Is connected. The third signal terminal T25 is connected to a parallel circuit including a diode D21 and a second resistor R22 connected in parallel to a series circuit of the first resistor R21. The other end of this parallel circuit and the ground potential (G
ND) is connected to a capacitor C23. Further, a second signal terminal T26 of the current increase rate identification circuit 311 is connected to the input / output terminal T16. Second
A fifth semiconductor element having a first main electrode, a control electrode connected to the other end of the parallel circuit, and a second ground resistor R24 connected between the second main electrode and the ground potential. Q21
Is provided. The input / output terminal T17 has
The first signal terminal T27 of the current rise rate identification circuit 311 is connected. The first signal terminal T27 is connected to a first main electrode and a control electrode to the second main electrode of the fifth semiconductor element Q21, and a first ground resistance is provided between the second main electrode and the ground potential. A fourth semiconductor element Q22 to which R25 is connected is arranged. The input / output terminal T2 has a resistor R10 and a switch S
W1 is connected.

As described above, various forms can be adopted as the load current differential detection / control circuit of the present invention. Therefore, connection between the input / output terminals T15, 16, 17 and the signal terminals T25, 26, 27 in various forms is possible. For example, in the structure of a monolithic power IC in which all circuits including the current rise rate discriminating circuit 311 are integrated on the same semiconductor chip 110, these are made of aluminum (Al) or aluminum alloy (Al-Si, Al) on the semiconductor chip. -Cu-Si) or the like. On the other hand, in the configuration of the multi-chip module (MCM) or the configuration of the hybrid IC, the input / output terminals T1
5, 16, 17 and the signal terminals T25, 26, 27 are connected via bonding wires or mounting wiring. As described above, according to the form of the power IC to be employed, the diode D constituting the current increase rate discrimination circuit 311 is used.
21, the resistors R21 to R25, the capacitor C23, and the semiconductor elements Q21 and Q22 are all or partially integrated on the semiconductor chip 110 in a monolithic manner. When monolithically integrated, the diode D21 and the semiconductor elements Q21 and Q22 may have a predetermined pn junction structure on the surface of the semiconductor chip 110, and the resistors R21 to R21 may be used.
Reference numeral 25 may be a polysilicon resistor or a diffusion resistor.

The fifth semiconductor element (pnp-type bipolar transistor) Q21 and the fourth semiconductor element (npn-type bipolar
Transistor) Q22 is biased to operate in the unsaturated region.

The power IC according to the embodiment of the present invention allows a user or the like to input / output terminals T shown in FIG.
It functions by turning on the switch SW1 connected to the switch SW2. Although shown as a black box 111 and a detailed circuit configuration is not shown, the drive circuit 111 includes a source transistor (npn-type bipolar transistor) having a collector connected to the potential VP supplied from the charge pump 305. , A sink transistor (npn-type bipolar transistor) having an emitter connected to a ground potential (GND) connected in series. Therefore, based on the switching signal by the on / off switching of the switch SW1, the drive circuit 111 controls the on / off of the source transistor and the sink transistor, and
A signal for controlling the driving of the first to third semiconductor elements QA, QB, and QC is output to respective control electrodes. The drive circuit 111 may be constituted by MOS transistors instead of bipolar transistors. The output voltage (power supply voltage) VB of the power supply 101 is, for example, 12 V, and the output voltage VP of the charge pump 305 is, for example, VB + 10 V.

As shown in FIG. 1, the first main electrode (drain electrode) of the first semiconductor element QA and the first main electrode (drain electrode) of the second and third semiconductor elements QB and QC are all common inputs. And is maintained at the same potential. For example, the first to third semiconductor elements QA, QB, QC
However, if a vertical structure such as a DMOS structure, a VMOS structure, or a UMOS structure is used, the same potential can be set in a common n-type buried drain region provided in a p-type substrate. And it is led to the surface by the p-type sinker region,
What is necessary is just to guide | lead to the bonding pad used as a common input terminal T1 with metal wiring, such as aluminum (Al). The first to third semiconductor elements QA, QB, QC are planar (horizontal)
Aluminum transistor (MOS)
Etc., and are connected to each other by a common input terminal T.
What is necessary is just to lead to the 1 bonding pad. The respective resistance values of the first ground resistor R25 and the second ground resistor R24 may be selected in consideration of the ratio of the channel width W of the second and third semiconductor elements QB and QC to the first semiconductor element QM. . The potential V ₊ and the node N1 connected to the "+" input terminal of the first comparator CMP1 "-" the potential of the node N2 which is connected to the input terminal V _- magnitude relationship is important. Resistance of the second grounding resistor R24 _{is, V} + = V _- in the case, the emitter current of the fifth semiconductor element Q21 is,
1/1000 of the drain current _IDQA of the first semiconductor element
The fifth semiconductor element Q21 is selected so as not to be saturated even with the maximum current within the operation range of the drain current _IDQA . If a large value can be selected as the resistance value of the second ground resistor R24, the control accuracy will be high. Conversely, if a small value is selected as the resistance value of the second ground resistor R24, the control accuracy will decrease. This first setting of the ground resistance R25 and the second ground resistor R24, the same drain as when overload current abnormal operation flows into the first semiconductor element QA - the second and third semiconductor voltage V _DS between the source It can be generated in the elements QB and QC.

The first main electrode (drain) of the first semiconductor element QA
Between the first main electrode (source electrode) and the second main electrode (source electrode).
A series circuit with the resistor R2 is connected. The first shown in FIG.
The first semiconductor CMP is connected to the “+” input terminal of the second comparator CMP2.
The voltage between the main electrodes of the element QA (the voltage between the drain D and the source S)
Pressure) V_DSIs divided by a resistor R1 and a resistor R2.
Supplied via anti-R5. Also, the second comparator C
The “−” input terminal of MP2 is connected to the source of the second semiconductor element QB.
Source voltage VS is supplied. In other words, "+" input terminal
Child signal level V₊Is the signal level V of the "-" input terminal₋
If higher, the output of the second comparator CMP2 is
It becomes “H” level, and the driving circuit 111 outputs the gate GA,
A voltage is supplied to GB and GC. Conversely, the “+” input terminal
Signal level V ₊Is the signal level V of the "-" input terminal₋Than
If it is low, the output of the second comparator CMP2 is "L"
Level, and the drive circuit 111 turns off the gate drive.
You. As described later, the second comparator CMP2 is constant.
Have a hysteresis.

FIG. 4 focuses on the first semiconductor element QA.
It is a conceptual equivalent circuit diagram. The first as a first semiconductor element
The equivalent circuit of one semiconductor element QA is_m・
v_i, Drain resistance rd, gate-source capacitance
C_GS, Gate-drain capacitance C_GDAnd drain
Source capacitance C_DSAre simplified. This
Where g _mIs the transmission conductor of the first semiconductor element QA.
Is. Using the equivalent circuit of the first semiconductor element QA
Power supply path from the power supply 101 to the load 102
Is represented as a circuit as shown in FIG. Load 102
Is the wiring inductance L0 of the power supply path and the wiring resistance
R0.

The load current differential detection / control circuit of the present invention
Two semiconductor elements QB and a first semiconductor element QA (main MOS transistor
The ratio of the channel width W of the transistor QM) is 1: n (n = 10
00) to form a current mirror circuit,
(Drain current I of first semiconductor element_DQA) = 1000
× (Drain current I of the second semiconductor element_DQB).
Therefore, the drain current of the first semiconductor element QA is I
_DA= 5A, as the drain current of the second semiconductor element QB
I_DQB= 5mA, the first half
Each drain of the conductor element QA and the second semiconductor element QB
In-source voltage V_DSAnd true gate-source voltage
V_TGSMatches. That is, V_DSA= V_{D SB}, V
_TGSA= V_TGSBBecomes Where V_DSA, V
_DSBAre the first semiconductor element QA and the second semiconductor element, respectively.
It is the drain-source voltage of QB, _TGSA, V
_TGSBAre the first semiconductor element QA and the second semiconductor element, respectively.
This is the true gate-source voltage of the child QB.

The value of the current flowing through the first ground resistor R25 is
The value obtained by dividing the voltage between the second main electrode SB of the second semiconductor element QB and the ground is the reference resistance Rr connected to the second semiconductor element QB. Therefore, the reference resistance Rr changes when the second semiconductor element QB is in the conductive state. Since the fourth semiconductor element Q22 operates in the unsaturated region, the reference resistance Rr
Is larger than the value of the ground resistance R25.

Next, the operation of the load current differential detection / control circuit of the present invention in the triode characteristic (ohmic characteristic) region will be described. When the first semiconductor element QA transitions to the ON state, the drain current _IDQA rises toward the final load current value determined by the circuit resistance. Further, the true gate-source voltage V of the first semiconductor element QA
_TGSA takes a value determined by the drain current _IDQA ,
Drain - while being braked by the mirror effect of the capacitance C _GD due to a decrease in source voltage V _DSA, which also goes rise. V ₊ = V _- of the case, the second
The voltage drop at the grounding resistor R24 is equal to the load current I
_In proportion to _DQA , the fourth semiconductor element Q22 operates as an emitter follower based on the potential at the connection point between the second ground resistor R24 and the fifth semiconductor element Q21. Therefore, R
If 24 = R25, the voltage drop of the first ground resistor R25 is lower than the voltage drop of the second ground resistor R24 by the base-emitter voltage VBE of the fourth semiconductor element Q22. Thus, rather than I _DQA / 1000,
A slightly smaller current will flow through the second semiconductor element QB.

The true gate of the first semiconductor element QA
The source-to-source voltage V _TGSA increases as the drain current _IDQA increases.

V _DSA = V _TGSA + V _{TGD ·····} (1) V _DSB = V _TGSB + V _TGD From a relationship of ..... (2), the _{V DSA -V DSB = V TGSA -V} TGSB = (I DQA -n × I DQB) / g m ····· (3). However, _{g m} is the transconductance of the first semiconductor element QA, n the first semiconductor element QA and the second semiconductor element Q
B is the ratio of the channel width. Therefore, the drain - by detecting the difference _V DSA _{-V DSB} source voltage, it is possible to obtain a difference between the drain current _{(I DQA -n × I DQB)} .

The drain-source voltage V _DSB of the second semiconductor element QB is supplied to the second comparator C via the resistor R14.
The signal is input to the “−” input terminal of MP2. Further, a value V _{+ obtained} by dividing the voltage V _DSA between the drain and the source of the first semiconductor element QA by the resistor R1 and the resistor R2 is supplied to the second resistor V5 via the resistor R5.
Is input to the "+" input terminal of the comparator CMP2. That is, V ₊ = V _DSA × R1 / (R1 + R2) (4) is input to the “+” input terminal of the second comparator CMP2. If the load side is in a normal state, (Rr / n)
<R, V ₊ <V _DSB , and the first semiconductor element QA maintains the ON state. Here, R is the value of the load resistance. When the load side is overloaded, (Rr / n)> R
Then, when V ₊ > V _DSB , the first semiconductor element QA is turned off in the triode characteristic region. Assuming that the source potentials of the first semiconductor element QA and the second semiconductor element QB are V _SA and V _SB , respectively, the first semiconductor element QA
Are turned off, the source potentials V _SA and V _SB decrease toward GND, so that both V _DSA and V _DSB increase. Source potential _{V SA, V S B} is, before reaching the GND _potential, V _{+ <and V DSB} condition is satisfied, the first semiconductor element QA is turned on again. The first semiconductor element QA is
Immediately after the transition to the ON state, it is in the pentode characteristic region (pinch-off region), and then continues the ON state toward the triode characteristic region, and turns off when V ₊ > _VDSB . This is one cycle of the on / off operation. It is due to the inductance of the load circuit that once it is turned off, the off state is maintained, and once it is turned on, the on state is maintained. The inductance of the load circuit is
When the current changes, it works equivalent to a resistance. When the current is decreasing, the sign of the inductance equivalent resistance becomes negative, and the load side resistance is reduced. on the other hand,
When the current increases, the sign of the inductance equivalent resistance becomes positive, and the load-side resistance increases. Therefore, once the first semiconductor element QA is turned off, the first semiconductor element QA maintains the off state, and when the first semiconductor element QA is turned on, the first semiconductor element QA maintains the on state. On the second semiconductor element QB side of the reference circuit, since the first ground resistance R25 (= Rr) is much larger than the load resistance R, the inductance effect is negligibly small. Therefore, it can be considered that the second semiconductor element QB side operates as a pure resistance circuit.

In the second comparator CMP2, a hysteresis is formed by the diode D1 and the resistor R5.
When the first semiconductor element QA transitions to the off state, the gate potential is grounded by the sink transistor of the drive circuit 111, and the cathode side potential of the diode D1 becomes V _SA −
Since the voltage becomes 0.7 V (forward voltage of the Zener diode ZD1), the diode D1 conducts. As a result, a current flows through the path of the resistor R1, the resistor R5, and the diode D1,
The signal level V at the "+" input terminal of the second comparator CMP2
₊ Becomes larger than the value of the above-described equation (4) when the drive circuit 111 performs the ON control. Accordingly, the first semiconductor element QA maintains the off state up to a specific drain-source voltage difference V _DSA −V _{DSB that is} smaller than immediately after the transition to the off state, and thereafter, the V _DSA further increases, signal level _{V +} is "+" input terminal of the second comparator _CMP2, it becomes smaller than _{V DSB,} the output of the second comparator CMP2 changes to "H" level from the "L" level. Therefore, the first semiconductor element QA is again turned on. It should be noted that there are various methods for attaching the hysteresis characteristic, but this is one example.

Threshold V voltage _{V D SA-source} - [0052] the drain when the first semiconductor element QA transition to the OFF state
_{Assuming DSAth} , the following equation holds. That is, V _DSAth −V _DSB = R2 / R1 × V _DSB (5) The overcurrent judgment value in the triode characteristic region is (5)
It will be determined by the formula.

Next, the operation in the pentode characteristic region will be described. When the wiring is normal, the first semiconductor element QA
Transitions to the ON state, the first semiconductor element QA continuously maintains the ON state. For this reason, after the true gate-source voltages V _TGSA and V _TGSB reach the pinch-off voltage, the first semiconductor element QA, the second semiconductor element QB, and the third semiconductor element QC all operate in the pentode characteristic region. . In the load current differential detection / control circuit of the present invention, the second semiconductor element QB and the first semiconductor element QA (main
Since the current mirror circuit is configured with the ratio of the channel width W of the S transistor QM) to 1: n, the ON resistance R _{DS (ON) B} of the second semiconductor element QB is equal to the ON resistance R _{DS (ON) B} of the first semiconductor element QA. N times _{DS (ON) A} (R
_{DS (ON) B} = n · R _{DS (ON) A} ). On the other hand, under the same bias condition, the drain current _IDQB of the second semiconductor element QB becomes the drain current _IDQ of the first semiconductor element QA.
1 / n times _DQA (I _DQB = (1 / n) · I
_DQA ). Referring to the typical on-resistance R _{DS (ON)} of the 5A class semiconductor element, for example, the on-resistance R _{DS (ON) A} of the first semiconductor element QA is changed to the gate-source voltage V _GS = 10V. Then, R _{DS (ON) A} = 30
It can be assumed to be mΩ. If n = 1000, in this case, the ON resistance R _{DS (ON) B of} the second semiconductor element QB
Is 30Ω. Accordingly, V _DSB = I _DQB × R _{DS (ON) B} = 5 [mA] × 30 [Ω] = 0.15 [V] (6) V _DSA = I _DQA × 30 [mΩ] ... (7) V _DSA −V _DSB = 30 [mΩ] × ( _IDQA− 5 [A]) (8)

When an abnormality occurs in the load and the drain current _IDQA increases, the value of the equation (8) increases. When the overcurrent determination value is exceeded, the first semiconductor element QA is turned off. In this case, the state transits to the off state via the pinch-off point and the operation state in the above-described triode characteristic region. Then, the diode D1 and the resistor R5 shown in FIG.
After a certain period of time, the second
The signal level V ₊ of the “+” input terminal of the comparator CMP2 becomes lower than V _DSB , and the output of the second comparator CMP2 changes from “L” level to “H” level, and the first semiconductor element QA To the ON state again. Thus, the first semiconductor element QA repeats the transition to the ON state and the OFF state, and finally reaches the cutoff. Note that if the load returns to normal before the interruption, the first semiconductor element QA continuously maintains the ON state.

The load current differential detection / control circuit of the present invention comprises:
As shown in FIG. 1, the current mirror circuit is configured by connecting a current mirror circuit in parallel with a current mirror circuit that flows a current corresponding to approximately 1 / n of the current flowing in the first semiconductor element QA to the second and third semiconductor elements QB and QC. . These second and third semiconductor elements QB,
The QC is connected to an npn-type bipolar transistor (fourth semiconductor element) Q22 and a pnp-type bipolar transistor (fifth semiconductor element) Q21 which are biased to operate in an unsaturated region. And the first
Comparator CMP1 of the case change in the drain current flowing through the load 102 is gradual, the "+" potential V ₊ and is supplied to the input terminal "-" potential is supplied to the input terminal V _-
So it substantially matches _(V + = _{V -)} to operate. on the other hand,
When the drain current flowing through the load 102 is rapidly increased is, V + _{<V -} the become such an operation. In this case, the behavior differs depending on the magnitude of the current increase rate di / dt due to the presence of the capacitor C23. That is, (a) the current increase rate di / dt of the current flowing through the load 102
Is large: For example, consider a case in which the current flowing through the load 102 sharply rises, for example, when an arm is pinched in a power window of an automobile. At this time, the first semiconductor element Q
Drain of A - source voltage _{V DSA} increases, _positive potential of the node N1 _V is the potential V of the node N2 _- if the lower value, the first comparator CMP1 outputs a "L" level. However, a parallel circuit composed of a diode D21 and a second resistor R22 connected in parallel to a series circuit of the first resistor R21 is connected to the output terminal of the first comparator CMP1, and furthermore, this parallel circuit is connected to ground. Since the capacitor C23 is connected between the capacitor C23 and the potential (GND),
Unless 23 discharges through the resistor R22, the base potential of the pnp bipolar transistor (fifth semiconductor element) Q21 does not decrease. Therefore, the first comparator CMP
1, the base potential of the pnp-type bipolar transistor (fifth semiconductor element) Q21 does not immediately decrease, so that the npn-type bipolar transistor
The base potential of the transistor (fourth semiconductor element) Q22 also does not rise until the capacitor C23 discharges. That is, the potential of the source SB of the second semiconductor element QB is R22
Is substantially constant during a predetermined time constant τ depending on C23. However, since the drain current _IDQA of the first semiconductor element (first semiconductor element) QA continues to increase rapidly,
V ₊ given by equation (4) increases, and finally the second
It becomes higher than the drain-source voltage V _{DSB of the} semiconductor element QB. As a result, the output of the second comparator CMP2 changes from the “H” level to the “L” level, causing the first semiconductor element (first semiconductor element) QA to transition to the off state, and current oscillation to start, Finally, the first semiconductor element (first semiconductor element) QA is fixed in the off state.

(B) When the current rise rate di / dt of the current flowing through the load 102 is small: For example, consider the case where the power window of an automobile gradually becomes heavy due to wear and the like, and the current flowing through the load 102 gradually rises. . Load 10
2 increases, and the potential V _{+ of the} node N1 becomes
If the potential drops below the potential V _{− of the} node N2, the first comparator C
MP1 outputs an “L” level. First comparator CMP
1 has a diode D21 and a first resistor R21.
A parallel circuit composed of a second resistor R22 connected in parallel to the series circuit is connected, and a capacitor C23 is connected between the parallel circuit and the ground potential (GND). The current rise rate di of the current flowing through the load 102 is higher than the rate of discharging through the resistor R22.
If / dt is small, the base potential of the pnp bipolar transistor (fifth semiconductor element) Q21 falls within the time constant τ. As a result, the collector current of pnp type bipolar transistor (fifth semiconductor element) Q21 increases, and the base potential of npn type bipolar transistor (fourth semiconductor element) Q22 also increases. Accordingly, the potential of the source SB of the second semiconductor element QB decreases with the time constant τ, and the drain-source voltage V _DSB increases. Therefore, the rate of increase of V ₊ given by the equation (4) can be compensated, and the output of the second comparator CMP2 can be maintained at the “H” level. Therefore, the current rise rate d of the current
When i / dt is small, current oscillation does not start and normal operation is maintained.

When the output of the first comparator CMP1 transitions from the "L" level to the "H" level, the current passes through the diode D21, so that the value of the first resistor R21 must be sufficiently small. In this case, the capacitor C23 can be charged instantaneously, so that the potentials of the first comparator CMP1 nodes (input terminals) N1 and N2 do not shift, and the potential of the source SB of the second semiconductor element QB changes shortly. Respond in time.

(Other Embodiments) As described above, the present invention has been described with reference to the above embodiments, but it should be understood that the description and drawings constituting a part of this disclosure limit the present invention. Should not be. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

For example, it is possible to use a current rise rate discrimination circuit 312 as shown in FIG. That is, the current rise rate identification circuit 312 shown in FIG.
5 and a first resistor R21.
A variable resistor (second resistor) R32 connected in parallel to the series circuit 21 and a variable capacitor C3 connected between the other end of the parallel circuit and the ground potential (GND).
3 and a first main electrode connected to the first signal terminal T37,
A first ground resistance R25 between the second main electrode and the ground potential;
And a second signal terminal T22.
A first main electrode is connected to 36, a control electrode is connected to the other end of the parallel circuit, a second main electrode is connected to a control electrode of the fourth semiconductor element Q22, and the second main electrode is connected to the ground potential. And a fifth semiconductor element Q21 with a second ground resistor R24 connected between them. The components other than the current increase rate discrimination circuit 312 are the same as those in FIG.

In the current rise rate discrimination circuit 312 shown in FIG. 3, if the second resistor included in the parallel circuit connected to the third signal terminal T35 is replaced by the variable resistor R32, an arbitrary time constant τ can be selected. . Alternatively, the third signal terminal T3
If the capacitor connected to the parallel circuit connected to 5 is a variable capacitor C33, an arbitrary time constant τ can be selected. Therefore, the current rise rate di of the current flowing through the load 102
Even when / dt takes various values, it is possible to provide an optimum current cutoff function.

The configuration of the current rise rate discrimination circuit 312 shown in FIG. 3 is such that the time constant τ can be continuously changed. However, by preparing a plurality of second resistors and capacitors and switching them with a switch, the discreteness is obtained. It is also possible to select a value of a proper time constant τ. That is, the versatility of the load current differential detection / control circuit of the present invention can be enhanced by changing the current rise rate di / dt, which is a threshold value, according to the characteristics of the target load, the use environment, and the like. As described above, the present invention naturally includes various embodiments and the like not described herein. Therefore, the technical scope of the present invention is determined only by the invention specifying matters according to the claims that are appropriate from the above description.

[0062]

According to the present invention, with a simple configuration, it does not respond to a gradual change in load current, responds only to a sudden change in load current, and can cut off overcurrent to detect a load current differential.
A control circuit can be provided.

[Brief description of the drawings]

FIG. 1 shows load current differential detection and detection according to an embodiment of the present invention.
FIG. 3 is a circuit configuration diagram of a control circuit.

FIG. 2 is a circuit configuration diagram of an on / off frequency integration circuit used in a load current differentiation detection / control circuit according to another embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of a load current differential detection / control circuit according to still another embodiment of the present invention.

FIG. 4 is a diagram illustrating load current differential detection and detection according to the embodiment of the present invention.
FIG. 3 is a conceptual equivalent circuit diagram focusing on a first semiconductor element of a control circuit.

FIG. 5 is a circuit configuration diagram of a conventional semiconductor switch.

FIG. 6 is a circuit configuration diagram of a switching element with a built-in temperature sensor.

[Explanation of symbols]

Reference Signs List 101 power supply 102 load 110 semiconductor chip 111 drive circuit 301 overcurrent detection unit 302 current enable unit 304 ON / OFF count integration circuit 305 charge pump unit 306 cut-off latch circuit 311, 312 current rise rate identification circuit C31, capacitor C33 variable capacitor CMP1 1st comparator CMP2 2nd comparator D1, D31, D32, D33 Diode QA, QF First semiconductor element QB Second semiconductor element QC Third semiconductor element Q21 Fifth semiconductor element Q22 Fourth semiconductor element Q31 MOS transistor Q32, Q34 pnp-type bipolar transistor Q33 npn-type bipolar transistor RG Internal resistance R1, R2, R5, R21-R23, R30-R37
Resistance R24 Second ground resistance R25 First ground resistance R32 Variable resistance T1, T2, T3, T14 to T18 Input / output terminal T27, T37 First signal terminal T26, T36 Second signal terminal T25, T35 Third Signal terminal ZD1, ZD31 Zener diode

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H03K 17/687 H03K 17/687 A

Claims (7)

[Claims] A first semiconductor element having first and second main electrodes and a control electrode; a first main electrode connected to the first main electrode and the control electrode of the first semiconductor element, respectively. A second semiconductor element having a control electrode and a second main electrode; a first main electrode and a control electrode respectively connected to the first main electrode and the control electrode of the first semiconductor element; A third semiconductor element having a main electrode; a first input terminal connected to a second main electrode of the first semiconductor element; and a second input terminal connected to a second main electrode of the third semiconductor element. A connected first comparator, a second comparator for comparing a second main electrode voltage of each of the first and second semiconductor elements, and an output of the second comparator, A driving circuit for supplying a control voltage to each control electrode of the first to third semiconductor elements; A first signal terminal to the second main electrode of the device, a second signal terminal to the second main electrode of the third semiconductor device, and a third signal to the output terminal of the first comparator. A current rise rate discrimination circuit having a terminal connected thereto, and detecting a time differential of a current flowing through a load connected to the second main electrode of the first semiconductor element, and detecting a time differential value equal to or greater than a predetermined value. A load current differential detection / control circuit characterized in that a current oscillation is generated by ON / OFF-controlling the first semiconductor element only in a case, and the conduction state of the first semiconductor element is cut off by the current oscillation. 2. The semiconductor device according to claim 1, wherein the first semiconductor element, the second semiconductor element, the third semiconductor element, the first comparator, the second comparator, and the driving circuit are integrated on a same semiconductor substrate. The load current differential detection / control circuit according to claim 1, wherein: 3. The current rise rate discrimination circuit includes a second resistor (R22, R3) having one end connected to the third signal terminal and connected in parallel to a series circuit of a diode and a first resistor.
2) a capacitor connected between the other end of the parallel circuit and a ground potential; a first main electrode connected to the first signal terminal; and a second main electrode connected to the ground. A fourth ground resistance connected to the first ground resistance
A semiconductor element, a first main electrode connected to the second signal terminal, a control electrode connected to the other end of the parallel circuit, a second main electrode connected to a control electrode of the fourth semiconductor element, 2. The load current differential detection / control circuit according to claim 1, further comprising a fifth semiconductor element having a second ground resistor connected between said second main electrode and a ground potential. 4. The circuit according to claim 3, wherein said second resistor is a variable resistor, and said capacitor is a variable capacitor. 5. A temperature sensor disposed near the first semiconductor element, a latch circuit connected to the temperature sensor, an overheat cutoff transistor having a control electrode connected to the latch circuit, and an overheat cutoff transistor. A main transistor having a control electrode connected to the transistor; a second main electrode of the first semiconductor element; and an on / off number integration circuit connected to the temperature sensor. , Turning on / off of the first semiconductor element
The load current differential detection / control circuit according to any one of claims 1 to 4, wherein the first semiconductor element is turned off when the number of times of off control reaches a predetermined number. 6. The load according to claim 1, wherein said first, second, and third semiconductor elements are semiconductor elements having the same transmission conductance per unit channel width. Current derivative detection and control circuit. 7. The rated current capacity of the first semiconductor element is n
7. The load current differential detection / control circuit according to claim 6, wherein n is a positive integer of 2 or more and is n times the rated current capacity of the second and third semiconductor elements.