JP2000299711A - Data communication control device, data communication control method, and recording medium - Google Patents

Abstract

(57) [Summary] [Problem] To easily analyze a failure of various devices that perform serial communication. A serial communication control device according to the present invention includes: a shift register for sequentially taking in a serial signal; a serial interface circuit for controlling the taking in of the serial signal into the shift register; The control circuit 5 includes a command setting register 3 for setting a command, a comparison circuit 4 for comparing a specific command set in the command setting register 3 with data taken into the shift register 1, and a control circuit 5. A specific command included in the serial signal D is set in the command setting register 3, and the serial signal D is set in the shift register 1.
The comparison circuit 4 compares the command set in the command setting register 3 with the data set in the shift register 1, and outputs a trigger signal if the comparison result matches. Command can be triggered.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for taking measures against a failure in a serial communication device that transmits a command, data, and an address through a single signal line.

[0002]

2. Description of the Related Art There is known a serial communication device for transmitting a command, data, and an address of a processor or the like through one signal line. This type of serial communication device is widely used in portable devices using a one-chip microprocessor because the number of signal lines can be reduced as compared with the case of performing parallel communication.

Incidentally, a logic analyzer is one of measuring instruments used when a failure occurs in various electronic devices. Logic analyzers have the feature of being able to observe the logic of multiple signal lines at the same time, triggering when multiple signal lines have reached a predetermined logic, and checking the logic of each signal line before and after the trigger. Used for purposes.

[0004]

However, although a normal logic analyzer can trigger on the logic of a plurality of signal lines, continuous logic changes of one signal line, that is, one It is not possible to trigger on serial data consisting of a plurality of bits transmitted via the signal line of the above.

For this reason, for example, when a write command is issued at an unexpected timing inside the serial communication device and a failure occurs such that the data in the memory is rewritten without permission, the write command is normally issued. At this point, it is desired to apply a trigger. However, the conventional logic analyzer cannot trigger on a serially transmitted command, and thus has a problem that it takes time to take measures against a failure.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a serial communication control device, a serial communication control method, and a recording medium that can easily analyze a failure of various devices that perform serial communication. Is to provide.

[0007]

According to a first aspect of the present invention, there is provided a data communication control apparatus for transmitting a serial signal including a command, data, and an address through a single signal line. Command holding means for holding a specific command included in the serial signal, command determination means for determining whether or not the same command as the held specific command is included in the serial signal, and the command determination means And trigger output means for outputting a coincidence signal when it is determined that the same command as the specific command is included in the serial signal.

According to the first aspect of the present invention, a specific command included in the serial signal is held, and it is determined whether or not the same command as the held specific command is included in the serial signal. In such a case, a coincidence signal (trigger signal) is output, so that a trigger can be reliably performed by a specific command in the serial signal.

According to the second aspect of the present invention, when a predetermined instruction command is included in the serial signal and a specific command is subsequently included, the position of the instruction command is changed to hold the specific command. , Various commands can be held.

According to the third aspect of the present invention, since the serial signal holding means for holding the serial signal in units of a plurality of bits is provided, the command can be easily extracted from the serial signal.

According to the fourth aspect of the present invention, it is possible to take measures against a failure in which a command instructing writing is issued at an unexpected timing.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a serial communication control device, a serial communication control method, and a recording medium according to the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a serial communication control device according to the present invention. The serial communication control device of FIG. 1 is intended to take measures against a failure of the serial communication device, and triggers when a predetermined command is included in a serial signal D for transmitting commands, data and addresses serially.

The serial communication controller shown in FIG. 1 includes a shift register 1 for sequentially taking in a serial signal D, a serial interface circuit 2 for controlling the taking in of the serial signal D into the shift register 1, and a specific interface included in the serial signal D. A command setting register 3 for setting a command;
A comparison circuit 4 for comparing a specific command set in the command setting register 3 with data taken into the shift register 1 and a control circuit 5 for controlling the entire device are provided.

A clock signal CK for controlling the shift operation of the shift register 1 is provided to the serial interface circuit 2.
, A chip select signal CS for instructing start of operation, and a serial signal D. The serial interface circuit 2 recognizes that the data transfer has been started by the chip select signal CS, and instructs the shift register 1 to acquire the serial signal D.
And a fetch completion signal SG2 for notifying the control circuit 5 that data has been fetched into all the registers in the shift register 1.

The control circuit 5 includes a shift register 1
Is analyzed, and it is determined whether or not the data is set in the command setting register 3. When it is determined that the setting in the command setting register 3 is to be performed, the setting instruction signal SG3 is transmitted to the command setting register 3. Further, the control circuit 5 instructs the comparison circuit 4 whether or not to compare the data set in the command setting register 3 with the data taken in the shift register 1.

Next, the operation of the serial communication control device shown in FIG. 1 will be described. First, an operation for setting data in the command setting register 3 will be described.

FIG. 2 is a flowchart showing the processing operation of the control circuit 5 when setting data in the command setting register 3, and FIG. 3 is a timing chart at this time. Hereinafter, a process of setting data in the command setting register 3 by the control circuit 5 will be described with reference to FIGS.

First, when the chip select signal goes high during the period T1 in FIG. 3, the serial signal D is sent to the shift register 1 from the point in time when the clock signal CK is input.
Is taken in.

The control circuit 5 includes a shift register 1
Then, it is determined whether or not the data has been taken into all the registers (step S1). Specifically, when the fetch completion signal SG2 is output from the serial interface circuit 2, it is determined that the fetch of data into all the registers has been completed.

During the period from T2 to T6 in FIG. 3, since the data has not been completely taken into all the registers in the shift register 1, the process of step S1 is continuously performed.
In the period T7, data is taken into all the registers in the shift register 1, and the high-level fetch completion signal S
G2 is output, and the control circuit 5 analyzes the data taken into the shift register 1 (step S2).
2).

Next, the analyzed data is the serial signal D
It is determined whether or not the command is a command instructing to set a specific command included in the command setting register 3 in the command setting register 3 (step S3).

If it is determined that the analyzed data is not the above-mentioned instruction command, the processing from step S1 is repeated.
On the other hand, when it is determined that the analyzed data is the above-mentioned instruction command, it is determined whether or not the next data has been taken into all the registers in the shift register 1 (step S).
4).

In the period from T7 to T10 in FIG. 3, since the data has not been completely taken into all the registers in the shift register 1, the processing in step S4 is repeated. In the period T11, the serial interface circuit 2 notifies the control circuit 5 of a capture completion signal SG2 indicating that data capture to all registers has been completed.
In response to the notification, the control circuit 5 transmits a setting instruction signal SG3 for instructing the command setting register 3 to set a command to the command setting register 3 (Step S5). Upon receiving this signal, the command setting register 3
Sets a specific command taken into the shift register 1.

FIG. 4 is a flowchart showing the processing operation of the control circuit 5 when comparing commands by the comparison circuit 4, and FIG. 5 is a timing chart at this time. Hereinafter, FIG.
The process of comparing the command set in the command setting register 3 with the command included in the serial signal D will be described with reference to FIG.

First, the control circuit 5 determines whether or not data has been taken into all the registers in the shift register 1 (step S11). Here, as in step S1 of FIG. 2, the determination is made based on whether or not the capture completion signal SG2 has been output from the serial interface circuit 2.

If data fetching into all the registers in the shift register 1 is not completed, the process stays at step S1. When data fetching is completed, an output permission signal is transmitted to the comparing circuit 4. (Step S12).

When the output permission signal SG4 is output from the control circuit 5, the comparison circuit 4 compares the command set in the command setting register 3 with the command fetched into the shift register 1, and the two match. Then, a high-level trigger signal TRG is output.

As described above, according to the present embodiment, a specific command included in the serial signal D is set in the command setting register 3 while the serial signal D is stored in the shift register 1 in units of a plurality of bits. The command set in the fetch / command setting register 3 and the data fetched into the shift register 1 are compared by the comparison circuit 4, and if the comparison result matches, the trigger signal TRG is output. It is possible to reliably trigger a specific command. Therefore, even if a failure occurs such that a write command is issued at an unexpected timing, a trigger can be reliably applied at the time when the write command is issued, and measures against the failure are facilitated.

Further, by changing the command set in the control circuit 5, the type of command set in the command setting register 3 can be changed arbitrarily. In other words, the trigger target can be changed arbitrarily,
It is possible to trigger on any command included in the serial signal.

The trigger signal output from the comparison circuit 4 in FIG. 1 can be input to a trigger input terminal of a measuring instrument such as a logic analyzer to trigger the measuring instrument. This facilitates countermeasures against the failure of the serial communication device.

The control circuit 5 shown in FIG. 1 may be constituted by hardware or software. For example, when the processing shown in the figure performed by the control circuit 5 is configured by software, a program for performing this processing may be stored in a recording medium such as a floppy disk or a CD-ROM, and read and executed by a computer. The recording medium is not limited to a portable medium such as a magnetic disk or an optical disk, but may be a fixed recording medium such as a hard disk device or a memory.

The program for performing the processing shown in FIGS. 2 and 4 may be distributed via a communication line (including wireless communication) such as the Internet. Further, even if the program for performing the processing of FIGS. 2 and 4 is encrypted, modulated, or compressed, it may be distributed via a wired or wireless line such as the Internet, or stored in a recording medium and distributed. Good.

[0034]

As described above in detail, according to the present invention, a specific command included in a serial signal is held, and whether the same command as the held specific command is included in the serial signal is determined. The same command is included and a match signal is output, so that a specific command included in the serial signal can be reliably triggered, making it easy to take measures against failure of the serial communication device. Become.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a serial communication control device according to the present invention.

FIG. 2 is a flowchart showing a processing operation of a control circuit when setting data in a command setting register.

FIG. 3 is a timing chart when the processing of FIG. 2 is performed.

FIG. 4 is a flowchart showing a processing operation of a control circuit when comparing commands by a comparison circuit.

FIG. 5 is a timing chart when the processing of FIG. 4 is performed.

[Explanation of symbols]

 Reference Signs List 1 shift register 2 serial interface circuit 3 command setting register 4 comparison circuit 5 control circuit

Claims (6)

[Claims] 1. A data communication control device for transmitting a serial signal including a command, data and an address through a single signal line, comprising: command holding means for holding a specific command included in the serial signal; Command determining means for determining whether or not the same command as the specific command is included in the serial signal; and when the command determining means determines that the same command as the specific command is included in the serial signal, And a trigger output means for outputting a coincidence signal. And a command holding means for instructing the command holding means to hold the specific command when a predetermined instruction command is included in the serial signal. And holding the specific command included in the serial signal after receiving an instruction from the command holding instruction unit.
2. The data communication control device according to item 1. 3. A serial signal holding means for holding the serial signal in units of a plurality of bits, wherein the command holding means is held by the serial signal holding means after receiving an instruction from the command holding instruction means. Holding the specific command, wherein the command comparing unit compares the specific command held in the command holding unit with data held in the serial signal holding unit following the command. The data communication control device according to claim 2, wherein: 4. The apparatus according to claim 1, wherein the specific command is a command for instructing writing to a memory.
4. The data communication control device according to any one of claims 1 to 3. 5. A data communication control method for transmitting a serial signal including a command, data, and an address through a single signal line, wherein: a first step of holding a specific command included in the serial signal; A second step of determining whether the same command as the specific command is included in the serial signal; and the second step determines that the same command as the specific command is included in the serial signal. Then
A third step of outputting a coincidence signal. 6. A computer-readable recording medium on which a program for transmitting a serial signal including a command, data, and an address through one signal line is recorded, wherein a first command holding a specific command included in the serial signal is stored. A second procedure for determining whether or not the same command as the held specific command is included in the serial signal; and the same command as the specific command is stored in the serial signal by the second procedure. And a third step of outputting a coincidence signal when it is determined that the program is included in a computer-readable recording medium.