JPH0877032A - Logic analyzer - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a logic analyzer for performing a software test, and an object thereof is to trace the operation of a variable area such as a buffer. A signal search unit for extracting a data signal and an address signal between an MPU and a memory of a unit under test including an MPU and a memory for storing a program and data and supplying the signal and the logic signal to a logic analyzer is provided. The address of the pointer storage unit in which the buffer position in the memory of the device under test is set is set in the first register, the address signal from the signal search unit and the first register are compared by the first comparison means, and the match is detected. The data signal at that time is stored in the second register, and the second
The register contents are compared with the address signal by the second comparing means, and the software is traced by using the coincidence detection signal of the second comparing means as a trigger.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a logic analyzer for performing software testing. With the increasing functionality of electronic products in recent years, it is required that the functions be shared by software. Therefore, MPU (Micro Processo
r Unit) is used to develop software by microprograms. The software needs to be tested to make sure it works properly, which is why a logic analyzer is used.

[0002]

2. Description of the Related Art FIG. 5 is an explanatory view of a conventional example. In FIG. 5, reference numerals 50 to 53 form a unit under test, 50 is an MPU,
51 is a memory in which software (program and data) to be tested is stored, 52 is an address signal, 53
Is a data signal, 54 is a probe (or signal search unit) for extracting each signal from a terminal, 55 is a logic analyzer,
56 is a register, 57 is a comparison unit, and 58 is a trace unit.

The test operation according to FIG. 5 will be explained.
An address signal 52 and a data signal 53 connecting between 50 and the memory 51 are taken out by a probe 54 and taken into a logic analyzer 55. The address to be tested is registered in the register 5 in the logic analyzer 55 in advance.
Set to 6.

When the MPU 50 is operated, an address signal 52 and a data signal 53 are sequentially generated with the memory 51. The comparison unit 57 of the logic analyzer 55 is the register 5
When the address set to 6 and the address signal 52 are compared and coincident, the coincidence output is used as a trigger to drive the trace unit 58. When the trace unit 58 is driven, the address signal 52 and the data signal 53 at that time are fetched and stored. This trace operation can be executed until a predetermined number of data thereafter or until a certain condition is satisfied.

[0005]

In the above conventional logic analyzer, since the trigger address is directly specified, it is possible to trace a fixed area, but the start address of the area to be traced like a buffer. When fluctuates, there is a problem that the address that becomes the trigger cannot be specified.

An object of the present invention is to provide a logic analyzer for performing a software test capable of tracing the operation of a variable area such as a buffer.

[0007]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, 1 is a logic analyzer, 1
0 is a first register for storing the pointer storage position, 11 is a first comparing means, 12 is a second register, 13 is a second comparing means, 14 is a third register, 2 is a data signal line 2a, an address signal line 2b, A signal line composed of the read / write signal line 2c, 3 is a portion to be tested, 4 is an MPU, 5 is a memory in which software to be tested is stored, and 5a is a memory 5 in which the start address of a buffer used by the software is set. A pointer storage unit 5b provided therein is a buffer. 6 is a data signal line 6a between the MPU 4 and the memory 5,
A signal search unit such as a probe for extracting the signal line 6 between the MPU 4 and the memory 5 and inputting the signal line 6 between the MPU 4 and the memory 5 to the signal line 7 composed of the address signal line 6b and the read / write signal line 6c. is there.

According to the present invention, the position where a pointer of a variable area such as a buffer is stored in software is monitored, and when the pointer is accessed, the address set therein is extracted, and thereafter the access to that address occurs. Then, the buffer area is tested by tracing.

[0009]

In FIG. 1, when the MPU 4 of the unit under test 3 accesses the memory 5 through the signal line 6 and uses the buffer 5b, which is an area that is changed by software, its head address is set in the pointer storage unit 5a. To be done. On the other hand, an address indicating the position of the pointer storage unit 5a of the memory 5 is set in the first register 10 of the logic analyzer 1. When the MPU 4 of the unit under test 3 executes the software of the memory 5 in this state, each signal on the signal line 6 between the MPU 4 and the memory 5 is input from the signal searching unit 7 to the signal line 2.

The address signal line 2b of the signal line 2 is compared with the address in the first register 10 in the first comparing means 11, and if a match is found, it is found that the MPU 4 has accessed the pointer storage 5a, and at that time the data signal line Since the pointer indicating the position of the buffer 5b stored in the pointer storage unit 5a is output from the memory 5 onto the 2a, the first
The data indicating the pointer is fetched from the data signal line 2a by the comparison and coincidence output of the comparison means 11, and the second register 12 is obtained.
Set to. After that, the second comparison means 13 inputs the pointer set in the second register 12 and the address generated from the MPU 4 from the address signal line 2b for comparison.

When the coincidence output is generated by the second comparing means 13, it is found that the MPU 4 has accessed the buffer 5b of the memory 5 at that time, and the trace is started by this coincidence output. The trace captures and displays or records each signal of the data signal line 2a and the address signal line 2b by a trace unit (not shown).

When the type of the read operation or the write operation to be traced is designated in advance in the third register 14, the second comparing means 13 not only compares the addresses but also the type set in the third register 14. By comparing the read / write signal lines 2c, the trace can be started when the address matches and the operation type matches. Also, another register is provided, and the length of the data to be traced (the number of data to be traced after a match is set) is set, and the trace is terminated when that number is reached. be able to.

[0013]

FIG. 2 is a block diagram of the first embodiment. In FIG. 2, 1 is a logic analyzer, 1a is an information processing unit for controlling each unit, 1b to 1e correspond to 10 to 13 in FIG. 1, 1b is a first register, 1c is a first comparison circuit, and 1d is a first register. 2 registers, 1e is a second comparison circuit, 1f is a trace part, 1g is a display part, and 2 is a signal line including a data signal line 2a and an address signal line 2b. The configuration of the unit under test 3 is the same as that of FIG.
And the like, 6 is a signal line composed of a data signal line 6a and an address signal line 6b, and 7 is a data signal line 6a and an address signal line 6b of the part under test, which correspond to the logic analyzer 1. A signal search unit for inputting to each of the signal lines 2a and 2b, 7a is a data signal search unit, 7b
Is an address signal search unit.

Explaining the operation of the first embodiment, the information processing unit 1a gives the first register 1b an address indicating the storage position of a pointer indicating the position of the buffer used by the software stored in the memory 5 in advance (above). (See FIG. 1).

In this state, when the software of the memory 5 is executed by the MPU 4 of the unit under test 3, the first comparison circuit 1
In c, the address of the address signal line 2b fetched by the signal search unit 7 is fetched and compared with the set address of the first register 1b, and if a match is detected, the detection output indicates the data signal line for the second register 1d at that time. Control is performed to store the data 2a (a pointer that points to the beginning position of the buffer area). After that, when the buffer is accessed by executing software, the address stored in the second register 1d and the address of the address signal line 2b are matched by the second comparison circuit 1e, and the trace detection section 1f is driven by the match detection output. .

As a result, the trace unit 1f starts tracing the software (data of the data signal line 2a and the address signal line 2b), and displays the trace data on the display unit 1g. The information processing unit 1a controls the operations of the trace unit 1f and the display unit 1g.

FIG. 3 is a block diagram of the second embodiment. Figure 2 above
In the case of the first embodiment shown in (1), the MPU 4 accesses the memory 5 (regardless of read or write) and the trace is started when the address matches the content of the second register 1d. In this case, read or write is designated in advance as a condition for starting the trace, and the trace unit is triggered only when the designated operation is performed.

In FIG. 3, reference numerals 1a to 1g in the logic analyzer 1 are the same devices or circuits as those shown in FIG. 2, and reference numeral 1h is a designation signal indicating any type of read / write from the information processing unit 1a. And read / write signal line 2c
Read / write signal detection unit for detecting coincidence of signals
i is an AND circuit. Further, in the unit under test 3, 4 to 7 are the same devices or circuits as those shown in FIG. 2, but 6c is a read / write signal line, and 7c is a read / write signal searching unit.

In the operation of the second embodiment shown in FIG. 3, the information processing section 1a first sets in the first register 1b an address indicating the storage position of the pointer indicating the position of the buffer used by the software stored in the memory 5. At the same time, a signal designating either read or write is supplied to the read / write signal detector 1h as a condition for starting the trace.

In this state, when the software of the memory 5 is executed by the MPU 4 of the unit under test 3, the above-mentioned first embodiment
The same operation as in (FIG. 2) is performed, the address of the address signal line 2b is compared with the set address of the first register 1b by the first comparison circuit 1c, and if a match is detected, the data signal is sent to the second register 1d. Store the data for line 2a. After this,
Further, the software is executed, the address stored in the second register 1d is compared with the address of the address signal line 2b by the second comparison circuit 1e, and when the MPU 4 accesses the buffer, a coincidence output is generated.

This coincidence output is output to the AND circuit 1i. At this time, the read / write signal detection unit 1h determines whether or not a signal of a designated type (read or write) has occurred on the read / write signal line 2c, and if so, outputs a detection signal to the AND circuit 1i. To do. The AND circuit 1i sets the trace unit 1f to the trigger enable state when both the coincidence output of the second comparison circuit 1e and the detection output of the read / write signal detection unit 1h occur. According to the second embodiment, the trace can be started by the writing to the buffer area and the reading from the buffer area as a trigger.

FIG. 4 is a block diagram of the third embodiment. Figure 2 above
In the case of the first embodiment of FIG. 3 and the second embodiment of FIG. 3, the MPU 4 accesses the memory 5 and its address is the second register 1d.
If it matches the contents of the above, or if the match of the address and the type of access match the specified type, the movement of the software after that is traced. In the third embodiment, the address where the match is detected. The area that continues from is traced by the data of the set length.

In FIG. 4, reference numerals 1a to 1g in the logic analyzer 1 are the same devices or circuits as those shown in FIG. 2, and 1j is a data length (L) designated by the information processing unit 1a. When the address of the second register 1d is generated, a trace data length storage register having a function of generating an address obtained by adding the address and the data length, 1k is a third comparison circuit, and 1m is a logic circuit.
Further, 4 to 7 of the unit under test 3 are the same devices or circuits as the reference numerals in FIG.

The operation of the third embodiment shown in FIG. 4 is similar to that of the first embodiment. First, the information processing section 1a transfers to the first register 1b,
The address indicating the storage position of the pointer indicating the position of the buffer used by the software stored in the memory 5 is set. In addition, according to the third embodiment, the data length (L) to be traced is designated from the information processing unit 1a to the trace data length storage register 1j.

In this state, the MPU 4 of the unit under test 3 executes the software of the memory 5. First comparison circuit 1c
Is the address signal line 2b extracted by the signal search unit 7.
Address of the first register 1b is compared with the set address of the first register 1b, and when a match is detected, the detection output outputs the data on the data signal line 2a at that time to the second register 1d (representing a pointer indicating the start position of the buffer). , Address P) is stored. When this address is supplied to the trace data length storage register 1j, the data length L designated by the information processing unit 1a and the address P are added to generate an address (P + L).

Thereafter, when software is further executed to access the buffer, the address stored in the second register 1d by the second comparison circuit 1e matches the address of the address signal line 2b. This coincidence detection output is supplied to the logic circuit 1m. The logic circuit 1m is the second comparison circuit 1
When the output of e is generated, an instruction to execute the trace operation is generated to the trace unit 1f. In addition, the second comparison circuit 1
The third comparison circuit 1k becomes active by the coincidence output of e. After that, the trace unit 1f executes a software trace.

After that, when the address of the address signal line 2b increases and coincides with the address (P + L) of the trace data length storage register 1j, the coincidence output is generated from the third comparison circuit 1k. When this coincidence output is supplied to the logic circuit 1m, the logic circuit 1m stops instructing the trace unit 1f to execute the trace operation accordingly. Therefore, the trace unit 1f is software (data and address) from when the match detection output is generated by the second comparison circuit 1e (when the buffer area is accessed) to when the match detection output is generated by the third comparison circuit 1k. The trace operation will be executed.

According to the third embodiment, the area of consecutive addresses from the desired address can be traced by the set length. Each of the above Examples 1 to 3
In the above, the traced data is displayed on the display unit 1g, but the display unit can be replaced with a RAM or an external storage device (flexible disk device or the like), and the trace data can be stored there.

In each of the above-described first to third embodiments, the logic analyzer 1 is constructed as a device different from the device under test 3, but the logic analyzer 1 and the device under test 3 are incorporated as a single device. You may do it.

[0030]

According to the present invention, a variable area such as a buffer can be traced, and the operation of the buffer area can be confirmed in real time in software operating on the MPU, which improves the function of the logic analyzer. Can be realized.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of a first embodiment.

FIG. 3 is a configuration diagram of a second embodiment.

FIG. 4 is a configuration diagram of a third embodiment.

FIG. 5 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 1 Logic Analyzer 10 1st Register 11 1st Comparison Means 12 2nd Register 13 2nd Comparison Means 14 3rd Register 2 Signal Line 3 Test Part 4 MPU 5 Memory 5a Pointer Storage 5b Buffer 6 Signal Line 7 Signal Search Unit

Claims (4)

[Claims] 1. A logic analyzer for performing a software test, in which a data signal and an address signal between an MPU and a memory of a unit under test including an MPU and a memory in which a program and data are stored are extracted and supplied to the logic analyzer. A first register in which the address of the pointer storage unit in which the buffer position in the memory of the unit under test is set, the address signal from the signal search unit, and the A first comparing means for comparing one register, a second register for storing the data signal at that time by the match detection of the first comparing means, and a second register for detecting a match between the content of the second register and the address signal. Comparing means is provided, and the software is traced by using the coincidence detection signal of the second comparing means as a trigger. A logic analyzer characterized by. 2. The read / write signal search unit for extracting a read / write signal according to claim 1, wherein the logic analyzer includes a third register for setting read or write as a trace start condition in advance. A logic which traces software by using the coincidence detection of the contents of the second register and the address signal and the coincidence detection of the read / write signal from the read / write signal searching unit and the third register as a trigger. analyzer. 3. The logic analyzer according to claim 1 or 2, wherein the trace data length storage register for storing data corresponding to a data length to be traced and the contents of the trace data length storage register and the address signal are matched. A logic analyzer, comprising: a third comparing means for detecting, wherein the trace section starts the tracing by the coincidence output of the second comparing means, and ends the tracing by the coincidence output of the third comparing means. 4. The data according to claim 1, wherein the data input to the trace unit is output to a display unit or a memory,
A logic analyzer that displays or records trace contents.