JP2000305532A - Image processing device - Google Patents

Abstract

[PROBLEMS] To provide an image processing apparatus using a liquid crystal panel as an optical shutter and capable of displaying an image with uniform brightness without luminance unevenness or color unevenness. SOLUTION: Selectors 21 and 22 input a horizontal offset value by a higher 3 bit signal of a horizontal count value HC and a vertical count value VC respectively derived from a horizontal _count value input terminal T _hc and a vertical _count value input terminal T _vc. Horizontal offset value Hi and vertical offset value input terminal T supplied from terminal T _hof
The vertical offset value Vj supplied from the _vof is selected, the adder 23 adds both offset values, and the added value is output to the adder 8 by the offset generation circuit 2 as the offset signal OF to provide multi-gradation display. The display video signal ID is added to the dither pattern signal DP output from the dither pattern generation circuit 1 to be used, output to the adder 9, and added to the video signal IM supplied to the video signal input terminal _Tim.
Is output from the display video signal output terminal _Tid .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for converting an image for a personal computer (hereinafter abbreviated as a personal computer) or an image for a television to an image on a liquid crystal display device such as a liquid crystal image projection device or a liquid crystal rear image projection TV. The present invention relates to an image processing device used for a computer.

[0002]

2. Description of the Related Art Liquid crystal image projection apparatus and liquid crystal rear image projection T
In an image display device such as V, when displaying a multi-gradation image on the screen, the following two methods are generally used. That is, one is a frame rate control method.
trol; hereinafter, abbreviated as FRC), and the other is a dither method. The FRC is a method of displaying a two-level halftone by switching the display gradation of each pixel for each frame. In addition, the dither method is a method in which a plurality of pixel groups are grouped together, and a pseudo random number is superimposed on the display gradation of each pixel and quantized to increase the number of gradations when displaying as one unit image. By combining these FRC and dither method,
A technique for spatially controlling gradation is described in, for example, “Digital Signal Processing of Images” (Takahiko Fukibuki, Nikkan Kogyo Shimbun, p.23).
6,237, May 1981) or JP-A-5-1
No. 08033 discloses this.

FIG. 9 is a circuit diagram showing a halftone image processing circuit according to a conventional example. Video signal IM inputted from video signal input terminal T _im, the display gradation is increased by being added to the dither pattern signal DP created in the adder 9 by a dither pattern generating circuit 1, the display image as the display image signal The signal is output to the signal output terminal _Tid .

In the dither pattern generation circuit 1, the least significant bit of the horizontal count value HC synchronized with the video signal IM, input from the horizontal _count value input terminal _Thc , in order to perform image processing by FRC and dither on the video signal IM. And the least significant bit value of the vertical _count value VC input from the vertical _count value input terminal _Tvc and the second least significant bit value of the frame count value FC input from the frame _count value input terminal Tfc are exclusive OR gates 11, A logical operation is performed in steps 12 and 13 to generate a dither pattern signal DP whose pattern is inverted at the frame period.

The dither pattern signal DP generated by the dither pattern generation circuit 1 is obtained by using pixel data of (2 dots in the horizontal direction × 2 lines in the vertical direction) as one image unit data.
Horizontally with respect to the video signal IM inputted from video signal input terminal T _im, vertical, depending on the timing of each of the frame period, when the second least significant bit value = 0 of the frame count, 0,3 ( (1st line) 2,1 (2nd line) When the second least significant bit value of the frame count value = 1, it changes to 3,0 (1st line) 1,2 (2nd line). The reason that the dither pattern signal DP is inverted every time the second least significant bit of the frame count value FC changes to (0, 1) is a wisdom for extending the service life of the liquid crystal panel. In general, one cycle is performed every four frames.

FIG. 10 is a characteristic diagram showing image data conversion characteristics for multi-tone display by the dither method. In the figure, (a) shows an output gray scale obtained by adding the dither pattern signal DP of the even-numbered line to the input video signal IM of 1 to 16 gray scales,
(B) shows the output gradation by the dither pattern signal DP of the odd line. The output signal shown in FIG.
An example in which the gray level is 2 bits smaller than the number of gray levels of the input video signal IM is shown. In addition to the input video signal IM (black diamond) and the dither pattern signal DP (▲, ■),
The average gradation (階 調) of the output signal when the added dither pattern signal DP repeats inversion due to the cycle change of the frame count value FC is also shown.

As described above, by inverting the dither pattern signal DP at the frame period, focusing on the same pixel,
(0, 3) or (2, 1) dither pattern signal DP
Can be perceived by human eyes as a signal having a luminance level of 1.5 corresponding to the intermediate luminance on average.
That is, the output gradation is (0.5), (1 + 0.5), (2
+0.5) and (3 + 0.5) below the minimum value level can be displayed. In this way, the display video signal I that can display substantially more gray scales than the gray scale at which the input video signal IM can be expressed at the time of input.
D and output.

[0008]

The above-described image display apparatus according to the prior art is a liquid crystal image projection apparatus for displaying a video display signal ID by functioning as a shutter for transmitting or blocking light through a liquid crystal panel. Is used as a main part of the apparatus. By the way, when the light from the light source is reflected by the reflecting mirror, there is a characteristic that the amount of light and the wavelength of the light change depending on the angle at which the light enters the liquid crystal panel. Therefore, at the time when the video display signal ID is output from the video signal processing circuit system, even if the signals have the same amplitude, the display video is determined by the respective display positions on the right, center, left, upper and lower sides of the display screen. However, there is a problem that the brightness difference and the brightness are not uniform. This is a phenomenon generally referred to as luminance unevenness or color unevenness, and has always been a problem to be faced when developing a product of a liquid crystal image projection device or a liquid crystal rear image projection TV.

SUMMARY OF THE INVENTION The present invention has been made to solve such problems in the prior art, and enables an image display apparatus using a liquid crystal panel as an optical shutter to display an image with uniform brightness without luminance unevenness or color unevenness. It is an object to provide a simple image processing apparatus.

[0010]

In order to solve the above-mentioned problems, the present invention divides a display screen into a plurality of regions in the horizontal and vertical directions, and adds a preset offset value for each region to display images. It is preferable that the additional data of the dither pattern in which irregular additional data is assigned to each pixel of the unit pixel group formed by arbitrarily combining a plurality of pixels is used for each pixel in the unit pixel group. This is obtained by performing an additional data addition process to be added to a video signal.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is an image processing circuit diagram according to a first embodiment of the present invention. In the figure, reference numeral 2 denotes an offset generating circuit for generating an offset signal OF having a preset offset value to be added to the video signal IM for each unit area obtained by dividing the display screen into a plurality of units, and 21 and 22 each represent a plurality of horizontal offsets. A selector for selecting one value from the value Hi and the vertical offset value Vj;
An adder for adding the horizontal offset value Hi and the vertical offset value Vj output from 22; T _hof and T _vof are a horizontal offset value input terminal to which a plurality of horizontal offset values Hi and a vertical offset value Vj are input, and a vertical offset, respectively. This is a value input terminal. Note that the same reference numerals are given to portions that are the same as or can be regarded as the same as those in the conventional example, and redundant description thereof will be omitted.

Next, the operation of this embodiment will be described. The dither pattern generation circuit 1 has a horizontal _count value input terminal T _hc , a vertical _count value input terminal T _vc, and a frame _count value input terminal T
The least significant bit value and the second least significant bit value of the count values in the horizontal direction, the vertical direction, and the frame period, which are input from _fc and are synchronized with the video signal IM, are input to generate the dither pattern signal DP. Since the operation of generating the dither pattern signal DP of the dither pattern generation circuit 1 is not different from that of the conventional example, a duplicate description will be omitted.

The offset generation circuit 2 has a display video signal ID
Is generated to generate an offset signal OF having a preset offset value, which is added to the input video signal IM for each unit area corresponding to the display position on the display screen displaying. Selector 21
H0, which gives a predetermined offset value corresponding to the horizontal display position, which is output from a picture quality adjustment microcomputer or the like (not shown), to eight horizontal offset value input terminals T _hof .
, H7 are input. Similarly, the eight vertical offset value input terminals T of the selector 22
_{In vof} , V0, V1, which give a predetermined offset value corresponding to the vertical display position output from a microcomputer or the like.
, V7 are input. And
The selectors 21 and 22 have horizontal _count value input terminals T _hc respectively.
The upper three bits of the horizontal count value HC and the vertical count value VC input to the vertical _count value input terminal _Tvc are input as control signals.

The selector 21 is controlled by the upper 3 bits of the horizontal count value HC supplied to the horizontal _count value input terminal T _hc , and controls the eight horizontal offset values Hi (H) input to the horizontal offset value input terminal T _hof. i = 0, ..., 7)
And select one. In this embodiment, the upper three bits of the horizontal count value HC are supplied to the control terminal of the selector 21.
As the bits change from the minimum value to the maximum value, the offset values output from the selector 21 are H0, H1, H
,..., H7 are sequentially switched. This selector 2
By the switching operation of 1, the selected offset values H0, H1, H2,..., H7 are supplied to the adder 23 for each of the regions obtained by dividing the display image into eight at equal intervals in the horizontal direction.

The operation of the selector 22 is the same as that of the selector 21. The switching operation of the selector 22 to which the upper 3 bits of the vertical count value VC are supplied as a control signal causes the displayed images to be equally spaced in the vertical direction. The vertical offset value Vj (j = 0,...,.
7) is supplied to the adder 23.

The adder 23 adds the horizontal offset value Hi output from the selector 21 and the vertical offset value Vj output from the selector 22 and generates an adder 8 as an offset signal OF.
Output to The adder 8 adds the dither pattern signal DP generated by the dither pattern generation circuit 1 and the offset signal OF output from the adder 23, and outputs the result to the adder 9.
The adder 9 adds the output from the video signal IM an adder 8 which is supplied from the video signal input terminal T _im (dither pattern signal DP + offset signal OF), the display image signal to the display video signal output terminal T _id Output as ID.

FIG. 2 shows specific examples of the horizontal offset value Hi, the vertical offset value Vj output from the selectors 21 and 22 and the value of the offset signal OF generated by the offset generating circuit 2 for each area of the display screen. FIG.
Are areas A1, A2, A3 obtained by dividing the horizontal direction of the display screen into eight parts.
, A8 output from the selector 21 at each of the display positions is represented by a horizontal offset value Hi, (b) which is a selector at each of the display positions B1, B2, B3,. 22 output from the vertical offset value V
j, (c) are the horizontal offset values Hi output from the adder 23 at the respective display positions of the areas A ₁₁ , A ₁₂ , A ₁₃ ,..., A _{88 obtained} by dividing the display screen into (8 × 8) = 64. And the offset value (Hi + V) to which the vertical offset value Vj is added.
j). Note that the specific numerical values of the horizontal offset value Hi and the vertical offset value Vj are merely examples, and the numerical values have no special significance.

FIG. 3 is an explanatory diagram showing the value of the dither pattern signal DP generated by the dither pattern generation circuit 1 in correspondence with each pixel on the display screen, and FIG. 4 is output from the adder 8 [the dither pattern signal DP + FIG. 3 is an explanatory diagram showing values of an offset signal OF] corresponding to each pixel on a display screen.
4, the value of (a) is in each pixel in the area A ₁₁ [dither pattern signal DP + offset signal OF],
(B) shows the value of [dither pattern signal DP + offset signal OF] of each pixel in area A ₁₄ , and (c) shows area A ₁₇
Indicates the value of [dither pattern signal DP + offset signal OF] of each pixel in FIG.

The dither pattern signal DP shown in FIG. 3 is an example of the above-described dither pattern when (2 horizontal dots × 2 vertical lines) is one block. As described above, the value of the offset signal OF added to the dither pattern signal DP shown in FIGS. 4A, 4B, and 4C is the area A ₁₁ and the area A shown in FIG. _Since they are the values of the offset signal OF of ₁₄ and the area A ₁₇ , these values are OF = 40, 20, and 10, respectively. As is apparent from FIG. 2, in this embodiment, the areas A ₁₈ , A ₂₇ , A ₃₆ ,..., A ₈₁ on the diagonal connecting the upper right corner and the lower left corner of the display screen.
The image signal IM of the pixel is unadjusted, and the gradient of the pixel located in a region away from the diagonal line toward the upper left corner is increased, and conversely, at a position away from the diagonal line toward the lower right corner. The gradation is adjusted so that the gradation becomes lower for a certain area pixel.

As described above, in the present embodiment, a signal for performing the gradation adjustment corresponding to the display position of the display screen is added to the video signal IM at the same time as the multi-gradation by the conventionally used dither processing. For example, even when the light source is arranged at a position near the lower right corner, a uniform image display in which the brightness unevenness and color unevenness of the liquid crystal display device are corrected can be realized.

In this embodiment, an example has been described in which pixel data (3, 2, 1, 0) of (horizontal 2 dots × vertical 2 lines) is generated as a group to generate a dither pattern signal DP. The present invention is not limited to this, and the size of one group and the combination of numerical values can be arbitrarily set. Also,
Although the dither pattern signal DP is created using a combination of exclusive OR gates, any generation circuit can be used.

Further, it is not always necessary to divide the positions on the display screen at which the display gradation adjustment is performed at equal intervals, and it is rather impossible to appropriately deal with the light reflection and light transmission characteristics of the reflecting mirror and the liquid crystal panel. In some cases, it is better to divide at equal intervals. In such a case, the horizontal _count value HC and the vertical count value VC input to the horizontal _count value input terminal _Thc and the vertical _count value input terminal _Tvc , respectively, are decoded, and the selector 2
What is necessary is just to set the control signal input to 1 and the selector 22 to a value that can be divided into regions at a desired position. Further, the horizontal offset value Hi and the vertical offset value Vj input to the horizontal offset value input terminal T _hof and the vertical offset value input terminal T _vof of the selector 21 and the selector 22 need not be limited to eight inputs, respectively. To the number of horizontal pixels of the display panel] (for example, 1280 and 1024 for an SXGA panel, 10 for an XGA panel)
24 and 768).

FIG. 5 is an image processing circuit diagram according to a second embodiment of the present invention. In the figure, reference numeral 3 denotes a horizontal offset for selecting and outputting a horizontal offset value Hi for each of the areas Ai obtained by dividing the display image into eight parts in accordance with the horizontal count value HC supplied to the horizontal _count value input terminal _Thc. The generating circuit 4 selects and outputs a vertical offset value Vj for each of the areas Bi obtained by dividing the display image into eight in accordance with the vertical count value VC input to the vertical _count value input terminal _Tvc. The circuit 7 is an adder for adding the horizontal offset value Hi supplied from the horizontal offset generation circuit 3 and the vertical offset value Vj supplied from the vertical offset generation circuit 4.

, 318 and 411, 412,..., 418 indicate that the result of decoding the horizontal count value HC and the vertical count value VC is "0",
.., 328 and 421, 422,..., 428 are decoding circuits for outputting high-level signals, respectively. …, 318, 411, 412,
,..., AND AND AND GATE AND AND GATE 33, 43, ANDing 418 with horizontal offset value Hi and vertical offset value Vj
Are AND gates 321, 322,..., 328, respectively.
AND gates 421, 422,..., 428. Note that the same reference numerals are given to portions which are the same as or can be regarded as the same as those of the first embodiment, and redundant description thereof will be omitted. The same applies to the following description of the embodiments.

Next, the operation of this embodiment will be described only with respect to differences from the first embodiment. , 318, 411, 412,...
, 418 respectively decode the horizontal count value HC and the vertical count value VC, and the decoded results are “0”,
If it is “1”,..., “7”, a high level signal is output.
, 328, 421, 422,..., 428.

AND gates 321, 322,..., 32
., 428 are decoding circuits 311, 312,..., 318, 411, 412, respectively.
When the output of 418 is high level, the horizontal offset value input terminal T _hof and the vertical offset value input terminal T
_The horizontal offset value Hi and the vertical offset value Vj supplied by the microcomputer or the like from _vof are output as they are. When the output is at a low level, the horizontal offset value (vertical offset value) = 0 is output. The OR gates 33, 43 take the logical sum of the AND gates 321, 322,..., 328 and the AND gates 421, 422,. The adder 7 adds the horizontal offset value Hi output from the horizontal offset generation circuit 3 and the vertical offset value Vj output from the vertical offset generation circuit 4 and supplies the result to the adder 8 as an offset signal OF.

In the present embodiment, the intervals of eight divisions for changing the horizontal and vertical offset values of the display screen are determined by the decoding circuits 311, 312,.
.., 418 will be based on the decrypted result,
The division intervals of the display screen are not always equal, and can be set arbitrarily. Further, the number of divisions of the display screen can be set arbitrarily as in the case of the first embodiment.

FIG. 6 is an image processing circuit diagram according to a third embodiment of the present invention. 5, reference numeral 5 denotes an offset generating circuit for generating an offset signal OF for giving an offset value according to the display position in the horizontal and vertical directions of the display screen, and 51, 52,..., 58 denote horizontal and vertical directions of the display screen. Selector 59 for selectively outputting the offset value in the two-dimensional divided area in the direction in accordance with the horizontal position;
A selector T for selecting and outputting the offset value selected by each of 1, 52,..., 58 according to its vertical position;
_off sets the display screen horizontally and vertically by 8
Offset values (i, j) when divided (= 64 divided);
(I = 0,..., 7) and (j = 0,..., 7) are input offset value input terminals.

The selectors 51, 52,..., 58 are the upper three of the horizontal count value HC supplied from the horizontal _count value input terminal _Thc.
According to the value of the bit, the two-dimensional (8 ×
8) is set corresponding to the divided areas, is supplied to the offset value input terminal T _off, 8 pieces of offset values each (j, 0), (k , 1), (l, 2), ......, ( q,
7) Any one of them is selected and output. The selector 59 selects the selectors 51 and 51 according to the value of the upper three bits of the vertical _count value VC supplied from the vertical _count value input terminal _Tvc .
, 58, respectively, the offset values (j, 0), (k, 1), (l, 2),.
7) One of them is selected and output.

In this embodiment, as described above, the two-dimensional (8 × 8) of the display screen supplied to the offset value input terminal _Toff is supplied.
8) The offset value (i, j) set corresponding to the divided area A _ij can be arbitrarily set in accordance with, for example, a luminance difference or a non-uniform brightness caused by a display position of the liquid crystal screen. More precise brightness adjustment can be performed according to the display position of. FIG. 7 is an explanatory diagram showing a specific example of the offset value (i, j) of each divided area A _ij when the display screen is divided into (8 × 8). In the specific example shown in the figure, the value of the offset value (i, j) of each divided area A _ij happens to be the same value as the offset value (Hi + Vj) output from the adder 23 of the first embodiment. However, the numerical value can be set arbitrarily as described above. Also, the number of divisions of the display screen and the interval between divisions can be arbitrarily determined.

FIG. 8 is an image processing circuit diagram according to a fourth embodiment of the present invention. In the figure, reference numeral 6 denotes a ROM (ROM) for storing an offset value (i, j) set corresponding to a two-dimensional (8 × 8) divided area A _ij of the display screen, and _Tpt is stored in the ROM 6. This is a page switching input terminal for inputting a page switching signal for switching a page having an offset value. The page switching signal input to the page switching input terminal _Tpt is supplied from a microcomputer or the like. The ROM 6 stores in advance offset values corresponding to two-dimensional coordinate positions in the horizontal and vertical directions of the display screen. As the offset value, a set of 64 offset values of a plurality of patterns is stored for each page.

The upper 3 bits of the vertical _count value VC input to the vertical _count value input terminal _Tvc are input to the upper address terminal of the ROM 6, and the upper 3 bits of the horizontal _count value HC input to the horizontal _count value input terminal _Thc. To the lower address, respectively, as a readout signal, the offset signal OF corresponding to the two-dimensional coordinates in the divided area A _ij obtained by dividing the display image in the horizontal direction and the vertical direction (8 × 8) to the adder 8 Can be output. When the brightness of a different pattern is adjusted on the display screen, a set of offset values of a different pattern is read out from ROM 6 by switching and inputting a page switching signal input to a page switching input terminal _Tpt . It can be output as OF.

In this embodiment, the ROM 6 is configured to store an offset value of (8 × 8) words. However, the present invention is not limited to this, and theoretically (0 to the number of horizontal display pixels) X (0 to the number of vertical display pixels) can be stored. Further, for example, 1280 × 1024 words are stored in the case of the SXGA panel, and 1024 × 768 words are stored in the case of the XGA panel. A large capacity one may be used. In addition, the control of the ROM address includes the upper three values of the horizontal count value HC and the vertical count value VC.
Although the configuration uses bit data, this is merely an example, and any division method for dividing the display screen in the horizontal direction and the vertical direction can be adopted. Furthermore, when the number of bits of the video signal IM is, for example, n, the number of pages of the ROM 6 in which the offset value is recorded can be stored up to 2n pages.

As described above, in the above embodiment, the video signal I
In addition to multi-gradation by dither processing as the halftone image processing of M, the offset value OF corresponding to the coordinate position of the display screen
Can be added to the video signal IM and output.
An image having uniform brightness can be displayed by correcting unevenness in brightness and unevenness in color of the liquid crystal display device.

[0036]

As described above, according to the first aspect of the present invention, the display screen is divided into a plurality of regions in the horizontal and vertical directions, and a preset offset value is added for each of the regions. Even if the amount of light or the wavelength of the light changes due to the difference in the incident angle of the irradiating light at each display position, the density of the liquid crystal display device is uniform without any brightness unevenness or color unevenness with respect to the same gradation image. Images can be displayed.

According to the second aspect of the present invention, additional data of a dither pattern in which irregular additional data is assigned to each pixel of a unit pixel group formed by arbitrarily combining a plurality of pixels is added to each unit pixel group. Since the additional data addition processing for adding to the video signal of each pixel has been performed, it is possible to display an image with uniform density for an image of the same gradation, in addition to the multi-gradation display required for the liquid crystal display device. .

According to the third aspect of the present invention, the offset value is selected from a plurality of preset horizontal offset values of the display screen and a plurality of vertical offset values of the display screen in the vertical direction. Since the horizontal offset value and vertical offset value are added, it is necessary to input a small number of offset values and display an image with a uniform density for an image of the same gradation using an image processing circuit with a simple configuration. Can be.

[Brief description of the drawings]

FIG. 1 is an image processing circuit diagram according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a specific example of a value of an offset signal in each region of a display screen in the first embodiment.

FIG. 3 is an explanatory diagram showing values of a dither pattern signal corresponding to each pixel on a display screen.

FIG. 4 is an explanatory diagram showing a value of [dither pattern signal + offset signal] corresponding to each pixel on a display screen.

FIG. 5 is an image processing circuit diagram according to a second embodiment of the present invention.

FIG. 6 is an image processing circuit diagram according to a third embodiment of the present invention.

FIG. 7 is an explanatory diagram showing a specific example of an offset value of each divided area when the display screen is divided into (8 × 8) in the third embodiment.

FIG. 8 is an image processing circuit diagram according to a fourth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a halftone image processing circuit according to a conventional example.

FIG. 10 is a characteristic diagram showing image data conversion characteristics of a multi-gradation display by a dither method in a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Dither pattern generation circuit 2, 5 Offset generation circuit 3 Horizontal offset generation circuit 4 Vertical offset generation circuit 6 ROM (ROM) 7, 8, 9, 23 Adder 21, 22, 51-59 Selector 11, 12, 13 Exclusive OR gate 311～318,411～418 decode circuit T _im video signal input terminal T _id display video signal output terminal T _hc horizontal count value input terminal T _vc vertical count input terminal T _fc frame count input terminal T _hof horizontal offset value Input terminal T _vof vertical offset value input terminal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 642 G09G 3/20 642B (72) Inventor Katsunobu Kimura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture (72) Inventor Haruki Takada 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term (reference) 2H093 NA52 NC13 NC27 NC50 NC90 ND06 ND09 NG02 NH18 5C006 AA03 AA17 AA22 AC02 AC24 AF42 AF43 AF46 BB11 BC03 BC12 BC16 BC22 BC23 BF24 BF26 BF28 FA22 5C080 AA10 BB06 CC03 DD05 DD30 EE29 FF09 GG02 GG09 JJ01 JJ02 JJ03 JJ05

Claims (3)

[Claims] An image processing apparatus that performs image processing on a sampled and quantized digital video signal and outputs the processed video signal as a display video signal of a liquid crystal display device, wherein a display screen is divided into a plurality of regions in horizontal and vertical directions. An image display device wherein the display video signal is obtained by adding an offset value preset for each area. 2. The additional data of a dither pattern, in which irregular additional data is assigned to each pixel of a unit pixel group formed by arbitrarily combining a plurality of pixels, into a video signal of each pixel for each unit pixel group. 2. The image processing apparatus according to claim 1, wherein an additional data addition process for adding is performed. 3. The method according to claim 1, wherein the offset value is a horizontal offset value selected from a plurality of preset horizontal offset values of the display screen and a plurality of vertical offset values of the display screen in the vertical direction. 2. The image processing apparatus according to claim 1, wherein the offset value and the offset value are added.