JP2000305802A - In-circuit emulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an emulation CPU from running away in the clock switching by integrating a user reset mask signal and a user power supply mask signal and resetting a simulation CPU. SOLUTION: A user reset signal URESET from a user is masked by a 1st mask circuit 8 according to a supervisor state signal SVMOD indicating that the in-circuit simulator 1 is in a supervisor state and outputs a user reset mask signal MURESET. A user power supply detection reset circuit 3, detects whether or not there is a user source voltage USRVDD from the user and outputs the user power supply mask signal MPRESET which is masked according to the signal SVMOD. Then a 2nd mask circuit 9 automatically resets the emulation CPU 7 with a reset signal RESET generated by integrating a forcible reset signal CRESET and the mask signals MURESET and the MPRESET.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an in-circuit emulator, and more particularly to an in-circuit emulator suitable for emulating a system frequently attached to and detached from a user system (in the case of an IC card, a card reader) such as an IC card having a CPU. Related to in-circuit emulators.

[0002]

2. Description of the Related Art First, terms used in an in-circuit emulator will be briefly described.

Target CPU: CPU of a user system to be emulated by an in-circuit emulator.

Emulation CPU: Alternative CP to target CPU built in in-circuit emulator
U. At the time of instruction execution, it operates similarly to the target CPU.

Control CPU: CPU for controlling the main body of the in-circuit emulator. Since the in-circuit emulator is a complicated device, it incorporates a CPU separately from the emulation CPU. The control CPU mainly exchanges information with the operator and controls the internal circuit of the in-circuit emulator. Further, a process of extracting information necessary for debugging from the emulation CPU in the break state is also performed.

Control program: A program executed by the control CPU. The control program is created at the time of development of the in-circuit emulator, starts processing when the power of the in-circuit emulator is turned on, and controls all the controls of the in-circuit emulator.

User program: A user-developed program executed by the target CPU. This is the debug target of the in-circuit emulator.

[0008] User system: A system to be developed by a user incorporating a target CPU.

Emulation probe: A dedicated cable for connecting an in-circuit emulator and a user system. The connector is connected to a mounting part of the target CPU of the user system. However, the connector part of the emulation probe for the IC card has the shape of an IC card in which the target CPU is incorporated, and the user system is a card reader connected to the IC card and exchanging information.

User state: A state in which the emulation CPU is executing a user program.

Break state: A state in which the emulation CPU is not executing a user program.

Alternate program: A program executed by the emulation CPU in a break state. Control C
In response to a request from the PU, a process for transferring information in a register or a memory used by the user program to the control CPU is executed.

Supervisor state: emulation C
A state in which the PU executes the alternate program, the control CPU retrieves various information from registers and memories used in the user program, and communicates with the operator. Generally, the operator checks the operation of the user program during the supervisor state.

Commands: Various commands given from the operator to the control CPU. The control CPU interprets the given command and controls the in-circuit emulator as intended by the operator. Typical commands include commands for specifying an operation such as an “execution resuming command” and “execution suspending command”, and commands for setting an execution suspending condition of the command such as a breakpoint setting command.

When the user system is connected to an in-circuit emulator using an emulation probe (hereinafter referred to as a user system connection), the emulation CPU described above uses a clock supplied from the user system (hereinafter referred to as a user clock). ), And executes the user program with a clock (hereinafter, referred to as an internal clock) inside the in-circuit emulator in a state where the user program is not connected to the user system (hereinafter, referred to as a user system non-connection). .

[0016] The conventional in-circuit emulator is designed to prevent the malfunction of the emulation CPU at the time of clock switching, when attaching the emulation probe or removing the emulation probe.
The emulation CPU has been manually reset.

FIG. 9 is a circuit diagram showing a configuration of a conventional in-circuit emulator.

As shown in FIG. 9, a conventional in-circuit emulator 201 includes an emulation CPU 207.
Has a reset circuit 202 that outputs a reset signal RESET for resetting.

The reset circuit 202 has a user reset signal U which is a reset signal supplied from the user system.
A first inverter 203 for inverting RESET;
A first NAND gate 204 which outputs a user reset mask signal MURESET which is a logical product of an output signal of the inverter 203 and a supervisory state signal SVMOD indicating whether or not the in-circuit emulator 201 is in a supervisory state; A second NAND gate 205 for outputting a logical product of the mask signal MURESET and a forced reset signal CRESET issued to the emulation CPU 204 by an instruction of the control software; and an output signal of the second NAND gate 205 for inversion and emulation. CPU
207 that outputs a reset signal RESET to the
And the inverter 206.

In such a configuration, the emulation CPU 207 basically transmits the user reset signal URE
It is reset by SET or forced reset signal CRESET. When the above-described emulation probe is attached or the emulation probe is detached, the emulation CPU 207 is normally reset by the user reset signal URESET. When the emulation CPU 207 is in the break state, the user reset signal URESET is masked by the supervisor state signal SVMOD.

[0021]

In the conventional in-circuit emulator as described above, when the emulation CPU switches from the break state to the user state in a state where the user system is not connected, the emulation CPU is not used.
Executes the user program with the internal clock of the in-circuit emulator.

At this time, if the user system is connected and the operation clock of the emulation CPU is switched to the user clock, the emulation CPU may run away due to the disturbance of the clock waveform at the time of switching the clock.

When the emulation CPU is in the user state while the user system is connected, if the connection to the user system is disconnected, no user clock is supplied and the operation clock of the emulation CPU is switched to the internal clock. Also at this time, the emulation CPU may run away due to the disturbance of the clock waveform at the time of clock switching.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and has as its object to provide an in-circuit emulator that prevents an emulation CPU from running away when a clock is switched. I do.

[0025]

In order to achieve the above object, an in-circuit emulator according to the present invention is a C-type substitute for a CPU of a user system to be emulated.
An in-circuit emulator including an emulation CPU that operates as a PU, and a user reset signal supplied from the user system, the reset signal for the emulation CPU indicating whether the in-circuit emulator is in a supervisor state. A first mask circuit for masking according to a supervisor status signal, and a user power detection reset for detecting presence / absence of user power supplied from the user system and masking the detection result according to the supervisor status signal A circuit;
A second mask for integrating a user reset mask signal as an output signal of the mask circuit and a user power mask signal as an output signal of the user power detection reset circuit, and outputting a reset signal for resetting the emulation CPU. And a circuit.

At this time, the user power supply detection reset circuit includes a user power supply detection circuit for detecting the presence or absence of the user power supply, a supervisor interrupt request signal for requesting switching to the supervisor state, and the user power supply signal based on the supervisor state signal. A supervisor mask signal generation circuit for generating a supervisor mask signal for masking a user power detection signal which is an output signal of the detection circuit, and a reset signal / mask signal integration circuit for masking the user power detection signal according to the supervisor mask signal The user power detection reset circuit may include a user power detection circuit that detects the presence or absence of user power supplied from the user system, and a supervisor that requests switching to the supervisor state. A supervisor mask signal generation circuit for generating a supervisor mask signal for masking a user power detection signal which is an output signal of the user power detection circuit from the supervisor interrupt request signal and the supervisor state signal; A user system connection switching signal generation circuit that outputs a signal for masking the user power detection signal, which is a status signal according to a connection state or a non-connection state, and an output signal of the user system connection switching signal generation circuit, A reset signal / mask signal integration circuit for masking the user power supply detection signal in accordance with the supervisor mask signal.

Further, the user power supply detection circuit has a comparator for comparing the voltage of the user power supply with a predetermined reference voltage and outputting a status signal according to a magnitude relation of the voltage of the user power supply with respect to the reference voltage. The supervisor mask signal generation circuit may be an AND gate that outputs an AND of the supervisor interrupt request signal and the supervisor state signal.

Further, the user system connection switching signal generation circuit may include a switch for outputting a high level or a low level according to a connection state or a non-connection state of the user system.

The in-circuit emulator configured as described above detects a first mask circuit for masking a user reset signal in accordance with a supervisor state signal, detects the presence or absence of a user power supply, and converts the detection result to a supervisor state. Emulating a user power detection reset circuit for masking according to a signal, a user reset mask signal as an output signal of the first mask circuit, and a user power mask signal as an output signal of the user power detection reset circuit; And a second mask circuit for outputting a reset signal for resetting the power supply. When the supply of user power is interrupted when the emulation CPU is not in the supervisor state, that is, in the user state, the user power detection reset circuit Emulation from ® is output signal to reset the down CPU, emulation CPU is automatically reset.

If the user system connection switching signal is set to a level at which the user power supply detection signal is masked, the user power supply detection signal can be detected when the emulation CPU is in the user state even when the user system is not connected. Emulation CP from reset circuit
No signal for resetting U is output.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram showing a configuration of an in-circuit emulator according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration example of the user power supply detection circuit shown in FIG. 1, and FIG. 3 is a circuit diagram showing a configuration example of a supervisor mask signal generation circuit shown in FIG. 4 is a reset signal shown in FIG.
FIG. 3 is a circuit diagram illustrating a configuration example of a mask signal integration circuit.

In FIG. 1, the in-circuit emulator 1 of the present embodiment has a reset circuit 2 for outputting a reset signal RESET for resetting the emulation CPU 7.

The reset circuit 2 masks a user reset signal URESET, which is a reset signal for the emulation CPU 7 supplied from the user system, according to a supervisor state signal SVMOD indicating whether the in-circuit emulator is in a supervisor state. A first mask circuit 8, a user power supply detection reset circuit 3 for detecting the presence or absence of a user power supply from a user power supply voltage USRVDD supplied from a user system, and masking the detection result in accordance with a supervisor state signal SVMOD; User reset mask signal MURESET which is an output signal of the first mask circuit 8
A reset signal for resetting the emulation CPU by integrating a user power supply mask signal MPRESET which is an output signal of the user power supply detection reset circuit 3 and a forced reset signal CRESET which is issued to the emulation CPU 7 by a command of control software. And a second mask circuit 9.

The first mask circuit 8 has a user reset mask signal MURESET which is a logical product of a first inverter 81 for inverting the user reset signal URESET, an output signal of the first inverter 81, and the supervisor state signal SVMOD. , And a first NAND gate 82 that outputs the same.

The second mask circuit 9 comprises a second NAND gate 91 for outputting a logical product of the user reset mask signal MURESET, the user power supply mask signal MPRESET, and the forced reset signal CRESET, and a second NAND gate 91. A second inverter 92 inverts the output signal of the inverter 91 and outputs a reset signal RESET.

The user power supply detection reset circuit 3 detects the presence or absence of the user power supply voltage USRVDD supplied from the user system to the in-circuit emulator, and outputs a user power supply detection signal PRESET as a detection result. , A supervisor interrupt request signal SVI and a supervisor state signal SVMO from the control CPU requesting switching to the supervisor state.
D, a supervisor mask signal generation circuit 5 for outputting a supervisor mask signal SVMASK for masking the user power detection signal PRESET, and a user power mask signal MPRES from the user power detection signal PRESET and the supervisor mask signal SVMASK.
And a reset signal / mask signal integration circuit 6 for generating ET.

As shown in FIG. 2, the user power supply detection circuit 4
Has a comparator 41, and outputs a Hi level when the voltage of the user power supply voltage USRVDD is higher than a predetermined reference potential VREF, for example.
When DD is lower than the reference voltage VREF, a low level is output.

As shown in FIG. 3, the supervisor mask signal generation circuit 5 has an AND gate 51.
When both the supervisor state signal SVMOD and the supervisor interrupt request signal SVI are at the Hi level, a high level is output as the supervisor mask signal SVMASK, and either the supervisor state signal SVMOD or the supervisor interrupt request signal SVI is Low.
At the level, the supervisor mask signal SVMASK
To output a low level.

As shown in FIG. 4, the reset signal / mask signal integration circuit 6 includes an inverter 61 for inverting the user power supply detection signal PRESET, and a NAND gate for outputting the logical product of the output signal of the inverter 61 and the supervisor state signal SVMASK. 62. The reset signal / mask signal integration circuit 6 outputs the user power supply mask signal M
As the PRESET, the supervisor mask signal SVM
When the ASK is at the low level, it always outputs the Hi level, and when the supervisor mask signal SVMASK is at the Hi level, it outputs the same level as the user power supply detection signal PRESET.

Next, the operation of the in-circuit emulator shown in FIG. 1 will be described with reference to FIG.

FIG. 5 is a timing chart showing the operation of the in-circuit emulator shown in FIG.
In the following, the forced reset signal CR is sent from the control software.
It is assumed that ESET is not supplied and is fixed at the Hi level, and the user system is always connected to the in-circuit emulator.

In FIG. 5, when the in-circuit emulator is in the supervisor state and the user system is in the non-connected state (before time T0), the user power supply voltage USRVDD is not supplied to the in-circuit emulator 1; The signal PRESET is Lo
It becomes w level.

At this time, since the in-circuit emulator is in the supervisor state, the supervisor state signal SVMOD is at the low level, the supervisor interrupt request signal SVI is at the high level, and the supervisor mask signal SVMASK is at the low level. Therefore, the user power supply detection signal PRESET is masked, and the user power supply mask signal MPRESET becomes Hi level.

Since the input of the first inverter 81 is pulled up as shown in FIG. 1, the user reset signal RESET is set when the user system is not connected.
Becomes Hi level. User reset signal URESRE
T is masked because the supervisor state signal SMVOD is at the low level, and the user reset mask signal M
URESET goes to Hi level.

Therefore, the RESET signal to the emulation CPU 7 is the user reset mask signal M
Since the RESET and the user power supply mask signal MPRESET are at the Hi level, respectively, they are set to the Hi level, and the emulation CPU 7 is in the reset release state.

Subsequently, when the user program is executed at time T0, the emulation CPU 7 enters the user state, and the supervisor state signal SVMOD becomes Hi.
Level, the supervisor mask signal S
VMASK becomes Hi level and the user power supply detection signal P
The mask for RESET is released.

At this time, the user power supply detection signal PRESE
Since T is at the low level, the user power supply mask signal M
PRESET goes low, and the reset signal RE
SET switches to the low level, and the emulation CPU 7 is reset.

In such a state, the emulation CPU
Even if the operation clock of 7 is switched from the internal clock to the user clock, no clock is supplied to the emulation CPU 7 because the user system is not connected. However, no problem occurs because the emulation CPU 7 is in the reset state.

Next, when the user system is connected to the in-circuit emulator using the emulation probe at time T1 (hereinafter simply referred to as "connecting the user system"), the user power is supplied from the user system to the in-circuit emulator 1 and the user is connected to the in-circuit emulator 1. Clocks are supplied respectively. When the user power supply voltage USRVDD is supplied, the user power supply detection circuit 4 switches the user power supply detection signal PRESET to the Hi level.

At this time, the supervisor mask signal SV
MASK is maintained at the Hi level without change, and the user power supply detection signal PRESET signal is not masked, so that the user power supply mask signal MPRESET is switched to the Hi level, and the reset of the emulation CPU 7 is released.

Generally, the user system drives the user reset signal URESET to a low level until time T2 when the oscillation of the user clock supplied at time T1 is stabilized. At this time, the supervisor state signal SVMO
Since D remains unchanged and remains at the Hi level, the user reset mask signal MURESET switches to the Low level.

Therefore, at time T1, the user reset mask signal MURESET goes low, the user power supply mask signal MPRESET goes high, and the reset signal RESET is kept low, so that the emulation CPU 7 is kept in the reset state.

Next, when the oscillation of the user clock is stabilized at time T2, the user system drives the user reset signal URESET to the Hi level to release the reset. At this time, the supervisor state signal SVMA
SK is maintained at the Hi level, and the user reset signal UR
Since the ESET is not masked, the user reset mask signal MURESET switches to the Hi level.

On the other hand, the user power supply detection signal PRESET is maintained at the Hi level, and the user power supply mask signal MPRE is maintained.
Since SET is maintained at the Hi level, the reset signal RESET is switched to the Hi level, and the emulation CPU 7 is released from the reset and executes processing according to the user program.

Next, when the user system is disconnected from the in-circuit emulator at time T3 (hereinafter, simply referred to as "disconnecting the user system"), the user power supply and the user clock are not supplied from the user system.

At this time, the user power supply detection signal PRESE
T switches to the low level, and the supervisor mask signal SVMASK is maintained at the high level.
The user power supply mask signal MPRESET is switched to a low level.

When the user system is disconnected, the first
Of the inverter 81 is pulled up, the user reset signal URESET becomes Hi level.
At this time, the supervisor state signal SVMASK becomes Hi.
Therefore, the user reset mask signal MURESET is maintained at the Hi level.

Therefore, user power supply mask signal MPR
ESET is low level, user reset mask signal M
Since RESET is at the Hi level, the reset signal R
ESET is switched to the low level, and the emulation CPU 7 is reset again.

That is, in the in-circuit emulator of the present embodiment, the emulation CPU 7 is automatically reset even when the supply of the user power supply and the user clock is interrupted when the emulation CPU 7 is in the user state. In such a state, even if the operation clock is switched from the user clock to the internal clock, the emulation C
PU7 does not run away.

Next, when the emulation CPU 7 shifts to the break state at time T4, the supervisor interrupt request signal SVI goes low, the supervisor mask signal SVMASK goes low, and the user power supply detection signal PRESET becomes the supervisor mask signal SVMASK signal. Masked by
At this time, the user power supply detection signal PRESET is at the low level, but the supervisor mask signal SVMASK
, The user power supply mask signal MPRESET becomes Hi level.

On the other hand, since the user reset signal URESET is pulled up, it is maintained at the Hi level. Since the supervisor state signal SVMOD is at the Hi level, the user reset mask signal MURESET is maintained at the Hi level.

Therefore, user power supply mask signal MPR
ESET and user reset mask signal MURESE
Since T is at the Hi level, the reset signal RE
SET becomes Hi level, and the emulation CPU 7
Is reset and the operation resumes.

Next, at time T5, when the emulation CPU 7 receives the supervisor interrupt request signal SVI and the in-circuit emulator 1 shifts to the supervisor state, the supervisor state signal SVMO
D becomes Low level, and the supervisor interrupt request signal SVI is cleared to Hi level.

At this time, the supervisor mask signal SV
Since MASKS is maintained at the low level and the user power supply detection signal PRESET is masked, the user power supply mask signal MPRESET is maintained at the Hi level.

On the other hand, since the user reset signal URESET is maintained at the Hi level, the user reset mask signal MUPRESET is maintained at the Hi level.

Therefore, user power supply mask signal MPRES
Since the ET and the user reset mask signal MURESET are at the Hi level, the reset signal RESET is
Are maintained at the Hi level, and the emulation CPU 7 is maintained in the reset release state.

As described above, the in-circuit emulator of the present embodiment operates when the emulation CPU changes from the break state to the user state when the user system is not connected (between T0 and T1 in FIG. 5, T3 and T4 in FIG. 5).
In the meantime, since the emulation CPU 7 is automatically reset, runaway of the emulation CPU 7 due to the disturbance of the clock waveform at the time of clock switching can be avoided.

(Second Embodiment) Next, a description will be given of a second embodiment of the in-circuit emulator according to the present invention.

FIG. 6 is a circuit diagram showing the configuration of a second embodiment of the in-circuit emulator of the present invention. FIG. 7 is a circuit diagram showing an example of the configuration of the reset signal / mask signal integration circuit shown in FIG. 6, and FIG. 8 is a circuit showing an example of the configuration of the user system connection switching signal generation circuit shown in FIG. FIG.

In FIG. 6, the in-circuit emulator according to the second embodiment provides a status signal according to the connection state or non-connection state of the user system to the user power detection reset circuit of the first embodiment. A user system connection switching signal generation circuit 11 for outputting a user system connection switching signal EMDMASK for masking a user power supply detection signal is added. In this configuration, a user system connection switching signal EMDMASK is input. The other configuration is the same as that of the first embodiment, and the description is omitted.

The reset signal / mask signal integration circuit 10 according to the present embodiment includes a supervisor mask signal SVMAS.
Not only K but also user system connection switching signal EMDM
ASK also has a function of masking the user power supply detection signal PRESET.

As shown in FIG. 7, the reset signal / mask signal integration circuit 10 outputs a user power supply detection signal PRESET.
101, an output signal of the inverter 101, a user system connection switching signal EMDMAS
K, and a three-input NAND gate 102 that outputs the logical product of K and the supervisor state signal SVMASK.

The reset signal / mask signal integration circuit 10 according to the present embodiment includes, for example, a user power supply mask signal MPR
As the ESET, the supervisor mask signal SVMAS
K, when any one of the user system connection switching signal EMDMASK is at a low level, a high level is output. When both the supervisor mask signal SVMASK and the user system connection switching signal EMDMASK are at a high level, the same level as the user power supply detection signal PRESET is set. Output.

As shown in FIG. 8, the user system connection switching signal generation circuit 11 outputs the user system connection switching signal EMDASK as Hi level (power supply voltage VC
C) or a switch 111 for outputting either a low level (ground potential). Note that the switch 111 shown in FIG. 8 is configured to manually switch the output voltage.

User system connection switching signal ENDM
The ASK is set to the Hi level when the user system is connected during the emulation, and is set to the Low level when the user system is not connected. Note that the user system connection switching signal generation circuit 11 may be configured to switch the level of the user system connection switching signal EMDMASK by a command input in addition to the switch 111 shown in FIG.

In such a configuration, in the in-circuit emulator according to the first embodiment, the emulation CPU is in the break state (before time T0 in FIG. 5).
(Period after time T4), the user power detection signal PRES
ET was masked by the supervisor mask signal SVMASK. Also, during the period when the emulation CPU is in the user state (period T0 to T4 in FIG. 5),
Since the user power supply detection signal PRESET is not masked by the supervisor mask signal SVMASK, the user power supply mask signal MPRES is output when the user system is not connected.
ET goes to the low level, and the emulation CPU has been reset.

On the other hand, in the in-circuit emulator according to the second embodiment, the user system connection switching signal E
By setting MDMASK to Low level, the user power supply detection signal PRESET is masked in the user state, and even when the user system is not connected and the user power supply detection signal PRESET is at Low level, the user power supply mask signal MPRESET is always Hi. Maintained at the level. When the user system is not connected, the input of the first inverter is pulled up, so that the user reset signal URESET is maintained at the Hi level.

Therefore, if the user system connection switching signal EMDMASK is set to the low level, the user power supply mask signal MPRESET and the user reset mask signal MURESET are always maintained at the high level in the user state even when the user system is not connected. And the emulation CPU is not reset.

Therefore, the user program can be executed even when the user system is not connected, and the user program can be debugged without the user system. The user system connection switching signal E
When MDMASK is set to Low level, the operation is the same as in the first embodiment.

[0081]

Since the present invention is configured as described above, the following effects can be obtained.

A first mask circuit for masking a user reset signal according to a supervisor state signal, and a user power supply detection reset circuit for detecting presence or absence of a user power supply and masking the detection result according to a supervisor state signal A user reset mask signal that is an output signal of the first mask circuit and a user power mask signal that is an output signal of the user power detection reset circuit, and outputs a reset signal for resetting the emulation CPU. When the supply of user power is interrupted when the emulation CPU is not in the supervisor state, that is, in the user state, a signal for resetting the emulation CPU is output from the user power detection reset circuit. , Emi Configuration CPU is automatically reset. Therefore, runaway of the emulation CPU due to the disturbance of the clock waveform at the time of clock switching can be avoided.

If the user system connection switching signal is set to a level at which the user power supply detection signal is masked, even when the user system is not connected, when the emulation CPU is in the user state, the user power supply detection signal is detected. Emulation CP from reset circuit
No signal for resetting U is output. Therefore, since the user program can be executed even when the user system is not connected, the user program can be debugged without the user system.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of an in-circuit emulator of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a user power supply detection circuit illustrated in FIG. 1;

FIG. 3 is a circuit diagram illustrating a configuration example of a supervisor mask signal generation circuit illustrated in FIG. 1;

FIG. 4 is a circuit diagram showing a configuration example of a reset signal / mask signal integration circuit shown in FIG. 1;

FIG. 5 is a timing chart showing an operation of the in-circuit emulator shown in FIG. 1;

FIG. 6 is a circuit diagram showing a configuration of a second embodiment of the in-circuit emulator of the present invention.

FIG. 7 is a circuit diagram showing a configuration example of a reset signal / mask signal integration circuit shown in FIG. 6;

8 is a circuit diagram illustrating a configuration example of a user system connection switching signal generation circuit illustrated in FIG. 6;

FIG. 9 is a circuit diagram showing a configuration of a conventional in-circuit emulator.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 In-circuit emulator 2 Reset circuit 3 User power detection reset circuit 4 User power detection circuit 5 Supervisor mask signal generation circuit 6, 10 Reset signal / mask signal integration circuit 7 Emulation CPU 8 First mask circuit 9 Second mask circuit 11 User system connection switching signal generation circuit 81 First inverter 82 First NAND gate 91 Second NAND gate 92 Second inverter 41 Comparator 51 AND gate 61, 101 Inverter 62, 102 NAND gate 111 Switch

Claims (6)

[Claims] 1. An in-circuit emulator incorporating an emulation CPU that operates as a substitute CPU for a CPU of a user system to be emulated, wherein the user reset signal is a reset signal supplied from the user system to the emulation CPU. A first mask circuit for masking the in-circuit emulator in accordance with a supervisory state signal indicating whether or not the in-circuit emulator is in a supervisory state. A user power detection reset circuit for masking a result according to the supervisor state signal, a user reset mask signal which is an output signal of the first mask circuit, and a user power detection reset circuit. A second mask circuit that integrates a user power supply mask signal as an output signal and outputs a reset signal for resetting the emulation CPU. 2. The user power supply detection reset circuit, comprising: a user power supply detection circuit for detecting presence / absence of the user power supply; A supervisor mask signal generation circuit that generates a supervisor mask signal for masking a user power detection signal that is an output signal of the circuit; and a reset signal / mask signal integration circuit that masks the user power detection signal according to the supervisor mask signal. The in-circuit emulator according to claim 1, comprising: 3. The user power supply detection reset circuit, comprising: a user power supply detection circuit for detecting presence / absence of user power supplied from the user system; and a supervisory interrupt request signal for requesting switching to the supervisory state. And a supervisor mask signal generation circuit for generating a supervisor mask signal for masking a user power detection signal, which is an output signal of the user power detection circuit, from the supervisor status signal, according to a connection state or a non-connection state of the user system. A user system connection switching signal generation circuit that outputs a signal for masking the user power supply detection signal, an output signal of the user system connection switching signal generation circuit, and the supervisor mask signal. In-circuit emulator according to claim 1 having a, a reset signal, mask signal integration circuit for masking the user power detection signal in accordance with. 4. The user power supply detection circuit has a comparator that compares a voltage of the user power supply with a predetermined reference voltage and outputs a status signal according to a magnitude relationship between the voltage of the user power supply and the reference voltage. The in-circuit emulator according to claim 2. 5. The in-circuit emulator according to claim 2, wherein the supervisor mask signal generation circuit is an AND gate that outputs an AND of the supervisor interrupt request signal and the supervisor state signal. 6. The in-circuit emulator according to claim 3, wherein the user system connection switching signal generation circuit has a switch that outputs a high level or a low level according to a connection state or a non-connection state of the user system.