JP2000322883A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor storage device which can reduce a chip area, lower power consumption and speed up processing. SOLUTION: The device has a plurality of banks 71-74 each including memory cell arrays arranged longitudinally and laterally corresponding to rows and columns, a column line select part 52 for selecting one column line from a plurality of column lines shared by the plurality of banks 71-74 based on a column access command, and a plurality of word line select parts 41-44 for selecting one word line from a plurality of word lines shared by the plurality of the banks 7L-74 based on the column access command and a row access command, and controlling a sense amplifier corresponding to the word line to read or write. Since the plurality of banks share the column lines, the column line select part can be shared among the plurality of banks, and the number of column line select parts included in the semiconductor storage device can be reduced. The semiconductor storage device can reduce a chip area and lower power consumption accordingly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a plurality of banks operating in synchronization with a clock.

[0002]

2. Description of the Related Art With the speeding up of CPUs, DRAMs (Digital
dynamic Random Access Memo
ry) and the like are required to further increase the data read / write speed. This DRA
M is devised to provide a page mode, for example, in order to improve the data read / write speed.

Further, by reading / writing data in synchronization with a clock, data reading / writing is performed.
SDRAM (Synchron) that improves write speed
ous Dynamic Random Access
Memory). Hereinafter, an operation of the SDRAM will be described as an example of a conventional semiconductor memory device. FIG. 1 shows a configuration diagram of an example of a semiconductor memory device. S in FIG.
The DRAM 1 includes an input / output signal processing unit 10, a row control unit 20, a column control unit 30, a plurality of row decoders 40, a plurality of column decoders 50, a plurality of read / write amplifiers 60, and a plurality of banks 70. , And the common data bus 80.

Each bank 70 independently has a row decoder 40, a column decoder 50, and a read / write amplifier 60, and utilizes the row decoder 40 and the column decoder 50 provided for each bank. Is read / written. The read data or the data to be written is transferred to the common data bus 8 shared by the banks 70 via the read / write amplifier 60.
0 was output or input from the common data bus 80.

[0005]

However, the conventional SDRAM 1 reads data from one bank 70,
Alternatively, when writing data, the row decoder 40 and the column decoder 50 of another bank 70 not used are used.
And the read / write amplifier 60 exists.
Therefore, there has been a problem that it has become a hindrance factor for realizing a reduction in chip area and a reduction in current consumption, which are required in recent semiconductor memory devices.

The read / write amplifiers 60 of each bank 70 use a common common data bus 80.
There is a problem that the maximum operation frequency of the read operation and the write operation is reduced. Further, the read / write amplifiers 60 of the respective banks 70 share a common data bus 80.
There is a problem that the load on the common data bus 80 is large due to the use of the common data bus.

An object of the present invention is to provide a semiconductor memory device capable of reducing a chip area, reducing power consumption, and increasing processing speed.

[0008]

Therefore, in order to solve the above-mentioned problems, the present invention according to claim 1 comprises a plurality of banks each including a memory cell array arranged vertically and horizontally corresponding to rows and columns; A column line selection unit that selects one column line from a plurality of column lines shared by the plurality of banks based on an access command; and a plurality of banks respectively included in the plurality of banks based on the column access command and the row access command. A plurality of word line selectors are provided for selecting one word line from the word lines and controlling a read or write operation of a sense amplifier corresponding to the selected word line.

As described above, by sharing a column line with a plurality of banks, a column line selection unit can be shared by a plurality of banks, and the number of column line selection units included in a semiconductor memory device can be reduced. Therefore, the semiconductor memory device of the present invention can reduce the chip area and reduce power consumption. Note that the bank selection is processed by a word line selection unit provided for each bank, and one bank can be selected from a plurality of banks based on a column access command. Therefore, even if the column line selection unit is shared by a plurality of banks, the bank can be selected.

In the present invention, preferably, the plurality of word line selection units include a signal for selecting a bank among the column access commands and a signal for controlling a read or write operation of a sense amplifier, and A selection of a sense amplifier and a read or write operation are controlled by a signal generated based on an access command and selecting a plurality of sense amplifiers selected by the one word line.

As described above, the bank selection and the read or write operation of the sense amplifier can be controlled by the word line selection unit, and the column line selection unit, the global data bus, the read amplifier, and the write amplifier can be controlled. Even if the data is shared by a plurality of banks, data can be read and written for each bank. According to a third aspect of the present invention, the plurality of word line selectors include a signal for selecting a bank among the column access commands, a signal for controlling a read or write operation of a sense amplifier, and an activation of the sense amplifier. The selection of the sense amplifier and the read or write operation are controlled by a timing signal for performing the conversion.

As described above, the selection of the sense amplifier and the control of the read or write operation are controlled by the signal for selecting the bank in the column access command, the signal for controlling the read or write operation of the sense amplifier, and the activation of the sense amplifier. It is also possible to carry out by a timing signal to be carried out. Therefore, by using the timing signal for activating the sense amplifier, it is possible to prevent the signal for controlling the operation of the sense amplifier from being activated before the operation of the sense amplifier, and to reduce disturbance to the operation of the sense amplifier. Is possible.

Further, according to a fourth aspect of the present invention, the signals for controlling the selection of the sense amplifier and the read or write operation output from the word line selector are provided by a plurality of sense amplifiers selected by the one word line. The amplifier is supplied for each sense amplifier group obtained by dividing the amplifier. As described above, the plurality of sense amplifiers selected by one word line are divided into the plurality of sense amplifier groups, and the selection of the sense amplifiers output from the word line selection unit and the read or write operation are performed for each of the sense amplifier groups. By supplying each of the signals to be controlled, it is possible to eliminate the operation failure of the sense amplifier due to signal delay and waveform rounding.

According to a fifth aspect of the present invention, the column line selector and the write amplifier are arranged in one of the plurality of banks, and the read amplifier is arranged in the other of the plurality of banks. I do. As described above, the column line selection unit and the write amplifier are arranged in one of the plurality of banks, and the read amplifier is arranged in the other of the plurality of banks. There is no need to set different timings. Therefore, it is not necessary to secure a timing margin that had to be provided for each operation, and each operation can be speeded up.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a configuration diagram of the first embodiment of the semiconductor memory device of the present invention. In this embodiment, the operation of an SDRAM having a 4-bank configuration will be described as an example of a semiconductor memory device, but the present invention is not limited to this. Also,
In FIG. 2, for example, only the minimum number of lines used for the description is shown for the word lines WL, the column lines CLS, and the like.

The SDRAM 2 shown in FIG. 2 includes an input / output signal processing unit 10, a row control unit 20, a column control unit 30, row decoders 41 to 44, a column decoder 52, a read amplifier 61, and a write amplifier 62. ,
The configuration includes banks 71 to 74 and a common data bus 80. Note that the banks 71 to 74 are composed of a plurality of blocks.

When a clock signal, a control signal, and an address signal are supplied to the input / output signal processing unit 10 from the control system input terminal CNTLs, the input / output signal processing unit 10 decodes the supplied control signal, and decodes the decoding result. Is supplied to the row control unit 20 and the column control unit 30. Low control unit 20
Are signals AB0-3 for selecting a bank to be activated based on the decoding result, signals PB0-3 for selecting a bank to be precharged, and an address signal BR0 for activating a specific sense amplifier row. To 1 are supplied to row decoders 41 to 44 including a sense amplifier driver.

A column control unit 30 has a signal BN for selecting a bank from which data is read or written, based on the result of decoding by the input / output processing unit 10.
K0-3, a signal ER for permitting data reading,
A signal EW for permitting data writing is supplied to the row decoders 41 to 44, and a signal for selecting the column line CLS is supplied to the column decorator 52.

The row decoders 41 to 44 generate signals BLK0 to BLKn for selecting a block by decoding the signals BR0 to BR1 supplied from the row control unit 20, and the signals BLK0 to BLKn and the column control unit 3
A signal / RS and a signal WS for controlling the reading and writing operations of the data of the sense amplifier row in contact with the block selected from the signals BNK0 to BNK3 supplied from 0 and the signal ER and the signal EW are generated.

In this embodiment, an example in which a signal BLK is used as a signal for selecting a block will be described. However, a signal used for activating a sense amplifier, for example, a signal SA is used.
In addition to N / SAP, a latch timing signal LE may be used. Although the processing relating to the address signal is omitted in the figure, normal decoding processing is performed to select a word line and a column line to read data, or select a cell to which data is to be written.

In the semiconductor memory device of the present invention, the column decoder 50 and the read / write amplifier 60 conventionally provided for each of the banks 71 to 74 are replaced with one column decoder 52, a read amplifier 61, and a write amplifier 62 common to each bank. Has been changed to. That is, when a word line and a column line are selected and a cell at the intersection of the word line and the column line is selected as in the conventional case, the banks 71 to 74 are selected.
Cell is selected one by one.

The row decoders 41 to 44 supply the signals / RS and WS controlling the data read and write operations of the sense amplifier array to one of the banks 71 to 74, respectively. One of the banks 74 can be selected. The bank selection is performed based on signals BNK0 to BNK3 supplied from the column control unit 30.

Therefore, among the cells selected for each bank by the word line and the column line, the signal / RS and the signal WS for controlling the data read and write operations are provided.
Only the cells corresponding to the sense amplifier row selected by the above are connected to the local data bus described later. The local data bus is connected to the read amplifier 61 and the write amplifier 62 via a global data bus commonly used by the banks 71 to 74, and connects the cells to the common data bus 80. The common data bus 80 connects the read amplifier 61, the write amplifier 62, and the input / output signal processing unit 10.

As described above, in the SDRAM 2, a sense amplifier row included in one of a plurality of banks is selected, and a local data bus, a global data bus, a read amplifier 61 or a write amplifier 62, a common data bus 80, and Through the input / output signal processing unit 10, data can be supplied to the data input / output terminals DQ0 to 1, or data can be supplied from the data input / output terminals DQ0 to 1.

The operation of the SDRAM 2 of FIG. 2 will be described more specifically. For example, when a read command for a block of the bank 71 is supplied, the signal B
NK0 and the activated signal ER are supplied to each of the row address decoders 41 to 44. That is, the row decoder 41 is selected by the signal BNK0, and the signal / RS for controlling the read operation of the sense amplifier row selected from the row decoder 41 is supplied to the bank 71.

At this time, the unselected sense amplifier row of the bank 71 and the signals / R of the other banks 72 to 74 are output.
S is inactive and does not affect the connected global data bus. Further, since the column line CLS is selected as usual, the data read from the pair of bit lines BL is output to the global data bus via the sense amplifier and the local data bus. Thereafter, data is output to the data input / output terminals DQ0-1 by the same processing as that of a normal semiconductor memory device.

On the other hand, when a write command for the block of the bank 72 is supplied, the signal BNK1 and the activated signal EW are supplied to the row address decoders 41 to 44.
Supplied to That is, the row decoder 42 is selected by the signal BNK1, and a signal WS for controlling the write operation of the selected sense amplifier row is supplied from the row decoder 42 to the bank 72.

At this time, the sense amplifier row not selected in the bank 72 and the signals WS of the other banks 71 and 73 to 74 are inactive and do not affect the connected global data bus. Since the column line CLS is selected as usual, the data input / output terminals DQ0 to DQ0
The data supplied to 1 is written to a set of bit lines BL via a global data bus, a local data bus, a sense amplifier, and the like.

As described above, the column decoder 52, the read amplifier 61, and the write amplifier 6 include the plurality of banks 71 to 74.
2. Even if the global data bus is shared, data read and write operations can be performed for each bank, and the number of column decoders and read / write amplifiers can be reduced. FIG. 3 shows a connection diagram of an example of the sense amplifier array. Although FIG. 3 shows an example of the circuit of the sense amplifier n selected by the column line CLS, the present invention is not limited to this circuit.

The NAND circuits 90 and 91 and the NOT circuit 92 in FIG. 3 are configured to be included in, for example, the row decoders 41 to 44. NAND circuit 90 includes a signal BLKn for selecting a block generated by decoding signals BR0 to 1 supplied from row control unit 20, and a signal BNK for selecting a bank from which data is read or written.
n and a signal EW for permitting data writing.

The NAND circuit 91 includes a signal BLKn for selecting a block generated by decoding the signals BR0 to BR1 supplied from the row control unit 20, and a signal BNKn for selecting a bank from which data is read or written. , And a signal ER for permitting data reading. Therefore, bank select signal BNK
n and the signal BLKn for selecting a block are High signals, and when the signal EW is a High signal, NA
A High signal is supplied via the ND circuit 90 and the NOT circuit 92, and outputs a signal WS for controlling the write operation of the sense amplifier array in contact with the selected block.

When the signal BNKn for selecting a bank and the signal BLKn for selecting a block are High signals and the signal ER is a High signal, a Low signal is supplied via the NAND circuit 91 and the selection signal is supplied. And outputs a signal / RS for controlling the read operation of the sense amplifier row in contact with the block. One sense amplifier row is connected to common signals / RS and WS, and is in a state where data can be read or written for each block.
At this time, data is read or written for one sense amplifier included in the sense amplifier row by the column line CLSn selected by the column decorator 52.

The selected one sense amplifier writes the data supplied from the local write data bus (local WDB) or outputs the read data to the local read data bus (local RDB). The local write data bus and the local read data bus are respectively read global data bus (RGD).
B) and a write global data bus (WGDB).

The read global data bus and the write global data bus may be a common global data bus (GDB). It is also possible to prepare a plurality of global data buses and simultaneously activate a plurality of sense amplifiers to read or write a large number of data. FIG. 4 shows a timing chart of an example of the semiconductor memory device of the present invention. The signal / RAS shown in FIG. 4C is a signal for row access, and corresponds to the activation commands ACTV0 and ACTV1 in FIG. FIG.
The signal / CAS shown in (D) is a signal for column access, and corresponds to the read command RD0,1 and the write command WRT0 in FIG.

The signal / RAS shown in FIG. 4C selects a row cell block in the semiconductor memory device, that is, a specific word line. Further, the signal / CAS shown in FIG.
Selects a specific column, that is, a sense amplifier, from the selected word lines. The signals shown in FIGS. 4B to 4F are the same as those in the timing chart of the conventional semiconductor memory device.

The signal CLS shown in FIG. 4G is a signal for selecting a column line, and is generated corresponding to the read command RD0, RD1 and the write command WRT0 shown in FIG. For example, the read command RD shown in FIG.
The signal CLS-i shown in FIG. The signal EW shown in FIG. 4H is a signal for permitting data writing, and is generated in response to the write command WRT0 shown in FIG. A signal ER shown in FIG. 4I is a signal for permitting data reading.
It is generated corresponding to the read command RD0, RD1 shown in FIG.

A signal bank0 shown in FIG. 4 (J) is a signal for selecting a bank from which data is read or written, and is generated in response to a read command RD0 and a write command WRT0 for bank 0 shown in FIG. 4 (A). Is done. The signals bank0 to WLn shown in FIG.
Select a specific word line in bank 0. The signal bank0- / RS shown in FIG. 4L is generated in response to the data read operation of the sense amplifier array. FIG.
The signal bank0-WS shown in (M) is generated in response to the data write operation of the sense amplifier array.

Therefore, after data is read from bank 0 at the timing shown in FIG. 4 (Q), data is subsequently written to bank 0. Also, as in the case of the read operation from bank 0, the operation of FIG.
After data is written to bank 0 shown in FIG. 4 (Q) based on the signals (N) to (P), data is subsequently read from bank 1.

As described above, since the data read / write operation of each bank can be controlled using the signal / RS and the signal WS, data read / write can be performed for each bank even if the global data bus is shared. Becomes Next, a second embodiment of the present invention will be described. FIG.
2 shows a configuration diagram of a second embodiment of the semiconductor memory device of the present invention. As shown in FIG. 5, the semiconductor memory device 3 includes a column decoder 104 shared by a plurality of banks in one of a memory cell array including a plurality of banks 110 to 113.
And a write amplifier 102, and a read amplifier 108 shared by a plurality of banks is provided on the other side. The control circuit 100 decodes the supplied control signal and controls each component based on the decoding result.

When a read command is supplied, the control circuit 100 reads data from each bank by controlling the column decoder 104, the row decoder 106, and the read amplifier 108, and outputs the data via the output driver 114. Also, the control circuit 100
When a write command is supplied, the column decoder 10
4. The row decoder 106, the input driver 115, and the write amplifier 102 are controlled to write data input to the input driver 115 to a predetermined bank via the write amplifier 102.

When the semiconductor memory device 3 is configured as shown in FIG. 5, the direction in which each signal flows is unified in the direction from the column decoder 104 to the read amplifier 108. As described above, when the directions in which the signals flow are unified, it is not necessary to set different timings when reading and writing data, and the timing control can be performed by the column decoder 104.

Therefore, it is not necessary to secure a timing margin which had to be provided for each operation, and each operation can be speeded up. FIG. 6 shows the signal / R
FIG. 2 shows a circuit diagram of an embodiment for generating S and WS. In the circuit diagram of FIG. 6, instead of using the signal BLKn for selecting a block, a signal LE for generating the signals SAn and SAp is used as one of the signals for generating the signals / RS and WS. I'm using

The signals SAn and SAp are timing signals for the latch operation of the sense amplifier. Also, NAND
The parts composed of the circuits 90 and 91 and the NOT circuit 92 are the same as those described with reference to FIG. Since this signal LE is activated when the sense amplifier actually starts amplifying, it is possible to reduce disturbance to the operation of the sense amplifier due to activation of the signals / RS and WS before the operation of the sense amplifier. It is possible to In order to further reduce the interference, the signal LE may be delayed by the delay circuit 121 before being input to the NAND circuit 90 as shown in FIG.

In this case, as shown in FIG.
Can be delayed with respect to the signal LE, and for example, the possibility that the signal / RS is activated before the operation of the sense amplifier can be reduced. FIG. 9 shows a configuration diagram of one embodiment of the sense amplifier array. In FIG. 9, a signal / RS, WS is divided into a plurality of signals sub- / RS, sub-WS, and the divided signals sub- / RS, sub-WS are divided.
Is supplied to a sub-sense amplifier array 132 obtained by dividing the sense amplifier array into a plurality of parts through an amplifier 130.

As described above, the signal / RS, WS is divided into a plurality of signals sub- / RS, sub-WS, and the sense amplifier array 132 is divided into a plurality of sub-sense amplifier arrays 132.
To one signal sub- / RS, su
It is possible to reduce the number of sense amplifiers connected to the b-WS, and it is possible to improve the delay of the signals / RS and WS and the rounding of the waveform.

Although not shown in the above embodiment,
When the size of the memory cell becomes large and a delay in signal propagation speed of a column line, a global data bus, or the like becomes a problem, the number of banks shared by one column decoder, read amplifier, and write amplifier is reduced. Is also good. For example, if the configuration shown in FIG.
A semiconductor memory device in a bank becomes possible.

The column line selecting section described in the claims corresponds to the column decoder 52, the word line selecting section corresponds to the row decoders 41 to 44, and the timing signal for activating the sense amplifier is a signal LE. , And the sense amplifier group corresponds to the sub-sense amplifier row 132.

[0048]

As described above, according to the first aspect of the present invention, a plurality of banks share a column line, so that a column line selecting unit can be shared by a plurality of banks. Can be reduced in the number of column line selection sections included. Therefore, the semiconductor memory device of the present invention can reduce the chip area and reduce power consumption.

The bank selection is performed by a word line selector provided for each bank, and one bank can be selected from a plurality of banks based on a column access command. Therefore, even if the column line selection unit is shared by a plurality of banks, the bank can be selected. According to the second aspect of the present invention, it is possible to control the bank selection and the read or write operation of the sense amplifier by the word line selection unit, and to select the column line selection unit, the global data bus, and the read operation. Even if the amplifier and the write amplifier are shared by a plurality of banks, data can be read and written for each bank.

According to the third aspect of the present invention, the selection of the sense amplifier and the control of the read or write operation are controlled by the signal for selecting the bank in the column access command and the read or write operation of the sense amplifier. Signals and a timing signal for activating the sense amplifier can also be used. Therefore, by using the timing signal for activating the sense amplifier, it is possible to prevent the signal for controlling the operation of the sense amplifier from being activated before the operation of the sense amplifier, and to reduce disturbance to the operation of the sense amplifier. Is possible.

According to the present invention, a plurality of sense amplifiers selected by one word line are divided into a plurality of sense amplifier groups, and each sense amplifier group is output from a word line selection unit. By supplying a signal for controlling the sense amplifier selection and the read or write operation to be performed, it is possible to eliminate a sense amplifier operation failure due to signal delay and waveform rounding.

According to the fifth aspect of the present invention, the column line selection section and the write amplifier are arranged in one of the plurality of banks, and the read amplifier is arranged in the other of the plurality of banks. The flow direction is unified, so that it is not necessary to set different timings when reading and writing data. Therefore, it is not necessary to secure a timing margin that had to be provided for each operation, and each operation can be speeded up.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an example of a semiconductor memory device.

FIG. 2 is a configuration diagram of a first embodiment of a semiconductor memory device of the present invention.

FIG. 3 is a connection diagram of an example of a sense amplifier array.

FIG. 4 is a timing chart of an example of the semiconductor memory device of the present invention.

FIG. 5 is a configuration diagram of a second embodiment of the semiconductor memory device of the present invention.

FIG. 6 is a circuit diagram of an embodiment for generating signals / RS and WS.

FIG. 7 is a circuit diagram of an embodiment for generating signals / RS and WS.

FIG. 8 is a timing chart of an example of the circuit diagram of FIG. 7;

FIG. 9 is a configuration diagram of an embodiment of a sense amplifier array.

[Explanation of symbols]

 2 SDRAM 10 I / O signal processing unit 20 Row control unit 30 Column control unit 41 to 44, 106 Row decoder 52, 104 Column decoder 61, 108 Read amplifier 62, 102 Write amplifier 71 to 74, 110 to 113 Bank 80 Common data bus 90, 91 NAND circuit 92 NOT circuit 100 control circuit 114 output driver 115 input driver 121 delay circuit 130 amplifying unit 132 sub-sense amplifier train

Continued on the front page (72) Inventor Masato Takita 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa F-term in Fujitsu Limited (Reference) 5B024 AA01 AA07 AA15 BA15 BA21 BA23 CA16 CA21

Claims (5)

[Claims] 1. A plurality of banks each including a memory cell array arranged vertically and horizontally corresponding to a row and a column, and one column line from a plurality of column lines shared by the plurality of banks based on a column access instruction. A column line selecting unit to be selected, one word line is selected from a plurality of word lines respectively provided by the plurality of banks based on the column access command and the row access command, and reading or reading of a sense amplifier corresponding to the word line is performed. A semiconductor memory device comprising: a plurality of word line selection units for controlling a write operation. 2. The method according to claim 1, wherein the plurality of word line selection units are generated based on a signal for selecting a bank and a signal for controlling a read or write operation of a sense amplifier in the column access command, and the row access command. 2. The semiconductor memory device according to claim 1, wherein a selection of a sense amplifier and a read or write operation are controlled by a signal for selecting a plurality of sense amplifiers selected by one word line. 3. The method according to claim 1, wherein the plurality of word line selection units include a signal for selecting a bank, a signal for controlling a read or write operation of a sense amplifier in the column access command, and a timing signal for activating the sense amplifier. 2. The semiconductor memory device according to claim 1, wherein a selection of a sense amplifier and a read or write operation are controlled by the control circuit. 4. A signal for controlling selection of a sense amplifier and reading or writing operation output from the word line selecting unit, wherein the signal is controlled for each sense amplifier group obtained by dividing a plurality of sense amplifiers selected by the one word line. 4. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is supplied. 5. The semiconductor memory device according to claim 1, wherein the column line selection unit and the write amplifier are arranged in one of the plurality of banks, and the read amplifier is arranged in the other of the plurality of banks. .