JP2000324355A - Dynamic focus circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an inexpensive dynamic focus circuit where no focus deviation is caused even when a deflection width is changed. SOLUTION: The dynamic focus circuit is provided with at least an FBT 1 that generates a high DC voltage to apply a dynamic focus(DF) signal to a grid terminal of a CRT, a coupling capacitor C1 that uses a breeder resistor to divide the high voltage so as to obtain a bias voltage suitable for the CRT and superimposes an AC waveform of the DF signal on the bias voltage, a DF amplifier 2 that outputs the DF signal with a large amplitude suitable for the CRT to the coupling capacitor C1, and with a DC correction circuit 4 that controls a voltage at a ground level side of the breeder resistor so as to obtain the proper bias voltage at the grid terminal on the basis of the DF signal from the DF amplifier 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CRT for a television receiver or a display device, and more particularly to a dynamic focus circuit in a device having a function of changing one of horizontal and vertical deflection widths.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a conventional dynamic focus circuit. A portion surrounded by a broken line is a part of the flyback transformer (FBT) 1, and a bias voltage (a high voltage on the order of several KV) when the dynamic focus signal (DF) is applied to the grid terminal (GT) of the CRT. Only the circuit part that generates it is shown.

In this FBT circuit section, high-voltage windings L1, L
2, L3 and the rectifier diodes D1, D2, D3, Dn generate a high-voltage pulse.
A DC high voltage is obtained on the cathode side of the diode Dn. Further, bleeder resistors R1, VR, R2 are provided between the bleeder resistors and the ground (GND), and a predetermined bias voltage is set at the center of the semi-fixed resistor (VR). A dynamic focus signal amplified via the coupling capacitor C1 is superimposed on this bias voltage and applied to the grid terminal.

[0004] The dynamic focus signal is obtained by adding a horizontal correction signal and a vertical correction signal obtained by mixing a parabolic wave and a sawtooth wave at a certain ratio to each of a horizontal period and a vertical period inputted from a synchronization signal processing circuit (not shown). The sum output is amplified by the dynamic focus amplifier 2 to a large amplitude of several hundred Vpp (peak-to-peak). As described above, this dynamic focus signal is applied to one side (the side other than the semi-fixed resistor VR) of the coupling capacitor.

FIG. 3 shows horizontal and vertical correction signals as:
Only the parabolic component is illustrated for simplicity. The bias voltage and the dynamic focus signal need to have appropriate values determined by the CRT used. Therefore, the parabolic wave, the sawtooth wave, and the bias voltage of the horizontal period and vertical period correction signals are adjusted by CR at the factory adjustment.
Adjustment is made so that the value becomes an appropriate value at the grid terminal of T.

FIG. 4 shows another example of a conventional dynamic focus circuit. As shown in the drawing, this circuit is obtained by connecting a circuit in which a clamp diode Dc and a bias resistor Rc are connected in parallel to the circuit of FIG. 3 to a semi-fixed resistor VR. As described later, the lower end of the waveform of the dynamic focus signal is clamped by the clamp diode Dc and the bias resistor Rc so as to suppress the fluctuation of the bias voltage at the lowermost end.

By the way, recent television receivers have a wide range of display angle of view (16: 9) or (4: 3), and various display devices for personal computers have been conventionally used. It is necessary to display the video signal of the synchronization frequency and the number of pixels. As described above, various deflection widths are displayed on the same CRT, and it is necessary to change the amplitude of the dynamic focus signal in accordance with the deflection width in order to obtain optimum focus in each case.

On the other hand, AC of the dynamic focus signal
When the user performs an operation of changing the deflection width (angle of view), it is easy to realize that the amplitude of the dynamic focus signal is also changed at an appropriate change rate in conjunction with the synchronous signal processing circuit. However, the DC component of the dynamic focus signal has a problem as described below.

FIGS. 5A and 5B are waveform diagrams of voltages at grid terminals. In the actual waveform, the horizontal and vertical components are superimposed, but since it is a linear addition, it is sufficient to consider only one of them. As shown in (a) and (b), the amplitude is expanded by the synchronization signal processing circuit in proportion to the deflection width. At this time, in order to keep the focus on the entire CRT screen at an appropriate value, the following method is used. Thus, the DC potential at the center of the screen (the lowermost end of the parabola wave opened upward) must be maintained so as not to fluctuate. However, when the amplitude of the dynamic focus signal is changed in the configuration of FIG.
As shown in (a), the lowermost end of the parabolic wave fluctuates, and as a result, a problem arises in that the entire tube surface is out of focus.

Even if such a problem exists, conventionally, even if the deflection width changes, the amplitude of the dynamic focus signal is generally kept at a fixed value, or changes in conjunction with the change in the deflection width. Even in such a case, the design shown in FIG. 5A is mainly used without taking any measures, or the design is such that any deviation in focus is allowed. On the other hand, as an example of a circuit configuration of a device requiring relatively high definition, FIG.
There is a configuration shown in FIG. In the circuit of FIG. 4, a semi-fixed resistor (VR)
By clamping the lower end of the waveform of the dynamic focus signal using the center of, the characteristic that the lowermost end does not fluctuate as shown in FIG. 5B is obtained. In the configuration of FIG. 4, between the FBT circuit unit of FIG. 3 and the coupling capacitor,
The clamp diode Dc and the bias resistor Rc are connected in parallel. With this configuration, the deflection width can be changed without a focus shift.

[0011]

However, the circuit configuration of FIG. 4 has a problem of cost. That is, the semi-fixed resistance V
R and the clamp diode Dc are equal to the number K of the FBT circuit unit 1.
FBT because it is dangerous because it is connected to the high voltage part of V
It is necessary to fill with an insulating material built in the circuit unit 1.
However, in general, the FBT is a dedicated component that is provided based on the mass production effect by sharing a built-in component. Therefore, the FBT added with a special specification in which such a clamp diode Dc and a bias resistor Rc are filled with an insulating material.
Were not always readily available at low cost.
For this reason, the configuration of FIG. 4 has a problem in terms of price, which is a major problem in a product field where price competition is fierce. Therefore, an inexpensive circuit countermeasure instead of the configuration in FIG. 4 has been required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a high-definition television receiver or display device having a variable deflection width without changing the deflection width without requiring special specifications for the FBT. It is an object of the present invention to provide an inexpensive dynamic focus circuit which does not cause a focus shift even if it is performed.

[0013]

According to the present invention, a CRT is provided.
Flyback transformer F that generates a DC high voltage to apply a dynamic focus signal to the grid terminal
BT and the high voltage are divided by a bleeder resistor to obtain a CRT.
A coupling capacitor C1 for generating a bias voltage suitable for the above and further superimposing an AC waveform of the dynamic focus signal, and a dynamic focus amplifier 2 which is input to the coupling capacitor and outputs a dynamic focus signal having a large amplitude suitable for a CRT In the dynamic focus circuit including at least a dynamic focus signal DF from the dynamic focus amplifier 2 to control a ground-side voltage of the bleeder resistor to obtain an appropriate bias voltage at the grid terminal GT. It is characterized by including a focus DC correction means 4.

[0014] Preferably, the dynamic focus DC correction means receives a dynamic focus signal from the dynamic focus amplifier and detects an average value of the voltage, and a bias voltage from the average value detector. And a DC inversion amplifying unit 42 for obtaining a DC inversion output by comparing with a ground potential, controlling a voltage on the ground side of the bleeder resistor by an output voltage from the DC inversion amplifying unit 42, and displaying the CRT. When the deflection width of the angle of view changes, the deviation of the DC bias voltage generated in the dynamic focus signal of the grid terminal is corrected.

More preferably, the average value detecting section 41
Is a capacitor C which receives a dynamic focus signal from the dynamic focus amplifier at one end.
5, a resistor R5 connected between the other end of the capacitor C5 and the ground side,
Diode D5 whose cathode side is connected to the common connection point
And a capacitor C6 connected between the anode side and the ground side of the diode D5. An average voltage is output from a common connection point between the diode D5 and the capacitor C6.

More preferably, the DC inverting amplifier 4
Reference numeral 2 denotes a resistor R6 received at one end receiving the average voltage from the average value detection unit 41, and a differential amplifier having the other end of the resistor R6 connected to a negative terminal and a positive terminal grounded. 421, the output side of the differential amplifier 421 and the resistor R
And a resistor R7 connected to the other end of the bleeder resistor 6. The output side of the differential amplifier is connected to the ground side of the bleeder resistor.

More preferably, the bleeder resistor comprises a resistor R1, a semi-fixed resistor VR and a resistor R2 connected in series, and an adjustment terminal of the semi-fixed resistor VR is connected to the grid terminal, and the other of the resistor R2 Is connected to the dynamic focus DC correction means, the combined resistance of the resistor R1 and the resistor up to the adjustment terminal of the semi-fixed resistor VR is Rt, and the semi-fixed resistor VR is
Is the combined resistance of the resistor up to the adjustment terminal of
When u is set, the resistors R6 and R7 are selected so as to satisfy R7 / R6 = (Rt + Ru) / Rt.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a dynamic focus circuit including a dynamic focus DC correction circuit according to the present invention. As shown, in the present invention, a dynamic focus DC correction circuit 4 is newly added to the circuit configuration of FIG.
As shown, the bleeder resistances R1, V
It is added to the ground side (GND) of R and R2.

The dynamic focus DC correction circuit 4 receives the dynamic focus signal DF from the dynamic focus focus amplifier 2 and
The bias voltage (average value of the waveform) is detected and DC-amplified to control the voltage at the lower end (ground side) of the bleeder resistor. As shown in FIG.
The output characteristics shown in FIG.

FIG. 2 shows the dynamic focus D of FIG.
FIG. 3 is a detailed configuration diagram as one embodiment of a C correction circuit. As shown, the dynamic focus DC correction circuit 4 of the present invention is composed of two blocks each including an average value detection unit 41 and a DC inversion amplification unit 42. Average value detector 41
Inputs a dynamic focus signal from the dynamic focus amplifier 2 and outputs a capacitor D5 and a resistor R5.
, The bias is reset to 0 (V). In the illustrated waveform of the connection point between C5 and R5, the potential of "V", which is a potential portion equal to or lower than GND (a portion equal to or lower than 0 (V)) reflects necessary bias voltage information.
And a diode D5 connected to the connection point of R5 and R5 in the direction shown in the figure, and a capacitor C6 connected to the other end of the diode D5 and GND, to detect and hold.

Next, in the DC inverting amplifier 42, the "V" voltage is input to the negative terminal on the input side of the differential amplifier 421 via the resistor R6, and is compared with the GND potential input to the positive terminal. , A DC inverted output voltage is obtained by the resistors R6 and R7. Here, the resistances R6 and R7 have a relationship satisfying R7 / R6 = (Rt + Ru) / Rt (1) between each resistance value Rt and Ru from both ends of the bleeder resistance in the FBT to the semi-fixed resistance VR. The resistance values of the resistors R6 and R7 are selected so that In this case, the correction error becomes smaller when the center of the semi-fixed resistor VR is closer to the VR position where the final dynamic focus adjustment is completed.

With this configuration, when the "V" voltage fluctuates due to the adjustment of the amplitude of the dynamic focus signal, the lower end voltage of the bleeder resistor is corrected, and the waveform of the waveform shown in FIG. As a result, even if the deflection width is changed, it is possible to obtain a dynamic focus voltage without a focus shift.

[0023]

According to the present invention, in a conventional CRT television receiver or display device, in many cases, the display field angle (deflection width in the case of CRT) is diversified in principle and dynamic Even if a focus shift occurred, he just accepted it. However, as the definition of the display device has advanced, this focus shift has become unacceptable. According to the present invention, when varying the deflection width, the DC shift of dynamic focus can be corrected using the conventional FBT as it is, and it is possible to cope with high definition.

[Brief description of the drawings]

FIG. 1 shows a dynamic focus circuit including a dynamic focus DC correction circuit according to the present invention.

FIG. 2 is a detailed configuration diagram as one embodiment of a dynamic focus DC correction circuit of FIG. 1;

FIG. 3 is an example of a conventional dynamic focus circuit.

FIG. 4 is another example of a conventional dynamic focus circuit.

FIGS. 5A and 5B are waveform diagrams of grid terminal voltages.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 flyback transformer (FBT) 2 dynamic focus amplifier 3 adder 4 dynamic focus DC correction circuit 41 average value detector 42 DC inverting amplifier

Claims (5)

[Claims] A flyback transformer for generating a DC high voltage for applying a dynamic focus signal to a grid terminal of the CRT; a high voltage divided by a bleeder resistor to generate a bias voltage suitable for a CRT; A dynamic focus circuit including at least a coupling capacitor for superimposing an AC waveform of a focus signal and a dynamic focus amplifier input to the coupling capacitor and outputting a dynamic focus signal having a large amplitude suitable for a CRT; Dynamic focus DC correction means for controlling a ground-side voltage of the bleeder resistor to obtain an appropriate bias voltage at the grid terminal based on a dynamic focus signal from an amplifier. Dynamic focus circuit for the butterflies. 2. The dynamic focus DC correction unit receives a dynamic focus signal from the dynamic focus amplifier, detects an average value of the voltage, and detects an average bias voltage from the average value detection unit. And a DC inverting amplifier for obtaining a DC inverting output by comparing with a ground potential, controlling a grounding voltage of the bleeder resistor by a DC inverting output voltage from the DC inverting amplifier, and displaying the CRT. 2. The dynamic focus circuit according to claim 1, wherein when the deflection width of the angle of view changes, a deviation of a DC bias voltage generated in a dynamic focus signal at the grid terminal is corrected. 3. The capacitor according to claim 1, wherein the average value detecting unit is configured to receive a dynamic focus signal from the dynamic focus amplifier at one end of the capacitor (C5), and connect the other end of the capacitor (C5) to a ground side. , The capacitor (C5) and the resistor (R5).
5) A diode (D5) having a cathode connected to a common connection point of the diode (D5), and a capacitor (C6) connected between an anode and a ground of the diode (D5). 3. The dynamic focus circuit according to claim 2, wherein an average voltage is output from a common connection point between the first and second capacitors and the capacitor (C6). 4. The DC inverting amplifier includes a resistor (R6) received at one end receiving the average voltage from the average value detector, and a negative terminal connected to the other end of the resistor (R6). And a resistor (R7) connected to the output side of the differential amplifier and the other end of the resistor (R6). 3. The dynamic focus circuit according to claim 2, wherein an output side is connected to a ground side of the bleeder resistor. 5. The bleeder resistor includes a resistor (R1), a semi-fixed resistor (VR), and a resistor (R2) connected in series, and an adjustment terminal of the semi-fixed resistor (VR) is connected to the grid terminal. In the configuration in which the other end of the resistor (R2) is connected to the dynamic focus DC correction means, the combined resistance of the resistor (R1) and the resistor up to the adjustment terminal of the semi-fixed resistor (VR) is represented by Rt. Assuming that the combined resistance of the resistor (R2) to the adjustment terminal of the semi-fixed resistor (VR) and the resistor (R2) is Ru, the resistor (R6) and the resistor (R7) are R7 / R6 = (Rt + Ru 5) The dynamic focus circuit according to claim 4, wherein the dynamic focus circuit is selected so as to satisfy / Rt.