JP2000332108A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] (Problem corrected) [PROBLEMS] A metal having a high barrier property against a metal such as copper (Cu) even in a high aspect ratio trench-embedded wiring pattern in which high step coverage of a barrier metal cannot be expected. Provided are a wiring and a method for forming the wiring. SOLUTION: On a base substrate including a semiconductor substrate 1, a diffusion preventing film 7 for suppressing at least metal diffusion, a third insulating film 8 in contact with an upper surface of the diffusion preventing film, and an upper surface of the diffusion preventing film as a bottom surface. A wiring groove 10 having the insulating film on a side surface, a metal wiring film 13 embedded in the wiring groove,
A barrier metal provided between the wiring groove and the metal wiring film; and a phosphorus (P) doped layer 11 provided on a surface of the insulating film on a side surface of the wiring groove.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a metal wiring having a trench filling structure of a semiconductor device and a method of forming the same.

[0002]

2. Description of the Related Art In a wiring forming technique using a metal having a large diffusion coefficient in an insulating film or a substrate, such as copper (Cu), as a main wiring material, in particular, a metal to be a wiring film is used. However, it is important to prevent diffusion into the insulating film and the substrate. Therefore, conventionally, diffusion of these metals into an insulating film or a substrate has been prevented by forming a barrier metal below these metal wiring films.

FIG. 2 is a longitudinal sectional view showing a process of manufacturing a metal wiring of a semiconductor device according to the prior art. First,
As shown in FIG. 2A, a first insulating film 2 is formed on a semiconductor substrate 1, and a lower wiring 4 having a trench filling structure is formed in the first insulating film 2. Further, for example, plasma CVD
(Chemical Vapor Deposition
By the n) method, an etching stopper 5 made of a silicon nitride film or the like, a second insulating film 6 made of a silicon oxide film or the like, a diffusion prevention film 7 made of a silicon nitride film or the like, and a third insulating film 8 made of a silicon oxide film or the like are formed. Form sequentially.

[0004] Then, as shown in FIG. 2 (b), a connection hole 9 reaching the etching stopper 5 on the lower wiring 4 is formed by a reactive ion etching method with a third insulating film 8, a diffusion preventing film 7 and a second insulating film. An opening is formed in the film 6. Then, FIG. 2 (c)
As described above, the third insulating film 8 is etched by the reactive ion etching method to open the wiring groove 10. At this time, the diffusion prevention film 7 and the etching stopper 5 are not removed.

Subsequently, as shown in FIG. 2D, the etching stopper 5 exposed on the lower wiring 4 is removed by an anisotropic etch-back method to expose the surface of the lower wiring 4. Thereafter, a barrier metal 12 such as a tantalum nitride (TaN) film and a metal wiring film 13 such as Cu are deposited by a sputtering method, and subsequently, the metal wiring film 13 is reflowed by excimer laser irradiation to form the connection holes 9 and the wiring grooves 10. Buried. Further, the barrier metal 12 and the metal wiring film 13 on the third insulating film 8 are formed by CMP (Chemical Mech).
By removing by an electrical polishing method, a trench-buried structure wiring using a metal such as Cu as a main wiring material is formed on the lower wiring 4.

[0006]

However, the above-described conventional metal wiring having a trench filling structure of a semiconductor device and a method of forming the same have the following problems. In order to reduce the interlayer capacitance and the capacitance between wires, which are essential requirements for high-speed operation of a semiconductor device, the aspect ratio of a wiring groove or a connection hole may be increased. Alternatively, due to the instability of the etching process, the shape of the connection hole may be inversely tapered. In such cases, there is a problem that the step coverage of the barrier metal is reduced. In particular, the thickness of the barrier metal is remarkably reduced in the side wall portions of the wiring grooves and the connection holes, so that the barrier property to the metal wiring film serving as a barrier metal may be impaired. As a measure for solving such a problem, a method of depositing a thick barrier metal in order to secure a necessary minimum film thickness in a side wall portion of a wiring groove or a connection hole can be considered. However, according to this method, there is a problem that the ratio of the metal wiring film occupying in the wiring grooves and connection holes having a low aspect ratio mixed in the same semiconductor device is reduced, and the specific resistance of the wiring is increased. Alternatively, dishing or erosion of the metal wiring film is likely to occur because the amount of polishing of the barrier metal in the trench wiring process by CMP increases.
There arises a problem that a variation in wiring resistance in a wafer surface becomes large or a process margin becomes narrow. Therefore, as another solution, there is a method of using a PSG film or BPSG film containing phosphorus (P), which is known to have an effect of trapping a metal such as Cu to suppress diffusion, as an insulating film. According to this method, even if the barrier metal is thinned, the metal in the wiring film can be
The effect of suppressing diffusion into an insulating film or a substrate can be obtained. However, PSG films and BPSG films have problems such as higher relative permittivity than silicon oxide films, high hygroscopicity, and easy occurrence of defects such as scratches in CMP when forming trench embedded wiring. Disadvantages in terms of performance, long-term reliability, manufacturing yield, and the like of the semiconductor device.
For this reason, the above-mentioned problem cannot be fundamentally solved.

SUMMARY OF THE INVENTION The present invention has been made in view of such problems in the prior art. Even in a wiring pattern with a trench-embedded structure having a high aspect ratio in which a high step coverage of a barrier metal cannot be expected, a metal such as Cu can be used. It is an object of the present invention to provide a metal wiring having a high barrier property and a method for forming the same.

[0008]

According to a first aspect of the present invention for solving the above-mentioned problems, a diffusion preventing film for suppressing at least metal diffusion and an upper surface of the diffusion preventing film are provided on an underlying substrate including a semiconductor substrate. An insulating film, a wiring groove having an upper surface of the diffusion prevention film as a bottom surface, and a wiring groove having the insulating film on a side surface, a metal wiring film embedded in the wiring groove, and between the wiring groove and the metal wiring film. A semiconductor device comprising: a provided barrier metal; and a P-doped layer provided on a surface of the insulating film on a side surface of the wiring groove. As described above, according to the semiconductor device of the first invention of the present application, the metal is diffused on the surface of the insulating film on the side of the wiring groove in contact with the barrier metal on the underlying substrate in which the lower wiring is formed on the semiconductor substrate. Is provided. In addition, a diffusion prevention film for suppressing metal diffusion is provided on a bottom surface of a wiring groove in contact with a barrier metal of a base substrate having a lower wiring formed on a semiconductor substrate. Therefore, the step coverage of the barrier metal is reduced due to a higher aspect ratio or a deteriorated shape of the wiring groove or the connection hole that can be formed by extending the wiring groove, and the barrier is formed at the side wall or the bottom of the wiring groove or the connection hole. Even when the metal is thinned, diffusion of the metal in the metal wiring film provided on the surface of the barrier metal into the insulating film and the substrate can be suppressed. Further, it is possible to prevent characteristic deterioration such as leakage between wirings and pn junction leakage of the semiconductor device.

A second invention of the present application is the semiconductor device according to the first invention of the present application, wherein the metal wiring film contains Cu. Therefore, according to the semiconductor device of the second invention of the present application, even when the barrier metal is thinned at the side wall or the bottom of the wiring groove or the connection hole, Cu in the metal wiring film provided on the surface of the barrier metal is reduced. ,
Diffusion into an insulating film or a substrate can be suppressed, and characteristic deterioration such as leakage between wirings and pn junction leakage of a semiconductor device can be prevented. Furthermore, C having a low resistance value
By using a metal wiring film containing u, a semiconductor device which operates at high speed can be realized.

The third invention of the present application is the semiconductor device according to the first or second invention of the present application, wherein the P-doped layer has a depth of 10 to 25 nm from a side surface of the wiring groove and a P concentration of 10 to 25 nm. 1 × 10 ²⁰ to 1 × 10 ²² atoms / c
characterized in that it is in the range of m ^3. Therefore, according to the semiconductor device of the third invention of the present application, it is possible to sufficiently exhibit the effect of P that suppresses diffusion by trapping metal.

According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects of the present invention, the diffusion preventing film is made of a silicon nitride film or a silicon oxynitride film. I do. Therefore, according to the semiconductor device of the fourth invention of the present application, it is possible to exhibit an excellent effect of suppressing the diffusion of the diffusion preventing film with respect to a metal such as Cu.

The fifth invention of the present application also includes a step of forming a diffusion prevention film for suppressing at least metal diffusion on a base substrate including a semiconductor substrate, and a step of forming an insulating film on the diffusion prevention film. Opening a wiring groove reaching the diffusion prevention film in a predetermined region of the insulating film; introducing P to an exposed surface of the insulating film; and forming a recess of the wiring groove on the base substrate. A method for manufacturing a semiconductor device, comprising: a step of forming a barrier metal so as to remain; and a step of forming a metal wiring film on the barrier metal and burying the wiring groove. As described above, according to the method for manufacturing a semiconductor device of the fifth invention of the present application, P for suppressing metal diffusion is introduced in advance into the surface of the insulating film on the side of the wiring groove in contact with the barrier metal, and the P-doped layer is formed. Is formed. Further, a diffusion prevention film for suppressing metal diffusion is formed on the bottom surface of the wiring groove in contact with the barrier metal on the base substrate having the lower wiring formed on the semiconductor substrate. Therefore, the step coverage of the barrier metal is reduced due to a higher aspect ratio or a deteriorated shape of the wiring groove or the connection hole that can be formed by extending the wiring groove, and the barrier is formed at the side wall or the bottom of the wiring groove or the connection hole. Even when the metal is thinned, it is possible to manufacture a semiconductor device that suppresses diffusion of the metal in the metal wiring film provided on the surface of the barrier metal into the insulating film and the substrate. Further, in the semiconductor device manufactured in this way, the leakage between wirings and the p
Characteristic deterioration such as n-junction leakage can be prevented.

A sixth invention of the present application is the method for manufacturing a semiconductor device of the fifth invention of the present application, wherein the metal wiring film contains Cu. Therefore, according to the method of manufacturing a semiconductor device of the sixth invention of the present application, even when the barrier metal is thinned at the side wall or the bottom of the wiring groove or the connection hole, the metal wiring film provided on the surface of the barrier metal can be formed. A semiconductor device that suppresses the diffusion of Cu into an insulating film or a substrate can be manufactured, and characteristic deterioration such as inter-wiring leak and pn junction leak of the semiconductor device manufactured in this way can be prevented. be able to. Further, by using a metal wiring film containing Cu having a low resistance value, a semiconductor device which operates at high speed can be realized.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the fifth or sixth aspect of the present invention, wherein
Is characterized by performing a heat treatment in a gas containing at least P. Therefore, according to the method for manufacturing a semiconductor device of the seventh invention of the present application, even if the wiring groove or the connection hole that can be formed by extending into the wiring groove has a high aspect ratio or a deteriorated shape,
P can be introduced uniformly to the surface of the insulating film on the side of the wiring groove or the connection hole that can be formed to extend to the wiring groove, and without damaging the surface of the insulating film.

According to an eighth aspect of the present invention, in the method for manufacturing a semiconductor device according to the seventh aspect of the present invention, the gas containing P is phosphine (PH ₃ ).
Therefore, according to the manufacturing method of the semiconductor device of the invention of the present application eighth, by performing spreading using a PH ₃ that is conventionally done, it can be carried out step easily and effectively introducing a P Become.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to the seventh or eighth aspect of the present invention, the heat treatment is performed at a temperature in the range of 300 ° C. to 500 ° C. Therefore, according to the method of manufacturing a semiconductor device of the ninth invention of the present application, a temperature of 300 ° C. or more at which P diffuses most effectively into the insulating film and a temperature of 500 ° C. or less that does not damage the underlying substrate. Can be introduced in the range of.

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the fifth to ninth aspects of the present invention, the diffusion preventing film is made of a silicon nitride film or a silicon oxynitride film. It is characterized by. Therefore, according to the method for manufacturing a semiconductor device of the tenth invention of the present application, it is possible to exhibit an excellent effect of suppressing the diffusion of the diffusion prevention film with respect to a metal such as Cu.

[0018]

Next, a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a vertical sectional view showing a manufacturing process of a metal wiring of a semiconductor device according to an embodiment of the present invention.

First, by the same process as in the prior art,
A connection hole and a wiring groove are formed. That is, as shown in FIG. 1A, a first insulating film 2 made of a silicon oxide film is formed on a semiconductor substrate 1 and a lower layer is formed on the first insulating film 2 by a reactive ion etching method using a resist as a known technique. The wiring groove 3 is opened. Then, a film for the lower wiring 4, for example, a barrier metal and a Cu film are sequentially deposited by a sputtering method or a plating method to bury the lower wiring groove 3, and then the lower wiring 4 for the lower wiring 4 on the first insulating film 2 is formed by the CMP method. The film is removed to form a lower wiring 4 having a trench filling structure. Further, for example, by a plasma CVD method, an etching stopper 5 made of a silicon nitride film having a thickness of 10 to 50 nm, a second insulating film 6 made of a silicon oxide film having a thickness of 400 to 800 nm, and a thickness of 10 to 50 nm made of a silicon nitride film. And a third insulating film 8 made of a silicon oxide film and having a thickness of 400 to 800 nm. The main material of the first insulating film 2, the second insulating film 6, and the third insulating film 8 is not limited to the silicon oxide film, and silicon (F) having a small relative dielectric constant to which fluorine (F) is added. An oxyfluoride film or the like may be used.

Then, as shown in FIG. 1B, a connection hole 9 reaching the etching stopper 5 on the lower wiring 4 is formed by a reactive ion etching method using a resist as a mask.
Openings are formed in the insulating film 8, the diffusion preventing film 7, and the second insulating film 6. At this time, it is desirable to perform two-stage etching.
That is, the third insulating film 8 is initially formed under the condition that the silicon oxide film and the silicon nitride film are etched at the same rate.
Then, the diffusion preventing film 7 is completely etched, and then the etching rate of the silicon nitride film is changed to a much lower etching condition than the etching rate of the silicon oxide film, and the second insulating film 6 is removed so that the etching stopper 5 is not removed. Is desirably etched.

Next, as shown in FIG. 1C, the third insulating film 8 is etched by a reactive ion etching method using a resist as a mask to open a wiring groove 10. On this occasion,
Etching with high selectivity to silicon nitride film,
The diffusion prevention film 7 and the etching stopper 5 are not removed. The reason why the etching stopper 5 on the lower wiring 4 is left without being removed is that it is necessary to prevent oxidation of the lower wiring 4 due to oxygen (O2) plasma when removing the resist serving as an etching mask. Through the above steps, the connection hole 9 and the wiring groove 10 are formed.

Next, P is introduced into the exposed surfaces of the second insulating film 6 and the third insulating film 8 to form a P-doped layer 11. P has an effect of trapping a metal such as Cu to suppress diffusion, as is known in a PSG film or a BPSG film. This P-doped layer 11 is an insulating material outside a barrier metal 12 to be formed later. It will function as a second diffusion prevention layer for metals such as Cu in the film and the silicon substrate. In order to sufficiently exhibit this effect, the P-doped layer 1
1 a depth of 10nm or more, P concentration 1 × ^{10 2} 0 ~1 ×
It is desirable to be in the range of 10 ²² atoms / cm ³ . Here, the P-doped layer 11 is also formed on the outermost surface outside the wiring groove 10. However, if a high concentration of P is present on the surface of the third insulating film 8, the P-doped layer 11 may be formed in a conventional PSG film or BPSG film. The same problem occurs. That is, problems such as a higher relative dielectric constant than the silicon oxide film, a higher hygroscopicity, and a tendency such as a defect such as a scratch to be easily generated in the CMP for forming the trench embedded wiring occur. Therefore, in the subsequent step of removing the etching stopper 5 by the anisotropic etch-back method to expose the surface of the lower wiring 4, the wiring groove 10 is removed.
It is also necessary to remove the P-doped layer 11 formed on the outermost surface of the substrate at the same time. For this reason, it is desirable that the depth of the P-doped layer 11 is 25 nm or less. In this step, since the surface of the lower wiring 4 is covered with the etching stopper 5 made of a silicon nitride film that does not easily react with P, it is protected without reacting with P. The main material of the etching stopper 5 is not limited to the silicon nitride film. Like the silicon nitride film, a material having an effect of suppressing the diffusion of P and oxygen and having a high etching selectivity with the silicon oxide film, for example, silicon An oxynitride film or the like may be used. The step of forming a P-doped layer 11, the semiconductor substrate 1, gas containing PH _3, for example, PH ₃ and a mixed gas of argon (Ar) and nitrogen _{(N 2),.} 10 to
By performing a heat treatment at 100 Torr, 300 to 500 ° C. for about 30 minutes, the second insulating film 6 and the third insulating film 8 are formed.
It is desirable to use a method of diffusing P to the surface of the substrate.

Subsequently, as shown in FIG. 1D, the exposed etching stopper 5 is removed by an anisotropic etch-back method to expose the surface of the lower wiring 4. At this time, the P-doped layer 11 formed on the outermost surface of the wiring groove 10 is also removed at the same time. Finally, the barrier metal 12 and the metal wiring film 13 are buried in the connection holes 9 and the wiring grooves 10 by the same process as in the conventional technique, thereby forming a trench buried structure wiring. That is, the barrier metal 12 having a thickness of, for example, a TaN film having a thickness of 10 to 100 nm C. Deposited by magnetron sputtering or CVD, and a thickness of 40
Metal wiring film 13 of, for example, Cu having a thickness of 0 to 1000 nm
To D. C. The connection holes 9 and the wiring grooves 10 are buried by depositing using a method such as magnetron sputtering, CVD, or plating. And 300 to 400 in a non-oxidizing atmosphere.
The heat treatment is performed at about 30 ° C. for about 30 minutes to stabilize the metal wiring film 13. Subsequently, the barrier metal 12 and the metal wiring film 13 on the third insulating film 8 are removed by a CMP method or the like. Through the above steps, a trench-buried structure wiring using a metal such as Cu as a main wiring material is formed.

As described above, according to the semiconductor device and the method of manufacturing the same according to the embodiment of the present invention, the P-doped layer 11 having the effect of suppressing diffusion of metal such as Cu is formed on the outer side surface of the barrier metal 12. Existing. Further, a diffusion preventing film 7 made of a silicon nitride film having a diffusion suppressing effect on metal such as Cu also exists on the bottom surface of the wiring groove 10 outside the barrier metal 12. For this reason, if the aspect ratio of the wiring groove 10 or the connection hole 9 is increased or the shape is deteriorated, the step coverage of the barrier metal 12 is reduced, and the barrier metal 12 is partially thinned at the side wall of the wiring groove 10 or the connection hole 9. Also in this case, diffusion of a metal such as Cu can be suppressed, so that the heat resistance becomes higher than that of the conventional method. As a result, it is possible to prevent characteristic deterioration such as leakage between wirings and pn junction leakage of the semiconductor device.

In the embodiment described above, the silicon nitride film is used as the diffusion preventing film 7, but the invention is not limited to this. Like the silicon nitride film, a material having an effect of suppressing diffusion of metal such as Cu and having a high etching selectivity with respect to the silicon oxide film, for example, a silicon oxynitride film may be used as the diffusion prevention film 7. . Further, although a TaN film is used as the barrier metal 12, the present invention is not limited to this, and titanium nitride (TiN), tantalum (Ta), tungsten (W), tungsten nitride (WN), or the like may be used. . In addition, the metal wiring film 1
Although a Cu film was used as 3, the film is not limited to this, and a film containing Cu or another metal having a large diffusion coefficient in an insulating film or a substrate, for example, a film containing gold (Au) is used. You may use it. Further, although a barrier metal and a Cu film are used as the lower wiring 4, the present invention is not limited to this, and another metal, silicon, silicide, or the like may be used.

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, the diffusion preventing property for the metal such as Cu can be maintained without depending on the aspect ratio and the shape of the wiring groove or the connection hole. A semiconductor device having high heat resistance and excellent leakage characteristics and a method for manufacturing the same can be provided.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a manufacturing process of a metal wiring of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a longitudinal sectional view of a manufacturing process of a metal wiring of a semiconductor device according to a conventional technique.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 first insulating film 3 lower wiring groove 4 lower wiring 5 etching stopper 6 second insulating film 7 diffusion prevention film 8 third insulating film 9 connection hole 10 wiring groove 11 P-doped layer 12 barrier metal 13 metal wiring film

Continued on the front page F term (reference) 5F033 HH11 HH22 JJ01 KK11 MM02 MM12 MM13 PP06 PP15 PP27 QQ09 QQ13 QQ23 QQ31 QQ37 QQ48 QQ60 QQ65 QQ79 RR06 RR08 TT03 TT07 WW02 WW03 B01B04 BD05B01 BD04

Claims (10)

[Claims] 1. A base substrate including a semiconductor substrate, a diffusion preventing film for suppressing at least metal diffusion, an insulating film in contact with an upper surface of the diffusion preventing film, an upper surface of the diffusion preventing film as a bottom surface, and A wiring groove having a film on a side surface, a metal wiring film embedded in the wiring groove, a barrier metal provided between the wiring groove and the metal wiring film, and an insulating film surface on a side surface of the wiring groove And a phosphorus (P) -doped layer provided on the semiconductor device. 2. The semiconductor device according to claim 1, wherein said metal wiring film contains copper (Cu). 3. The P-doped layer has a depth of 10 to 25 nm from a side surface of the wiring groove and a P concentration of 1 × 10 ^20.
3. The semiconductor device according to claim 1, wherein the range is from about 1 × 10 ²² atoms / cm ^{3. 4} . 4. The semiconductor device according to claim 1, wherein the diffusion preventing film is made of a silicon nitride film or a silicon oxynitride film.
The semiconductor device according to claim 3. 5. A step of forming, on a base substrate including a semiconductor substrate, a diffusion prevention film for suppressing at least diffusion of metal; a step of forming an insulating film on the diffusion prevention film; A step of opening a wiring groove reaching the diffusion prevention film in a region; a step of introducing P on the surface of the exposed portion of the insulating film; and forming a barrier metal on the base substrate so as to leave a concave portion of the wiring groove. And forming a metal wiring film on the barrier metal and burying the wiring groove. A method of manufacturing a semiconductor device, comprising: 6. The method according to claim 5, wherein the metal wiring film contains Cu. 7. The method according to claim 7, wherein the step of introducing P comprises at least P
7. The method according to claim 5, wherein the heat treatment is performed in a gas containing: 8. The gas containing P is phosphine (P
8. The method for manufacturing a semiconductor device according to claim 7, wherein H ₃ ). 9. The method according to claim 7, wherein the heat treatment is performed at a temperature in a range of 300 ° C. to 500 ° C. 10. The method of manufacturing a semiconductor device according to claim 5, wherein said diffusion prevention film is made of a silicon nitride film or a silicon oxynitride film.