JP2000332120A - Semiconductor integrated circuit - Google Patents

Abstract

[PROBLEMS] To connect a plurality of field effect transistors to a power supply line and a ground line in a semiconductor integrated circuit in which a plurality of field effect transistors are arranged in a row and connected by wiring to form a logic circuit. In this case, the wiring can be easily connected without changing the wiring layer with a short wiring length, the wiring resistance can be reduced and the circuit configuration can be simplified, and the reliability of the circuit can be improved and the operation can be stabilized and speeded up. Provided is a semiconductor integrated circuit that can be achieved. SOLUTION: In a semiconductor integrated circuit in which a plurality of field effect transistors are arranged in a row and connected to each other by wiring to constitute a logic circuit, a parallel first field effect transistor row 4 and a second field effect transistor row 5, a first wiring 1 disposed between the first field-effect transistor row 4 and the second field-effect transistor row 5, and a first wiring with the first field-effect transistor row 4 interposed therebetween. 1 and a third wiring 3 parallel to the first wiring 1 with the second field-effect transistor row 5 interposed therebetween, wherein the first wiring 1 has a first potential. And the second wiring 3 and the third wiring 3 have a second potential.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit in which a plurality of field effect transistors are arranged in a row and connected to each other to form a logic circuit.

[0002]

2. Description of the Related Art When designing a large-scale integrated circuit, it is often designed using a standard cell system. Conventional standard cells are designed with a constant height in all cells. For this reason, as shown in FIG. 6, the area where the standard cell column 61 including the plurality of standard cells 63 is arranged can be clearly separated from the wiring area 62, and automatic design by CAD becomes easy. In this case, as shown in FIG. 7, the power supply line 71 and the P-channel MOSFET
T (PMOS) column 72, N-channel MOSFET (NM
OS) Column 73 and ground wiring 74 are arranged in this order,
A power supply is connected to and supplied to the cell (conventional example 1).

More specifically, each PMOS of a PMOS column 72 composed of a diffusion layer is connected to a power supply wiring 71 composed of a first metal layer by a power supply wiring branch line 75 composed of a first metal layer via a contact region 76. The respective NMOSs of the NMOS column 73 formed of a diffusion layer are connected to a ground wiring 74 formed of a first metal layer via a power supply wiring branch line 77 formed of a first metal layer via a contact region 78. An input line 79 made of polycrystalline silicon is connected to each PMOS and NMOS.

Japanese Patent Application Laid-Open No. Hei 8-213470 discloses another example of a power supply wiring having a layout of a standard cell system. As shown in FIG.
By arranging the MOS column 102, the power supply line 101, the ground line 104, and the NMOS column 103 in this order, as shown in FIG. 9, the power supply can be connected without designing the standard cells 93 at the same height. A configuration is adopted in which a gap region 94 generated by upper and lower irregularities of the standard cell row 91 is used as a wiring region in addition to the conventional wiring region 92 (conventional example 2).

More specifically, as shown in FIG. 10, each PMOS of a PMOS row 102 composed of a diffusion layer is connected to a first metal layer of a power supply wiring 105 composed of a first metal layer via a contact region 106. Power supply wiring 10 composed of layers
1 and each N of the NMOS column 103 composed of a diffusion layer.
The MOS is connected to the ground wiring 104 made of the first metal layer by the ground wiring branch line 107 made of the first metal layer via the contact region 108, and the PMOS column 1
The input line 109 made of polycrystalline silicon is connected to the 02 and the NMOS column 103. The gap region 110 is used as a wiring region, for example, the wiring 1 formed of a metal layer.
11 denotes a PMOS 102 via a contact region 112.
It is connected to the.

Japanese Unexamined Patent Publication No. Hei 9-199608 discloses another example of power supply wiring of a gate array type layout. As shown in FIG.
22 and a ground wiring 124 in the NMOS column 123, and the unused P
The MOS gate and the diffusion layer are connected to the ground wiring 124, and the unused NMOS gate and the diffusion layer are connected to the power supply wiring 1.
21 is connected to the power supply wiring 121.
Further, it is possible to suppress the fluctuation of the voltage value generated in the ground wiring 124 (conventional example 3).

More specifically, as shown in FIG. 12, each PMOS of a PMOS row 122 composed of a diffusion layer is connected to a first metal layer via a power supply wiring branch line 125 composed of a first metal layer via a contact region 126. Power supply wiring 12 composed of layers
1 and each N of an NMOS column 123 composed of a diffusion layer.
The MOS is connected to the ground wiring 124 made of the first metal layer via a power supply wiring branch line 127 made of the first metal layer via the contact region 128, and each of the PMOS and NMOS is made of polycrystalline silicon. The input line 129 is connected.

In the gate array, the unused M
Since the ratio of the OS is small, and even if an unused MOS is not connected to the power supply wiring or the ground wiring, there is no fatal effect on the operation of the circuit, so this is an effective wiring method for the purpose of stabilizing the operation of the gate array. .

[0009]

A normal PMOS is turned on when the gate voltage is set to 0 volt as the ground voltage, and when the source voltage is set to V volt as the power supply voltage, the drain voltage is set to V volt. However, when the source voltage is set to 0 volt as shown in FIG. 14, the drain voltage cannot be lowered below Vth volt which is the threshold voltage of the MOS.

Similarly, a normal NMOS is turned on when the gate voltage is set to V volt, and the drain voltage is set to 0 volt when the source voltage is set to 0 volt.
As shown in FIG. 5, when the source voltage is set to V volts, the drain voltage cannot be higher than (V-Vth) volts. Usually, the threshold voltage Vth is about 0.3 volt to 0.5 volt.

In a normal CMOS circuit or the like, the PMOS is connected to only the power supply and the NMOS is connected to only the ground so that the above-mentioned voltage change does not occur. For example, FIG.
Indicates a CMOS logic circuit of Y = A + B, and PM
The OSs 181, 182, 183 are connected only to the power supply Vdd, and the NMOSs 184, 185, 186 are connected only to the ground Vss.

DTMOS (Dyn)
Amic Threshold MOS (MOS) is a MOS that can dynamically control the threshold voltage Vth by controlling the voltage of the back gate.

More specifically, the DTMOS has a structure in which a well is formed separately for each transistor, and the well and the gate of the corresponding transistor are connected. Normally, the power supply voltage is used at about 0 V to 5 V. According to this configuration, the back gate voltage is controlled by the back gate effect, and the DTMOS transistor is turned on and off.
Since the threshold voltage Vth changes at the time of F, the threshold voltage V at the drain electrode of the transistor is apparently changed.
There is no potential drop for th.

Here, the difference in characteristics between MOS and DTMOS will be described.

First, the point that the MOS characteristics depend on the back gate voltage Vbg will be described with reference to FIG.

When the back gate voltage Vbg = 0V,
When the back gate voltage Vbg = 0.5 V, the MOS
The relationship between the gate voltage Vg and the drain current Id of FIG.
As shown in (a), each threshold voltage Vth
(0), Vth (0.5), Vth (0.5)
Becomes 0 V or less.

As shown in FIG. 20C, when the source voltage Vs = Vdd of the MOS, the drain voltage Vd = V
When dd−Vth (0), Vd = Vth (0), and the drain current Id = 0. For this reason, the drain voltage Vd cannot be higher than Vdd-Vth.

On the other hand, in the case of DTMOS, FIG.
As shown in (d), when the gate voltage Vg = Vdd, the back gate voltage Vbg = Vdd. Therefore, FIG.
As shown in (a), the back gate voltage Vbg is set to 0.5
If it is controlled to about V, the threshold voltage Vth
(0.5) becomes 0 V or less, and no threshold occurs. As shown in FIG. 20E, the gate voltage Vg = 0
In this case, the DTMOS has the same characteristics as the normal MOS, and there is no fear of leakage current.

That is, the NMOS which is the DTMOS is
As shown in FIG. 16, when the source voltage is 0 volt,
The drain voltage does not change and becomes 0 volt. The DTMOS PMOS has a source voltage of V
When set to volts, the drain voltage will be at V volts. Therefore, in the circuit using DTMOS, the above-described normal MO is used.
There is no connection restriction as in the case of S, and no problem occurs when the PMOS and NMOS are connected to either the power supply or the ground.

For example, FIG. 19 shows the same Y = A + as FIG.
An example is shown in which the logic circuit B is constituted by DTMOS. In this case, the PMOS and NMOS can be connected to either the power supply or the ground.
191 and NMOS 194 are connected to a power supply Vdd, and PM
A configuration in which the OS 192 and the NMOS 193 are connected to the ground Vss can be employed. As a result, the circuit using the normal MOS shown in FIG. 18 requires six MOSs to form the same logic circuit, but the DT shown in FIG.
In a circuit using MOS, it is possible to configure the circuit with four MOSs.

In the case of the first conventional example, as shown in FIG. 7, a power supply line 71 and a PMOS 72 and a ground line 7 are connected.
4 and the NMOS 73 are adjacent to each other.

In a normal MOS circuit, the PMOS is connected only to the power supply line and the NMOS is connected only to the ground line.
Each can be connected with short wiring.

However, in the circuit using the DTMOS, both the PMOS and the NMOS are connected to the power supply wiring and the ground wiring. Therefore, when connecting the PMOS to the ground wiring, it is necessary to provide a long ground wiring branch line 83 to the ground wiring 74 and connect the PMOS to the PMOS 72 via the contact region 84 as shown in FIG. Similarly, NMOS
Is connected to the power supply wiring, a long power supply wiring branch 81 is provided in the power supply wiring 71, and N is connected through the contact region 82.
It is necessary to connect to MOS73. Therefore, DTMOS
In the circuit using, since long wiring is required, the operation of the circuit becomes slow or unstable. In addition, it becomes an obstacle for performing other wiring.

In the case of the above conventional example 2, the normal MOS
In the circuit described above, the PMOS can be connected to the power supply wiring and the NMOS can be connected to the ground wiring with short wirings, as in the case of the first conventional example.

In a circuit using a DTMOS, as shown in FIG.
Even when S is connected to the power supply wiring, the wiring length of the metal layer can be made relatively short as compared with the above-mentioned conventional example 1.

However, when the PMOS is connected to the ground wiring, since the power supply wiring 101 is provided between the PMOS column 102 and the ground wiring 104, it is necessary to change the wiring layer. Wiring 116 made of a metal layer
Is provided, and a PMOS is provided through the through holes 117 and 118.
The PMOS of the column 102 is connected to the ground wiring 104. For this reason, the wiring as a whole becomes longer, and the through holes 11
Since the parasitic resistance due to 7, 118 also increases, the operation of the circuit becomes slow or unstable. In addition, it becomes an obstacle for performing other wiring.

Similarly, when the NMOS is connected to the power supply wiring, it is necessary to change the wiring layer because the ground wiring 104 exists between the NMOS column 103 and the power supply wiring 101.
Specifically, a wiring 113 made of a second metal layer is provided, and the NMOS column 1 is connected through the through holes 114 and 115.
The NMOS 03 is connected to the power supply wiring 101. For this reason, the wiring as a whole becomes longer, and the through holes 11
4, 115, the parasitic resistance also increases, so that the operation of the circuit becomes slow or unstable. In addition, it becomes an obstacle for performing other wiring.

In the case of the above-mentioned conventional example 3, the normal MOS
In the circuit using the PMO, as shown in FIG.
The PMOS in the S column 122 can be connected to the ground line 124, and the NMOS in the NMOS column 123 can be connected to the power supply line 121 by a short line.

In a circuit using DTMOS, unless the PMOS and NMOS used effectively are connected to the ground wiring and the power supply wiring, respectively, the circuit will not operate. Moreover, the number of MOSs connected to the power supply wiring and the ground wiring is large, and both the vertically adjacent PMOS and NMOS must be connected to the ground wiring and the power supply wiring at the same time.

As shown in FIG. 13, the PMOS of the PMOS column 122 is connected to the ground line 124, and the NM of the NMOS column 123 is
When the OS is connected to the power supply wiring 121 vertically at the same time, the wiring layer must be changed as in the case of the above-described conventional example 2 shown in FIG.

More specifically, the PMOS of the PMOS train 122
Is connected to a ground wiring 124 made of the first metal layer via a contact region 128 and a ground wiring branch line 127 branched from the ground wiring 124. For this reason, when the NMOSs of the vertically adjacent NMOS rows 123 are simultaneously connected to the power supply wiring 121, a wiring 131 made of a second metal layer is provided as shown in FIG. The NMOS 123 and the power supply line 121 are connected via the gate.

As a result, the wiring becomes longer, and the parasitic resistance due to the through holes 132 and 133 also increases, so that the operation of the circuit becomes slow or unstable. In addition, it becomes an obstacle for performing other wiring.

The present invention solves the above-mentioned problems of the prior art. In a semiconductor integrated circuit in which a plurality of field effect transistors are arranged in a row and connected by wiring to form a logic circuit, each of the field effect transistors is provided. When connecting the transistor to the power supply wiring or the ground wiring, the wiring can be easily connected without changing the wiring layer with a short wiring length, reducing the wiring resistance and simplifying the circuit configuration, and improving the reliability of the circuit. It is an object of the present invention to provide a semiconductor integrated circuit capable of improving, stabilizing operation, and increasing operation speed.

[0034]

According to a semiconductor integrated circuit of the present invention, a plurality of field-effect transistors are arranged in a column and connected by wiring to form a logic circuit. A field-effect transistor row and a second field-effect transistor row; a first wiring disposed between the first field-effect transistor row and the second field-effect transistor row; A second wiring parallel to the first wiring across the transistor row;
A third wiring parallel to the first wiring with the second field effect transistor row interposed therebetween, wherein the first wiring is a first wiring.
And the second wiring and the third wiring are at the second potential, thereby achieving the above object.

The second wiring and the third wiring may have a configuration in which the cross-sectional area of the wiring is smaller than that of the first wiring.

In the semiconductor integrated circuit according to the present invention, in a semiconductor integrated circuit in which a plurality of field effect transistors are arranged in a row and connected by wiring to form a logic circuit, the first field effect transistor row and the Two field-effect transistor rows, a first wiring disposed between the first field-effect transistor row and the second field-effect transistor row, and a first field-effect transistor row interposed therebetween. A second wiring parallel to the first wiring, and a third wiring parallel to the first wiring with the second field-effect transistor row interposed therebetween.
The cross-sectional structure composed of the second wiring and the third wiring
, At least one of the wirings is shared, and a plurality of wirings are continuously arranged, the first wiring has a first potential, and the second wiring and the third wiring have a second potential. Thus, the above object is achieved.

According to the semiconductor integrated circuit of the present invention, in a semiconductor integrated circuit in which a plurality of field-effect transistors are arranged in a row and connected to each other to form a logic circuit, a parallel first field-effect transistor row and a Two field-effect transistor rows, a first wiring disposed between the first field-effect transistor row and the second field-effect transistor row, and a first wiring disposed on the first field-effect transistor row. A second wiring parallel to the first wiring; and a third wiring disposed on the second field-effect transistor row and parallel to the first wiring. The wiring is at a first potential, the second wiring and the third wiring are at a second potential, and the above object is achieved.

[0038] The first field-effect transistor row and the second field-effect transistor row may have different polarities.

The first field-effect transistor row and the second field-effect transistor row may be formed of a mixture of different polarities.

The field effect transistor may be a DTMOS.

The operation of the present invention will be described below.

According to the above configuration, the first wiring, which is the first potential, is arranged between the parallel first and second field-effect transistor rows, and the first potential is set at the second potential. A certain second wiring is provided in parallel across the first field-effect transistor row, and a third wiring having a second potential is provided in parallel across the second field-effect transistor row.

For this reason, the first field-effect transistor row is adjacent to both the first wiring and the second wiring, and the second field-effect transistor row is connected to both the first wiring and the third wiring. Therefore, when connecting each transistor to each wiring, it is possible to use a single wiring layer to connect them with a short wiring length, thereby reducing wiring resistance and simplifying the circuit configuration. Therefore, it is possible to improve the reliability of the circuit, stabilize the operation, and increase the speed.

In particular, in a circuit using DTMOS, the circuit will not operate unless PMOS and NMOS, which are used effectively, are connected to the ground wiring and the power supply wiring, respectively. Moreover, M connected to the power supply wiring and the ground wiring
There are many OSs. On the other hand, with the above configuration, both the vertically adjacent PMOS and NMOS can be connected to the ground wiring and the power supply wiring at the same time. Therefore, the present invention is applied to a circuit using DTMOS as a field effect transistor. In some cases, it has a remarkable effect.

When the second wiring and the third wiring have a smaller cross-sectional area than the first wiring, the size of the semiconductor integrated circuit can be reduced. This is because, when the above configuration is employed, the number of field effect transistors connected to one of the second wiring and the third wiring is reduced by the number of field effect transistors connected to the first wiring. Paying attention to about half of the above, each wiring has a sectional area corresponding to a required signal transmission capability.

The second potential at the second potential, the first field effect transistor row, the first potential at the first potential, the second field effect transistor row, and the third potential at the second potential When the structure in which a plurality of wirings are arranged in parallel is formed by sharing at least one of the second wiring and the third wiring, and a plurality of transistors are connected to each wiring, In addition to being able to connect with a short wiring length by using one wiring layer, it is possible to reduce the size of the semiconductor integrated circuit by sharing wiring.

A first wiring having a first potential is disposed between the first and second parallel field-effect transistor rows, and a second wiring having a second potential is provided between the first and second field-effect transistor rows. If a third wiring which is provided in parallel on the first field-effect transistor row and has the second potential and is provided in parallel on the second field-effect transistor row is used, each transistor is connected to each wiring. At the time of connection, since the first field-effect transistor row and the second field-effect transistor row are adjacent to the first wiring, it is possible to connect with a short wiring length using one wiring layer, Further, a second wiring is provided in parallel on the first field-effect transistor row, and a third wiring is provided on the second field-effect transistor row.
Because it is juxtaposed on the field effect transistor row of
Only by providing a contact region in the diffusion region of each transistor, each transistor can be connected to each wiring. As a result, the wiring branch lines can be eliminated, the wiring length can be shortened accordingly, the wiring resistance can be reduced, and the circuit configuration can be simplified. Therefore, it is possible to further improve the reliability of the circuit and stabilize the operation and increase the speed.

Even when the first field-effect transistor row and the second field-effect transistor row have different polarities, the first field-effect transistor row and the second field-effect transistor row can be formed by mixing different polarities. With such a configuration, the above-described operation and effect can be similarly obtained.

[0049]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows an example of the configuration of a semiconductor integrated circuit according to Embodiment 1 of the present invention. A plurality of field effect transistors are arranged in a column, and they are interconnected to form a logic circuit. In the semiconductor integrated circuit, the first and second field-effect transistor rows 4 and 5 are arranged in parallel, and the first and second field-effect transistor rows 4 and 5 are arranged in parallel. A first wiring 1 disposed therebetween, a second wiring 2 parallel to the first wiring 4 with the first field effect transistor row 4 interposed therebetween, and a second wiring 2 parallel to the first wiring 4 interposed therebetween And a third wiring 3 parallel to the first wiring 1. The first wiring 1 has a first potential, and the second wiring 2 and the third wiring 3 have a second potential. It consists of a configuration.

The first field-effect transistor row 4
And the second field-effect transistor row 5 can be configured to have different polarities, and the first field-effect transistor row 4 and the second field-effect transistor row 5
A configuration consisting of a mixture of different polarities can also be used.

More specifically, for example, as shown in FIG. 1, the configuration of the semiconductor integrated circuit has a structure in which MOSs composed of diffusion layers are arranged in two upper and lower stages, and the upper stage has three PMs.
The lower row is an NMOS row 5 in which three NMOSs 51, 52, and 53 are arranged.
The ground wiring 1 made of the first metal layer is arranged between the PMOS row 4 and the NMOS row 5, and the ground wiring 1 is placed on the PMOS row 4.
A power supply line 2 made of a metal layer is disposed, and an NMOS column 5 is provided.
Below, a power supply wiring 3 made of a first metal layer can be arranged. PMOS 41, 42, 43 and N
The input lines 6 made of polycrystalline silicon are connected to the MOSs 51, 52, and 53, respectively.

According to this structure, the PMOSs 41, 42,
43 can be connected to the power supply wiring 2 or the ground wiring 1 with a short wiring without changing the wiring layer. Specifically, as shown in FIG. 1, the diffusion region of the PMOS 41 can be connected to the ground wiring 1 through the contact region 21 using the ground wiring branch line 11, and the diffusion region of the PMOS 42 is connected to the power supply wiring. It can be connected to the power supply wiring 2 through the contact region 22 using the branch line 12, and the PMOS 43
Can be connected to the ground wiring 1 through the contact region 23 using the ground wiring branch line 13.

Similarly, the NMOSs 51, 52, and 53 can be connected to the power supply wiring 3 or the ground wiring 1 with a short wiring without changing the wiring layer. Specifically, as shown in FIG. 1, the diffusion region of the NMOS 51 can be connected to the ground wiring 1 via the contact region 24 using the ground wiring branch line 14, and the diffusion region of the NMOS 52 is connected to the power supply wiring. The branch line 15 can be connected to the power supply line 3 via the contact region 25, and the diffusion region of the NMOS 53 can be connected to the power supply line 3 via the contact region 26 using the power supply line branch line 16. .

Here, the vertically adjacent PMOS 43 and N
Focusing on the MOS 53, the PMOS 43 is connected to the ground line 1
Further, it can be seen that the NMOS 53 can be simultaneously connected to the power supply wiring 3 with a short wiring without changing the wiring layer.

In a circuit using a DTMOS as a field effect transistor, a PMOS and an N which are effectively used are used.
If the MOS is not connected to the ground wiring and the power supply wiring, the circuit will not operate. Moreover, the number of MOSs connected to the power supply wiring and the ground wiring is large, and
Both OS and NMOS must be connected to the ground wiring and the power supply wiring at the same time. Therefore, the first embodiment described above
Has a remarkable effect when applied to a circuit using DTMOS.

In the specific example of the first embodiment, the ground wiring is arranged between the PMOS row and the NMOS row,
Although an example in which the power supply wiring is arranged above the column and below the NMOS column has been described, the present invention is not limited to this. The power supply wiring is arranged between the PMOS column and the NMOS column, and Alternatively, a ground line may be provided below the NMOS column.

(Embodiment 2) FIG. 2 shows an example of the configuration of a semiconductor integrated circuit according to Embodiment 2 of the present invention, which differs from Embodiment 1 in that a second wiring 2B and a third wiring 3 are provided.
B is different in that it has a configuration in which the cross-sectional area of the wiring is smaller than that of the first wiring 1, and the other configuration is the same as that of the first embodiment.

Specifically, for example, as shown in FIG.
The configuration of a semiconductor integrated circuit has a structure in which MOSs composed of a diffusion layer are arranged in two stages, upper and lower, and two PMOSs are arranged in the upper stage.
In the PMOS row 4 in which 44 and 45 are arranged, the lower row shows two NMs.
This is an NMOS row 5 in which OSs 54 and 55 are arranged, and a PMOS
A ground wiring 1 made of a first metal layer is arranged between the column 4 and the NMOS column 5. A power source made of the first metal layer on the PMOS column 4 and having a smaller wiring cross-sectional area than the ground wiring 1 Wiring 2
B, a power supply wiring 3B made of a first metal layer below the NMOS row 5 and having a smaller cross-sectional area than the ground wiring 1.
Can be provided. PMOS 44, 45
The input lines 6 made of polycrystalline silicon are connected to the NMOSs 54 and 55, respectively.

In the configuration of the second embodiment, the M connected to one of the upper and lower power supply wirings 2B, 3B
Paying attention to the fact that the number of OSs is about half of the number of MOSs connected to the ground wiring 1, and making the cross-sectional area of each power supply wiring 2B, 3B smaller than the cross-sectional area of the ground wiring 1, FIG. The size of the semiconductor integrated circuit is reduced as compared with the configuration of the first embodiment.

Also in the configuration of the second embodiment, similarly to the first embodiment, the PMOSs 44 and 45 can be connected to the power supply wiring 2B or the ground wiring 1 with short wiring without changing the wiring layer. . Specifically, as shown in FIG. 2, the diffusion region of the PMOS 44 can be connected to the power supply line 2B through the contact region 35 using the power supply line branch line 31, and the diffusion region of the PMOS 45 is connected to the ground line. The branch line 32 can be used to connect to the ground wiring 1 via the contact region 36.

Similarly, the NMOSs 54 and 55 can be connected to the power supply wiring 3B or the ground wiring 1 with short wiring without changing the wiring layer. Specifically, as shown in FIG. 2, the diffusion region of the NMOS 54 is
And the diffusion region of the NMOS 55 can be connected to the ground wiring 1 via the contact region 38 using the ground wiring branch line 34.

(Embodiment 3) FIG. 3 shows an example of the configuration of a semiconductor integrated circuit according to Embodiment 3 of the present invention. A plurality of field-effect transistors are arranged in a column, and they are interconnected to form a logic circuit. In the semiconductor integrated circuit constituting the above, the parallel first field-effect transistor row (4-1) and second field-effect transistor row (5-1), and the first field-effect transistor row (4-1) ) And the second field effect transistor row (5-1), the first wiring (1-1) disposed between the first field effect transistor row (4
-1), the second line parallel to the first wiring (1-1)
Composed of the wiring (2-1) of FIG. 1 and a third wiring (3-1) parallel to the first wiring (1-1) with the second column of field effect transistors (5-1) interposed therebetween. Structure A ₁ is the second
At least one of the wiring (2-1) and the third wiring (3-1) is shared to form a common cross-sectional structure A ₂ ,
A ₃ ,..., _An are continuously arranged as a plurality, and the first wiring (1-n) has the first potential, the second wiring (2-n) and the third wiring (2-n). The wiring (3-n) has the second potential.

Specifically, for example, as shown in FIG.
The PMOS columns (4-1), (4-2), ..., (4-
n) and NMOS columns (5-1), (5-2),...
In the case where (5-n) is arranged alternately and repeatedly, a power supply line and a ground line are alternately arranged between each PMOS column and NMOS column.

According to this configuration, similarly to the first and second embodiments, each PMOS and NMOS is
In addition to being able to be connected to the power supply wiring or the ground wiring without changing the wiring layer using short wirings, the size of the semiconductor integrated circuit can be reduced by sharing the power supply wiring or the ground wiring.

(Embodiment 4) FIG. 4 shows a configuration example of a semiconductor integrated circuit according to Embodiment 4 of the present invention, in which a plurality of field effect transistors are arranged in a column, and they are connected by wiring to form a logic circuit. In the semiconductor integrated circuit constituting the above, the first and second parallel field-effect transistor rows 7 and 8 and the first and second field-effect transistor rows 7 and 8 The first wiring 1 disposed therebetween, the second wiring 2 parallel to the first wiring 4 with the first field effect transistor row 7 interposed therebetween, and the second field effect transistor row 8 with the first field effect transistor row 7 interposed therebetween And a third wiring 3 parallel to the first wiring 1. The first wiring 1 has a first potential, and the second wiring 2 and the third wiring 3 have a second potential. , The first field effect transistor array 7 and the second electric field Fruit transistor array 8, a configuration consisting of a mixture of different polarities.

Specifically, for example, as shown in FIG.
The MOS column 7 in which the PMOS 46 and the NMOS 56 are mixed, and the MOS column 7 in which the PMOS 47 and the NMOS 57 are mixed.
By arranging the ground wiring 1 between the OS columns 8 and arranging the power wiring 2 parallel to the ground wiring 1 across the MOS column 7 and the power wiring 3 parallel to the ground wiring 1 across the MOS column 8 The same effects as in the first to third embodiments shown in FIGS. 1 to 3 can be obtained.

(Embodiment 5) FIG. 5 shows a configuration example of a semiconductor integrated circuit according to Embodiment 5 of the present invention, in which a plurality of field effect transistors are arranged in a column, and they are connected by wiring to form a logic circuit. In the semiconductor integrated circuit, the first and second field-effect transistor rows 4 and 5 are arranged in parallel, and the first and second field-effect transistor rows 4 and 5 are arranged in parallel. A first wiring 1 disposed between the first wiring 1 and a second wiring disposed on the first field-effect transistor row 4 and parallel to the first wiring 1;
And a third wiring 3C arranged on the second field-effect transistor row 5 and parallel to the first wiring 1. The first wiring 1 is at the first potential, 2 wiring 2
C and the third wiring 3C are configured to have the second potential.

Specifically, for example, as shown in FIG.
A PMOS column 4 composed of PMOSs 48 and 49, and an NMOS
An NMOS column 5 composed of 58 and 59, a PMOS column 4 and N
A ground line 1 arranged between the MOS columns 5;
Power supply wiring 2C arranged on
The power supply line 3 </ b> C arranged on the MOS column 8 and parallel to the ground line 1 can be provided.

According to this structure, only by providing the contact region 27 in the diffusion region of the PMOS 48,
Can be connected to the power supply wiring 2C. Similarly, NM
The NMOS 58 can be connected to the power supply wiring 3C only by providing the contact region 28 in the diffusion region of the OS 58. Therefore, in each of Embodiments 1 to 4, each M
The power supply wiring branch lines necessary for connecting the OS to the power supply wiring can be eliminated, the wiring length can be shortened accordingly, the wiring resistance can be reduced, and the circuit configuration can be simplified. Therefore, it is possible to further improve the reliability of the circuit, stabilize the operation, and increase the speed. It should be noted that the same effect can be obtained even if the power supply wiring and the ground wiring are arranged in a reverse arrangement relationship.

In the fifth embodiment, the same effects as those in the first to fourth embodiments shown in FIGS. 1 to 4 can be obtained.

It should be noted that the semiconductor integrated circuit of the present invention is not limited to the specific configurations of the first to fifth embodiments described with reference to FIGS.

[0073]

As described above, according to the semiconductor integrated circuit of the present invention, in a semiconductor integrated circuit in which a plurality of field effect transistors are arranged in a column and connected by wiring to constitute a logic circuit, When the field effect transistor is connected to the power supply wiring or the ground wiring, the connection can be made with a short wiring length by using one wiring layer, so that the wiring resistance can be reduced and the circuit configuration can be simplified. Therefore, the reliability of the circuit is improved and
Operation can be stabilized and speeded up by stable power supply. In addition, since the power supply wiring does not interfere with other signal wirings, other signal wirings can be shortened, and high-speed operation of the circuit can be realized. Further, since the wiring area can be reduced, the chip area can be reduced. In addition, since the power supply can be connected with a short wiring and there is no need to change the wiring layer, there is an effect that circuit design becomes easy.

More specifically, a first wiring, which is a first potential, is arranged between a first row of first field-effect transistors and a second row of second field-effect transistors, and a first wiring, which is a second potential, is provided. 2 lines are arranged in parallel across the first field-effect transistor row, and a third line at a second potential is connected to the second line.
, The first field-effect transistor row is adjacent to both the first wiring and the second wiring, and the second field-effect transistor row is Since the state is adjacent to both the first wiring and the third wiring, each transistor can be connected to each wiring with a short wiring length by using one wiring layer, thereby reducing wiring resistance. The circuit configuration can be simplified. Therefore, the reliability of the circuit can be improved, and the operation can be stabilized and the speed can be increased.

In particular, in a circuit using a DTMOS, both a vertically adjacent PMOS and an NMOS can be simultaneously connected to a ground wiring and a power supply wiring. Therefore, the present invention provides a circuit using a DTMOS as a field effect transistor. When applied to, it has a remarkable effect.

If the second wiring and the third wiring have a smaller cross-sectional area than the first wiring, the size of the semiconductor integrated circuit can be reduced.

A second potential at the second potential, a first field effect transistor row, a first potential at the first potential, a second field effect transistor row, and a third potential at the second potential When the structure in which a plurality of wirings are arranged in parallel is formed by sharing at least one of the second wiring and the third wiring, and a plurality of transistors are connected to each wiring, In addition to being able to connect with a short wiring length using one wiring layer, the size of the semiconductor integrated circuit can be reduced by sharing wiring.

A first wiring having a first potential is arranged between the first and second parallel field-effect transistor rows, and a second wiring having a second potential is provided between the first and second field-effect transistor rows. If a third wiring which is provided in parallel on the first field-effect transistor row and has the second potential and is provided in parallel on the second field-effect transistor row is used, each transistor is connected to each wiring. At the time of connection, since the first field-effect transistor row and the second field-effect transistor row are adjacent to the first wiring, connection can be made with a short wiring length using one wiring layer. Since the second wiring is provided on the first field-effect transistor row and the third wiring is provided on the second field-effect transistor row, the contact region is formed in the diffusion region of each transistor. Just provide
Each transistor can be connected to each wiring. As a result, the wiring branch lines can be eliminated, the wiring length can be shortened accordingly, the wiring resistance can be reduced, and the circuit configuration can be simplified. Therefore, it is possible to further improve the reliability of the circuit, stabilize the operation, and increase the speed.

Even when the first field-effect transistor row and the second field-effect transistor row have different polarities, the first field-effect transistor row and the second field-effect transistor row are formed by mixing different polarities. With such a configuration, the above-described operation and effect can be similarly obtained.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 2 is a diagram illustrating a configuration example of a semiconductor integrated circuit according to a second embodiment of the present invention;

FIG. 3 is a diagram illustrating a configuration example of a semiconductor integrated circuit according to a third embodiment of the present invention;

FIG. 4 is a diagram illustrating a configuration example of a semiconductor integrated circuit according to a fourth embodiment of the present invention;

FIG. 5 is a diagram showing a configuration example of a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 6 is a layout diagram of a standard cell type semiconductor integrated circuit according to Conventional Example 1.

FIG. 7 is a diagram showing a configuration example of a semiconductor integrated circuit according to Conventional Example 1.

FIG. 8 is a diagram for explaining a problem in the semiconductor integrated circuit according to Conventional Example 1.

FIG. 9 is a layout diagram of a standard cell type semiconductor integrated circuit according to Conventional Example 2.

FIG. 10 is a diagram showing a configuration example of a semiconductor integrated circuit according to Conventional Example 2.

FIG. 11 is a diagram for explaining a problem in a semiconductor integrated circuit according to Conventional Example 2.

FIG. 12 is a diagram showing a configuration example of a semiconductor integrated circuit according to Conventional Example 3.

FIG. 13 is a diagram for explaining a problem in a semiconductor integrated circuit according to Conventional Example 3.

FIG. 14 is a diagram for explaining characteristics of a normal PMOS.

FIG. 15 is a diagram for explaining characteristics of a normal NMOS.

FIG. 16 is a diagram for explaining characteristics of a PMOS which is a DTMOS.

FIG. 17 is a diagram illustrating characteristics of an NMOS that is a DTMOS.

FIG. 18 is a diagram illustrating a configuration example of a logic circuit using a normal MOS.

FIG. 19 is a diagram illustrating a configuration example of a logic circuit using DTMOS.

FIG. 20 is a diagram for explaining the back gate voltage dependence of MOS characteristics.

[Explanation of symbols]

Reference Signs List 1 ground wiring 2, 2B, 2C, 3, 3B, 3C power supply wiring 4 PMOS column 5 NMOS column 6 input line 7, 8 MOS column 11, 13, 14, 17, 18, 32, 34 ground wiring branch lines 12, 15, 16, 31, 33 Power supply wiring branch lines 21 to 28, 35 to 38 Contact regions 41 to 49 PMOS 51 to 59 NMOS

Claims (7)

[Claims] 1. A semiconductor integrated circuit in which a plurality of field-effect transistors are arranged in a row and connected to each other by wiring to form a logic circuit, wherein a parallel first field-effect transistor row and a second field-effect transistor row are arranged in parallel. A first wiring disposed between the first field-effect transistor row and the second field-effect transistor row; and a first wiring interposed between the first field-effect transistor row and the first wiring. A second wiring parallel to the second field effect transistor, and a third wiring parallel to the first wiring with the second field effect transistor row interposed therebetween, wherein the first wiring has a first potential, A semiconductor integrated circuit in which the second wiring and the third wiring have a second potential. 2. The semiconductor integrated circuit according to claim 1, wherein said second wiring and said third wiring have a smaller cross-sectional area than said first wiring. 3. A semiconductor integrated circuit in which a plurality of field-effect transistors are arranged in a row and connected by wiring to form a logic circuit, wherein a parallel first field-effect transistor row and a second field-effect transistor row are arranged in parallel. A first wiring disposed between the first field-effect transistor row and the second field-effect transistor row; and a first wiring with the first field-effect transistor row interposed therebetween. A cross-sectional structure including a parallel second wiring and a third wiring parallel to the first wiring with the second field-effect transistor row interposed therebetween is formed by the second wiring and the third wiring At least one of them is shared, and a plurality of the wirings are continuously arranged, the first wiring has a first potential, and the second wiring and the third wiring have a second potential. Semiconductor integrated circuit. 4. A semiconductor integrated circuit in which a plurality of field effect transistors are arranged in a row and connected to each other by wiring to form a logic circuit, wherein a parallel first field effect transistor row and a second field effect transistor row are arranged in parallel. A first wiring disposed between the first field-effect transistor row and the second field-effect transistor row; and a first wiring disposed on the first field-effect transistor row, A second wiring parallel to the wiring, and a third wiring arranged on the second column of field effect transistors and parallel to the first wiring, wherein the first wiring has a first potential Wherein the second wiring and the third wiring are at a second potential. 5. The semiconductor integrated circuit according to claim 1, wherein said first field-effect transistor row and said second field-effect transistor row have different polarities. 6. The semiconductor integrated circuit according to claim 1, wherein said first field-effect transistor row and said second field-effect transistor row are made of a mixture of different polarities. 7. The method according to claim 1, wherein the field effect transistor is a DTMOS.
The semiconductor integrated circuit according to claim 1, wherein