JPH02172256A - Logic circuit - Google Patents

Abstract

PURPOSE:To reduce an unused region, a chip size and cost by a method wherein standard cells of a CMOS gate and BiCMOS gate are made equally high and a bipolar transistor is placed in parallel to a power source line in a lengthwise direction of a contact. CONSTITUTION:A first and a second paris of power source lines 1, 2 are placed in parallel, while a MOS transistor 5 having first polarity is placed in a region between one pair of the power source lines 1, 2 and on the side of the first power source line 1, while MOS transistors 6, 7 having second polarity are placed on the side of the second power source line 2 and a bipolar transistor 8 is placed in a region between one pair of the power source lines 1, 2. Therefore, height of standard cells of a CMOS gate and a BiCMOS gate can be made equal, and a bipolar part 4 can be placed in parallel to the power source lines 1, 2 in the lengthwise direction of a contact. This reduces an unused region, a chip size and cost.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a logic circuit, and more particularly to the layout of a logic circuit constructed by combining MOS transistors and bipolar transistors.

(Prior Art) Generally, in the layout design of LSI logic circuits,
Since this requires a large amount of man-hours, the conventional standard is to design the layout of multiple types of basic logic gates with a certain height in advance, and then place and route these many basic logic gates using an automatic layout tool. Layout techniques such as cells are often used.

On the other hand, recently, in order to improve the speed performance of LSI,
BiCMO8 basic logic gates, which are a combination of MOS transistors and bipolar transistors, are attracting attention.

Such a B1 CMOS gate has the low power consumption of a CMOS gate consisting of a pair of N-channel and P-channel MOS transistors and the high speed of a bipolar transistor, and is therefore a promising logic gate for future LSIs.

For example, in a standard cell constructed with such a conventional B1CMOS gate, a bipolar section is added above or below the 0M08 section.

(Problems to be Solved by the Invention) The conventional B1 CMOS gate described above is difficult to use when driving a large load capacity such as a large number of logic gates or long wiring.
Although it is possible to drive at a higher speed than a gate, it is slower to drive a small load capacitance than a CMOS gate. Additionally, most logic gates inside an LSI are generally 1 m long.
It is connected to only a few logic gates by short wiring of less than m. Therefore, if all the logic gates are constructed of B1CMOS gates, there is a problem that sufficient speed performance cannot be obtained. Therefore, in order to solve this problem and increase speed, the conventional method was to configure only logic circuits with large fan-out numbers and long wiring lengths using B1 CMOS gates, and to configure most of the remaining logic circuits with CMOS gates. is advantageous.

However, since the conventional standard cell using a B1CMOS gate has a structure in which a bipolar section is added to the top of the 0M08 section, when such standard cells with Bi CMOS gates and CMOS gates are placed together, the heights are not the same. However, the conventional B1CMOS gate layout method has the disadvantage of increasing the unused area and increasing the chip size.
The disadvantage is that the increase in chip size leads to an increase in price.

The object of the present invention is to use such a CMOS gate and B1CMOS
Reduces unused area when placing gates in a mixed manner,
An object of the present invention is to provide a logic circuit that can reduce the chip size of an LSI and can be laid out at a low cost.

(Means for Solving the Problems) The logic circuit of the present invention is configured by MOS transistors and bipolar transistors, in which a first and second pair of power supply wiring lines are arranged in parallel, and the pair of power supply wiring lines are arranged in parallel. A MOS transistor of a first polarity is arranged in a region between the wiring lines and on the side of the first power supply wiring line, and a MOS transistor of a second polarity is arranged on the side of the second power supply wiring line, and the MOS transistor of the second polarity is arranged on the side of the second power supply wiring line. is arranged in a region between the pair of power supply wiring lines.

Further, in the logic circuit of the present invention, the first and second pair of power supply wiring lines are arranged in parallel in the logic circuit composed of MOS transistors and bipolar transistors, and the area between the pair of power supply wiring lines is and a MOS transistor of a first polarity is arranged on the side of the first power supply wiring line, a MOS transistor of a second polarity is arranged on the side of the second power supply wiring line, and the bipolar transistor is connected between the pair of power supply wiring lines. The rectangular contact of the bipolar transistor is arranged in a region such that the length direction of the rectangular contact of the bipolar transistor is parallel to the pair of power supply lines.

(Function) By making the standard cells of the CMOS gate and the B1CMOS gate the same height, the logic circuit of the present invention can prevent unevenness between the CMOS gate and the B1CMOS gate when placing and wiring the standard cells using automatic layout. This will reduce the amount of unused space.

In addition, if you want to increase the drive capacity of the bipolar part by arranging the contact length of the bipolar part parallel to the power supply line, you can simply extend the contact parallel to the power supply line, so you can change the height. Therefore, a B1CMOS gate with high driving ability can be realized without any problem.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a basic layout diagram of a logic circuit for explaining one embodiment of the present invention.

As shown in FIG. 1, the B1CMOS gate in this embodiment is provided with a first power supply wiring 1 and a second power supply wiring 2 that are drawn parallel to each other. An 0M08 section 3 and a bipolar section 4 are provided between the power supply wiring 2 and the power supply wiring 2. Normally, 5V (volts) is applied to this first power supply wiring 1, and the second power supply wiring 2 is used as a ground.

The B1 CMOS gate arranged in this way is a CMOS
Since it is the same height as the gate, B1CMOS gate and C
Even if MOS gates are mixed and arranged, the first power supply wiring 1
and the second power supply wiring 2 can be drawn in parallel. Therefore, when a plurality of logic gates are connected, the unused area is reduced and the chip size can be reduced.

FIG. 2 is a block diagram of the logic circuit represented by the layout shown in FIG. 1, and FIG. 3 is a specific layout diagram of the logic circuit shown in FIGS. 1 and 2.

This embodiment will be described in detail below with reference to FIGS. 2 and 3.

As shown in FIG. 2, the logic circuit of this embodiment includes a CMOS inverter consisting of a first P-channel type MOS transistor 5 and a second N-channel type MOS transistor 5, and a third N-channel type MOS transistor. A B1CMOS inverter circuit consisting of a MOS transistor and an NPN bipolar transistor 8 is connected between an input terminal 9 and an output terminal 10.

In this logic circuit, when a high potential is applied to the input terminal 9, the second and third MOS transistors 7 become conductive, and the output terminal 10 becomes a low potential. On the other hand, when a low potential is applied to the input terminal 9, the bipolar transistor 8 becomes conductive together with the first MOS transistor 5, and the output terminal 10 becomes a high potential. That is, the output terminal 10 is connected to the power supply terminal (2) via the bipolar transistor 8 having low conduction resistance. Therefore, if such a logic circuit is used, high-speed driving is possible even for a large capacity load.

As shown in FIG. 3, the transistors constituting the logic circuit described above are arranged between the first power supply wiring 11 and the second power supply wiring 12. First, the P type diffusion layer 13 and the gate electrode 14 form the first MOS transistor 5 described above in FIG. 2, and the N type diffusion layer 15 and the gate electrode 14 form the second MOS transistor 6. A third MOS transistor is formed. Next, first to fifth contacts) 16A to 16E are P-type diffusion layer 13 and first power supply wiring 11, N-type diffusion layer 15 and second power supply wiring 12, respectively.
, the P type diffusion layer 13 and the -th layer metal wiring 17, the N type diffusion layer 15 and the -th layer metal wiring 17, and the N type diffusion layer 15 and the -th layer metal wiring 17 are connected. Furthermore, the third and fourth contacts 16C and 116D and the base contact 18 of the bipolar transistor are connected by a -th layer metal wiring 17, and the collector contact 19 of the bipolar transistor is connected to the first power supply wiring 11. Furthermore, the emitter contact 20 of the bipolar transistor is connected to the N-type diffusion layer 15 and the second layer metal interconnect 22 via the -th layer metal interconnect 17, the fifth contact 16E, and the through-hole contact 21. Therefore, the gate electrode 14 described above becomes the input terminal 9 shown in FIG. 2, and the second layer metal wiring 22 becomes the output terminal 10.

In this way, the first power supply wiring 11 and the second power supply wiring 1
A transistor is formed between 2 and contacts 16A to 16.
By connecting via E and 18-21, the second
The logic circuit shown in the figure can be realized.

As mentioned above, the bipolar transistor represented by the base contact 18, collector contact 19 and emitter contact 2o is arranged next to the P-type diffusion layer 13. For this reason, the height of the B1CMOS gate is set to CM
Since the height can be made the same as the OS gate, the unused area is reduced and the chip size can be reduced.

On the other hand, the conduction resistance of such a bipolar transistor can be reduced by increasing the length of the rectangular contacts (base contact 18, collector contact 19, emitter contact 20). That is, if this conduction resistance can be reduced, the driving ability of the bipolar transistor can be increased. In this embodiment, as shown in FIG. 3, by arranging the rectangular contacts 18 to 20 so that the length direction thereof is parallel to the first power supply wiring 11, the height of the B1CMOS gate is not changed. It becomes possible to extend the length of the rectangular contacts 18-20.

In short, B1 CMOS gates having various driving capabilities can be realized with the same height as the CMOS gate.

(Effects of the Invention) As explained above, the logic circuit of the present invention can realize a B1CMOS gate with the same height as a CMOS gate, and also makes the contact length of the bipolar transistor parallel to the power supply line. By arranging B1CMOS gates with various driving capacities, it is possible to realize them at the same height as 0MO8. Therefore, when CMOS gates and B1CMOS gates are arranged together, the unused area can be reduced and the LSI chip This has the effect of reducing the size, that is, lowering the price.

[Brief explanation of the drawing]

FIG. 1 is a basic layout diagram of a logic circuit for explaining one embodiment of the present invention, FIG. 2 is a configuration diagram of a logic circuit formed with the layout shown in FIG. 1, and FIG. FIG. 3 is a specific layout diagram of the logic circuit in FIG. 3 and FIG. 2; 1.11...First power wiring, 2.12...Second power wiring, 3...0M08 section,
4...Bipolar section, 5-7...MOS)-transistor, 8...Bipolar transistor, 9...Input terminal,
10... Output terminal, 13... P-type diffusion layer, 14...
・Gate electrode, 15・-N type diffusion layer, 16A to 16E・
... Contact, 17... Second layer metal wiring, 18... Base contact, 19... Collector contact, 20... Emitter contact, 21... Through hole contact, 22... Second layer metal wiring.

Claims (2)

[Claims] (1) In a logic circuit constituted by a MOS transistor and a bipolar transistor, a pair of first and second power supply wiring lines are arranged in parallel, and within a region between the pair of power supply wiring lines and the first power supply wiring line. A MOS transistor of a first polarity is arranged on a wiring line side, a MOS transistor of a second polarity is arranged on a side of the second power supply wiring line, and the bipolar transistor is arranged in a region between the pair of power supply wiring lines. A logic circuit characterized by: (2) In a logic circuit constituted by a MOS transistor and a bipolar transistor, a first and second pair of power supply wiring lines are arranged in parallel, and within a region between the pair of power supply wiring lines and the first power supply wiring line. A MOS transistor of a first polarity is arranged on the wiring side, a MOS transistor of a second polarity is arranged on the second power supply wiring line side, and the bipolar transistor is arranged in a region between the pair of power supply wiring lines. . A logic circuit characterized in that the length direction of the rectangular contact of the bipolar transistor is parallel to the pair of power supply lines.