JP2000340413A - Multiple chip resistor and manufacturing method thereof - Google Patents

Abstract

(57) [Problem] To provide a multiple chip resistor capable of reducing a mounting area when mounted on a mounting board and a method of manufacturing the same. A plurality of pairs of upper electrode layers provided from a side portion of an upper surface of a substrate to a part of a side surface thereof, and a plurality of resistors provided so as to be electrically connected to the plurality of pairs of upper electrode layers. A layer 23, and a protective layer 24 provided so as to cover at least the plurality of resistance layers 23, and when soldering to a mounting substrate, a solder fillet becomes small.
The mounting area can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiple chip resistor used for various electronic devices and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of electronic devices, there has been an increasing demand for miniaturization in order to increase the mounting density of electronic components used for circuit boards. As for resistors, in order to reduce the mounting area on the mounting board, the demand for not only small resistors but also multiple chip resistors with independent resistance elements as one unit is increasing. I have.

A conventional resistor of this type is disclosed in Jpn.
Japanese Unexamined Patent Publication No. 79430/1992 (Japanese Utility Model Laid-Open No. 4-38001) discloses a microfilm.

Hereinafter, a conventional multiple chip resistor and a method of manufacturing the same will be described with reference to the drawings.

FIG. 15A is a perspective view of a conventional multiple chip resistor, and FIG. 15B is a sectional view of the same.

In FIGS. 15A and 15B, reference numeral 1 denotes a ceramic substrate having a notch 2 at the center of both side surfaces. Reference numeral 3 denotes two pairs of upper electrode layers provided on the side of the upper surface of the substrate 1. Reference numeral 4 denotes two resistance layers provided so as to partially overlap the two pairs of upper electrode layers 3. 5 is a protective layer provided so as to cover the two resistance layers 4. Reference numeral 6a denotes two pairs of side electrode layers which are provided from the side surface of the substrate 1 to the side surface of the lower surface so as to partially overlap the two pairs of upper electrode layers 3, and are formed by printing and firing a conductive paste. Reference numeral 6b denotes a plating layer formed of solder plating or nickel and solder plating provided so as to cover the two pairs of upper electrode layers 2 and the two pairs of side electrode layers 6a.

A method of manufacturing a conventional resistor having the above-described structure will be described below.

FIGS. 16A and 16B and FIG.
(A), (b) is a process drawing which shows the manufacturing method of the conventional multiple chip resistor.

First, as shown in FIG. 16A, a through hole 9 is formed in a sheet-like substrate 8a made of ceramic.
A vertical dividing groove 10a and a horizontal dividing groove 10b for dividing the substrate 8a in a later step are formed.

Next, as shown in FIG. 16B, a plurality of pairs of upper electrode layers 3 are formed by printing on the upper surface of the sheet-like substrate 8a, and further overlap a part of the pair of upper electrode layers 3. The plurality of resistance layers 4 are formed by printing as described above.

Next, as shown in FIG. 17A, after a plurality of protective layers 5 are formed by printing so as to cover the whole of the plurality of resistive layers 3, a horizontal dividing groove 10b (FIG. 16A) , (B)
To obtain a strip-shaped substrate 8b.

Next, as shown in FIG. 17 (b), the side surface electrode layer extends from the side surface of the strip-shaped substrate 8b to the side surface of the lower surface so as to partially overlap the upper surface electrode layer 3 of the strip-shaped substrate 8b. After coating 6a, the strip-shaped substrate 8b is divided along the vertical dividing grooves 10a to obtain individual substrates (not shown).

Finally, a portion of the upper electrode layer 3 and a surface of the side electrode layer 6a are subjected to solder plating or nickel and solder plating to form a plating layer 6b as shown in FIGS. Formed to produce conventional multiple chip resistors.

[0014]

However, in the above conventional configuration, when this multiple chip resistor is mounted on a mounting substrate such as a printed circuit board by soldering, FIG.
As shown in the cross-sectional view showing the mounting state, the multiple chip resistor is soldered to the solder land pattern 12 of the mounting substrate on both the side surface on which the side electrode layer (not shown) is provided and the side surface on the lower surface. Then, the fillet 13 is formed by the solder. In this case, as shown in the top view of the mounting state of FIG. 18B, an area 15 for soldering the side surface is required in addition to the component area 14 of the multiple chip resistor 11, and the mounting area combining these is required. 16 is required. In addition, as the external dimensions of components are reduced in order to increase the mounting density, the ratio of the soldering area to the mounting area increases, and as a result, the mounting density for miniaturizing electronic devices is increased. Had the problem that limits would arise.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a multiple chip resistor capable of reducing a soldering area occupying a mounting area when mounted on a mounting board.

[0016]

In order to achieve the above object, a multiple chip resistor according to the present invention comprises a plurality of pairs of upper electrode layers provided from a side of an upper surface of a substrate to a part of a side surface thereof.
It is provided with a plurality of resistance layers provided so as to be electrically connected to the plurality of pairs of upper electrode layers, and a protection layer provided so as to cover at least the plurality of resistance layers. If this multiple chip resistor is mounted on a mounting board such as a printed board, the soldering area occupying the mounting area can be reduced. In addition, since it is a multiple chip, the area of a solder land pattern required for mounting by soldering can be made smaller than that of a single chip.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a substrate, a plurality of pairs of upper electrode layers provided from the side of the upper surface of the substrate to a part of the side surface, and the plurality of upper surfaces of the plurality of pairs. According to this configuration, a plurality of resistance layers provided so as to be electrically connected to the electrode layers and a protective layer provided so as to cover at least the plurality of resistance layers are provided. Since the electrodes are provided only on a part of the side surface, not the whole, when this multiple chip resistor is mounted on the mounting board by soldering, the portion where the solder fillet is formed can be reduced, and This has the effect that the soldering area occupying the mounting area can be reduced.

According to a second aspect of the present invention, in the first aspect, the plurality of pairs of upper electrode layers are covered with the plurality of pairs of plating layers, and the plurality of pairs of the plating layers and the protective layer are flush with each other. According to this structure, the height of the plurality of pairs of plating layers is higher than that of the protective layer. According to this configuration, the solder land pattern of the mounting board and the plating layer covering the upper electrode layer are close to each other. This has the effect of reducing soldering defects at the time.

According to a third aspect of the present invention, in the first aspect of the invention, a plurality of pairs of upper electrode layers are formed of a metal material obtained by firing a gold-based organometallic compound. For example, since a gold-based metal material is used for the upper electrode layer, ion migration is reduced and the load life characteristics are improved.

According to a fourth aspect of the present invention, in the first aspect of the present invention, a plurality of pairs of upper electrode layers are formed of a metal material provided by a nickel-based or gold-based sputtering method. For example, since the thickness of a plurality of pairs of upper electrode layers provided on a part of the side surface of the substrate can be reduced, when the sheet-like substrate is divided by the division grooves, burrs and distortions occur at the division surface of the upper electrode layer. Is less likely to occur, and has the effect of dividing the substrate.

According to a fifth aspect of the present invention, in the first aspect of the present invention, the ridges of the plurality of pairs of upper electrode layers are rounded, and according to this configuration, the area of the ridges of the upper electrode layers is increased. The thermal expansion coefficient between the mounting board and the board of the multiple chip resistor can be expanded even if a temperature change such as thermal shock is applied after soldering this multiple chip resistor to the mounting board. It is possible to alleviate the concentration of the stress generated due to the difference in the ridge portion of the upper electrode layer, thereby improving the reliability after mounting.

According to a sixth aspect of the present invention, there is provided a substrate, a plurality of pairs of first upper electrode layers provided from a side portion of the upper surface of the substrate to a part of a side surface, and the plurality of first upper surfaces. A plurality of pairs of second upper electrode layers provided on the upper surface of the substrate so as to be electrically connected to the electrode layers; and a plurality of pairs of second upper electrode layers provided to be electrically connected to the plurality of pairs of the second upper electrode layers. With a plurality of resistance layers and a protective layer provided so as to cover at least the plurality of resistance layers, according to this configuration, electrodes are provided not on the entire side surface of the substrate but only on a part of the side surface. Therefore, when this multiple chip resistor is mounted on a mounting board by soldering, a portion where a solder fillet is formed can be reduced, and thereby, the soldering area occupying the mounting area can be reduced. Has the effect of

According to a seventh aspect of the present invention, in the sixth aspect of the invention, a plurality of pairs of the first upper electrode layer and the second upper electrode layer are covered with a plurality of pairs of plating layers, and The plating layer and the protection layer are configured such that the height of the plating layer or the plurality of pairs of plating layers is higher than the protection layer, and according to this configuration, the plating layer covers the solder land pattern and the upper electrode layer of the mounting board. Since it is close to the plating layer, it has an effect of reducing soldering defects at the time of soldering.

According to an eighth aspect of the present invention, in the sixth aspect, the plurality of pairs of first upper electrode layers are made of a metal material obtained by firing a gold-based organometallic compound.
According to this configuration, since a gold-based metal material is used for the upper electrode layer, it has an effect of reducing ion migration and improving load life characteristics.

According to a ninth aspect of the present invention, in the invention according to the sixth aspect, a plurality of pairs of the first upper electrode layers are formed of a metal material provided by a nickel-based or gold-based sputtering method. According to the configuration, the thickness of a plurality of pairs of upper electrode layers provided on a part of the side surface of the substrate can be reduced. Burr, distortion, and the like are less likely to occur and the substrate can be divided.

According to a tenth aspect of the present invention, in the sixth aspect of the invention, a plurality of pairs of second upper electrode layers have rounded ridges. Since the area of the ridge portion of the layer can be enlarged, even if a temperature change such as thermal shock is applied after soldering this multiple chip resistor to the mounting board, the mounting board and the multiple chip resistor The stress generated due to the difference in thermal expansion coefficient from the substrate can be reduced from being concentrated on the ridge portion of the upper electrode layer, thereby improving the reliability after mounting. is there.

According to an eleventh aspect of the present invention, a plurality of pairs of upper surface electrode layers are formed by a printing method on the upper surface of the sheet-like substrate and in the division grooves so as to straddle the division grooves of the sheet-like substrate having the division grooves. A step of forming a plurality of resistive layers so as to electrically connect the plurality of pairs of upper electrode layers, a step of forming a protective layer so as to cover at least the plurality of resistive layers, and a step of: According to this manufacturing method, there is provided a step of dividing the sheet-shaped substrate into strip-shaped substrates by the divided grooves of the sheet-shaped substrate, and a step of dividing the strip-shaped substrate into individual pieces. Since the electrodes are formed only on a part of the side surface, not on the entire side surface, when this multiple chip resistor is mounted on the mounting board by soldering, the portion where the solder fillet is formed can be reduced, By implementation It is expected to have an effect that it is possible to reduce the soldering area occupying in the product.

According to a twelfth aspect of the present invention, a plurality of pairs of upper electrode layers are formed by a sputtering method on the upper surface of the sheet-like substrate and in the above-mentioned divisional grooves over the divisional grooves of the sheet-like substrate having the divisional grooves. A step of forming a plurality of resistive layers so as to electrically connect the plurality of pairs of upper electrode layers, a step of forming a protective layer so as to cover at least the plurality of resistive layers, and a step of: According to this manufacturing method, there is provided a step of dividing the sheet-shaped substrate into strip-shaped substrates by the divided grooves of the sheet-shaped substrate, and a step of dividing the strip-shaped substrate into individual pieces. Since the electrodes are formed only on a part of the side surface, not on the entire side surface, when this multiple chip resistor is mounted on the mounting board by soldering, the portion where the solder fillet is formed can be reduced, By And it has an effect that it is possible to reduce the soldering area occupying in the mounting area.

According to a thirteenth aspect of the present invention, a plurality of pairs of first upper electrode layers are formed by a printing method on the upper surface of the sheet-like substrate and the inside of the divided groove over the divided groove of the sheet-shaped substrate having the divided groove. Forming a plurality of pairs of second upper surface electrode layers so as to be electrically connected to the plurality of pairs of first upper surface electrode layers; and forming the plurality of pairs of second upper surface electrode layers. Forming a plurality of resistive layers so as to electrically connect them, forming a protective layer so as to cover at least the plurality of resistive layers, and dividing the sheet-like substrate obtained in the previous step with the dividing grooves. The method includes a step of dividing the sheet-shaped substrate into strip-shaped substrates, and a step of dividing the strip-shaped substrate into individual pieces. According to this manufacturing method, not the entire side surface of the substrate, but a part of the side surface Only the electrodes are formed on this multiple chip resistor. When implemented by soldering the mounting substrate, it is possible to reduce the portion of the solder fillet is formed, thereby, those having the effect that it is possible to reduce the soldering area occupying in the mounting area.

According to a fourteenth aspect of the present invention, a plurality of pairs of first upper surface electrode layers are formed by sputtering on the upper surface of the sheet-like substrate and the inside of the divisional grooves over the divisional grooves of the sheet-like substrate having the divisional grooves. Forming a plurality of pairs of second upper surface electrode layers so as to be electrically connected to the plurality of pairs of first upper surface electrode layers; and forming the plurality of pairs of second upper surface electrode layers. Forming a plurality of resistive layers so as to electrically connect them, forming a protective layer so as to cover at least the plurality of resistive layers, and dividing the sheet-like substrate obtained in the previous step with the dividing grooves. The method includes a step of dividing the sheet-shaped substrate into strip-shaped substrates, and a step of dividing the strip-shaped substrate into individual pieces. According to this manufacturing method, not the entire side surface of the substrate, but a part of the side surface Since multiple electrodes are formed only on this chip, When a resistor is mounted on a mounting board by soldering, a portion where a solder fillet is formed can be reduced, thereby having an effect that a soldering area occupying a mounting area can be reduced. .

(Embodiment 1) Hereinafter, a multiple chip resistor and a method of manufacturing the same according to Embodiment 1 of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a multiple chip resistor according to the first embodiment of the present invention.

In FIG. 1, reference numeral 21 denotes an insulating substrate containing 96% of alumina. Reference numeral 22 denotes a plurality of pairs of upper electrode layers made of silver-based conductive powder containing glass provided from the side of the upper surface of the substrate 21 to a part of the side surface thereof. It has. Further, the upper electrode layer 22 provided on the side surface of the substrate 21
Is less than half the area of the side surface of the substrate 21. 2
Reference numeral 3 denotes a plurality of resistance layers mainly composed of ruthenium oxide provided on the upper surface of the substrate 21 so as to be electrically connected to the plurality of pairs of upper electrode layers 22. Reference numeral 24 denotes a protective layer made of glass, resin, or the like provided so as to cover at least the upper surfaces of the plurality of resistance layers 23. Reference numerals 25 and 26 denote a nickel plating layer and a solder plating layer which are provided so as to cover the upper electrode layer 22 as necessary, and which ensure reliability and the like at the time of soldering.

A method of manufacturing the multiple chip resistor according to the first embodiment of the present invention having the above-described configuration will be described below with reference to the drawings.

FIGS. 2A to 2C and FIGS. 3A to 3 A
FIG. 4C is a process diagram illustrating the method for manufacturing the multiple chip resistor in the first embodiment of the present invention.

First, as shown in FIG. 2 (a), the surface has a plurality of vertical and horizontal dividing grooves 27, 28 provided on the surface for dividing into strips and individual pieces in a later step. And a silver-based conductive powder in the sheet-like substrate 21 and the lateral divisional grooves 28 over the lateral divisional grooves 28 of the sheet-like substrate 21 containing 96% alumina having excellent insulation properties. After printing the electrode paste containing glass,
By baking at about 850 ° C., a plurality of pairs of upper electrode layers 22 are formed. At this time, the electrode paste is divided into the horizontal dividing grooves 28.
As a result, the upper surface electrode layer 22 can be formed to the depth of the horizontal dividing groove 28. Further, the depth of the vertical and horizontal dividing grooves 27 and 28 with respect to the thickness of the sheet-like substrate 21 is set to be not more than half of the thickness of the sheet-like substrate 21 so as not to be broken during handling in a manufacturing process. Is formed.

Next, as shown in FIG. 2B, a resistance paste containing ruthenium oxide as a main component is printed on the upper surface of the sheet-like substrate 21 so as to electrically connect a plurality of pairs of upper electrode layers 22. After that, firing at about 850 ° C.
To form

Next, as shown in FIG.
In order to correct the resistance value of No. 3 to a predetermined value, trimming is performed by forming a trimming groove 29 with a YAG laser. At this time, the trimming probe for measuring the resistance value is set on the upper electrode layer 22 to perform trimming.

Next, as shown in FIG. 3A, in order to protect the resistance layer 23 having the corrected resistance value, a paste containing glass as a main component is printed so as to cover at least the resistance layer 23, and about 600 The protective layer 24 is formed by baking at a temperature of ° C. In this case, the print pattern of the protection layer 24 may be formed so as to continuously cover the plurality of resistance layers 23 arranged in the horizontal direction across the divisional grooves 27 in the vertical direction.

Next, as shown in FIG. 3B, the sheet-like substrate 21 on which the upper electrode layer 22, the resistance layer 23, the trimming groove 29, and the protective layer 24 are formed is divided along the horizontal dividing groove 28. Then, the strip-shaped substrate 30 is formed. At this time, the upper surface electrode layer 22 formed previously is formed on the side surface in the longitudinal direction of the strip-shaped substrate 30 to the depth of the horizontal dividing groove 28.

Finally, as shown in FIG. 3C, as a preparation step for plating the exposed upper electrode layer 22, the strip-shaped substrate 30 is divided along the vertical dividing grooves 27. Then, an individual substrate 31 is formed. Then, a nickel plating layer (not shown) and a solder plating layer (not shown) are formed by electroplating so as to cover the exposed upper electrode layer 22, thereby manufacturing a multiple chip resistor. It is.

A state in which the multiple chip resistor constructed and manufactured in the first embodiment of the present invention is mounted on a mounting board such as a printed board by soldering will be described.

FIG. 4A is a sectional view showing a mounted state of the multiple chip resistor according to the first embodiment of the present invention.
(B) is the same top view. When the multiple chip resistor according to the first embodiment of the present invention is mounted by soldering on the solder land pattern 32 of a mounting board such as a printed board with the protective layer 24 facing down, as shown in FIG. Substrate 21
Since the area of the side surface electrode layer (not shown) provided on the side surface of the substrate 21 is small, the side surface of the substrate 21 is hardly soldered, and the fillet 33 of this solder is only slightly formed. That is, the upper surface electrode layer (not shown) provided on the side of the substrate 21 is soldered to the solder land pattern 32 of the mounting substrate, and the fillet 33 is slightly formed by this solder. At this time,
As shown in the top view of the mounting state in FIG. 4B, the area 35 for soldering the side surface is smaller than the component area 34 of the multiple chip resistor, and as a result, the mounting area 36 combining these is reduced. It can be reduced.

Further, as shown in FIG.
When the area obtained by adding the area 35 required for soldering the side surface to the mounting surface 36 is, for example, 1.0 ×
When the mounting area is compared with a product having a conventional structure in which a multiple chip resistor having a size of 1.0 mm is mounted, a reduction of about 20% can be achieved. Therefore, according to the configuration of the present invention, since the area of the electrode provided on the side surface of the board 21 is small, when this multiple chip resistor is mounted on a mounting board such as a printed board, the soldering area occupying the mounting area is small. And the amount of solder to be used can be reduced because the fillet 33 is formed small.

In the first embodiment of the present invention, the solder plating layer 26 and the protection layer 24 are flush with each other or the height of the solder plating layer 26 is made higher than the protection layer 24, so that the solder plating layer 26 and the protection layer 24 are mounted. Land pattern 32 of time
Thus, a gap is hardly generated, and the mounting quality can be further improved.

In the first embodiment of the present invention, when the upper electrode layer 22 and the protective layer 24 are combined as shown in (Table 1), it is necessary to improve other characteristics as shown in (Table 1). Can be done.

[0047]

[Table 1]

(Embodiment 2) Hereinafter, a multiple chip resistor and a method of manufacturing the same according to Embodiment 2 of the present invention will be described with reference to the drawings.

FIG. 5 is a sectional view of a multiple chip resistor according to the second embodiment of the present invention.

In FIG. 5, reference numeral 41 denotes an insulating substrate containing 96% of alumina. Reference numeral 42 denotes a plurality of pairs of upper electrode layers made of a metal material provided from the side of the upper surface of the substrate 41 to a part of the side surface by a gold-based sputtering method. The ridge line of the upper electrode layer 42 is rounded. I have. The area of the upper electrode layer 42 provided on the side surface of the substrate 41 is less than half the area of the side surface of the substrate 41. Reference numeral 43 denotes a plurality of resistance layers mainly composed of ruthenium oxide provided on the upper surface of the substrate 41 so as to be electrically connected to the plurality of pairs of upper electrode layers. Reference numeral 44 denotes a protective layer made of glass, resin, or the like provided so as to cover at least the upper surfaces of the plurality of resistance layers 43. Reference numerals 45 and 46 denote a nickel plating layer and a solder plating layer which are provided so as to cover the upper electrode layer 42 as necessary, and which ensure reliability and the like at the time of soldering.

A method for manufacturing the multiple chip resistor according to the second embodiment of the present invention having the above-described configuration will be described below with reference to the drawings.

FIGS. 6A to 6C and FIGS.
(C) is a process diagram showing a method for manufacturing a multiple chip resistor in Embodiment 2 of the present invention.

First, as shown in FIG. 6 (a), the surface has a plurality of vertical and horizontal dividing grooves 47, 48 provided on the surface for dividing into strips and individual pieces in a later step. Gold is deposited on the entire upper surface of the sheet-like substrate 41 and the vertical and horizontal division grooves 47 and 48 by using a sputtering method. Thereafter, a heat treatment is performed at a temperature of about 300 to 400 ° C. on the deposited gold as a desired electrode pattern by a photolithography method to form a plurality of pairs of upper electrode layers 42. At this time, since gold is deposited up to the inside of the lateral division groove 48, the upper electrode layer 42 can be formed to the depth of the lateral division groove 48. The vertical and horizontal dividing grooves 4
The depth of the sheet-like substrate 41 with respect to the thickness of the sheet-like substrate 41 is formed so as to be half or less of the thickness of the sheet-like substrate 41 so as not to be broken during handling in the manufacturing process.

Next, as shown in FIG. 6B, a resistive paste containing ruthenium oxide as a main component is printed on the upper surface of the sheet-like substrate 41 so as to electrically connect a plurality of pairs of upper electrode layers 42. Thereafter, the resistive layer 43 is fired at about 850 ° C.
To form

Next, as shown in FIG. 6C, the resistance layer 4
In order to correct the resistance value of No. 3 to a predetermined value, trimming is performed by forming a trimming groove 49 with a YAG laser. At this time, the trimming probe for measuring the resistance value is set on the upper electrode layer 43 to perform trimming.

Next, as shown in FIG. 7A, in order to protect the resistance layer 43 having the corrected resistance value, a paste containing glass as a main component is printed so as to cover at least the resistance layer 43, and about 600 The protective layer 44 is formed by baking at a temperature of ° C. In this case, the print pattern of the protective layer 44 may be formed so as to continuously cover the plurality of resistance layers 43 arranged in the horizontal direction across the vertical division grooves 47.

Next, as shown in FIG. 7B, the sheet-like substrate 41 on which the upper electrode layer 42, the resistive layer 43, the trimming groove 49, and the protective layer 44 are formed is divided along the lateral dividing groove 48. Then, the strip-shaped substrate 50 is formed. At this time, on the side surface in the longitudinal direction of the strip-shaped substrate 50, the upper electrode layer 42 previously formed is formed to the depth of the horizontal dividing groove 48.

Finally, as shown in FIG. 7C, as a preparation step for plating the exposed upper electrode layer 42, the strip-shaped substrate 50 is divided along the vertical dividing grooves 47. Then, an individual substrate 51 is formed. Then, a nickel plating layer (not shown) and a solder plating layer (not shown) are formed by electroplating so as to cover the exposed upper electrode layer 42 to manufacture a multiple chip resistor. It is.

The effect of soldering the multiple chip resistor constructed as described above and manufactured in the second embodiment of the present invention to a mounting board will be described in comparison with the first embodiment of the present invention. Since they are the same, the description is omitted.

In Embodiment 2 of the present invention, the upper electrode layer 42, the resistance layer 43 and the protection layer 44 are formed as shown in Table 2.
When the combinations shown in (1) and (2) are used, other characteristics can be improved as shown in (Table 2).

[0061]

[Table 2]

(Embodiment 3) Hereinafter, a multiple chip resistor and a method of manufacturing the same according to Embodiment 3 of the present invention will be described with reference to the drawings.

FIG. 8 is a sectional view of a multiple chip resistor according to the third embodiment of the present invention.

In FIG. 8, reference numeral 61 denotes an insulating substrate containing 96% of alumina. Reference numeral 62 denotes a plurality of pairs of first upper electrode layers formed by firing a gold-based organometallic compound provided from the side portion of the upper surface of the substrate 61 to a part of the side surface. The ridge is rounded. The area of the upper electrode layer 62 provided on the side surface of the substrate 61 is less than half the area of the side surface of the substrate 61. Numeral 63 denotes a plurality of pairs of second upper electrodes made of a silver-based conductive powder containing glass so as to be electrically connected to the plurality of pairs of first upper electrode layers 62. Layer. Reference numeral 64 denotes a plurality of resistance layers mainly composed of ruthenium oxide provided on the upper surface of the substrate 61 so as to be electrically connected to the plurality of pairs of second upper electrode layers 63. 65
Is a protective layer made of glass, resin, or the like provided so as to cover at least the upper surfaces of the plurality of resistance layers 64.
66 and 67 are the first and second upper electrode layers 6 if necessary.
A nickel plating layer and a solder plating layer which are provided so as to cover 2, 63 and which can ensure the reliability and the like at the time of soldering.

A method of manufacturing the multiple chip resistor according to the third embodiment of the present invention configured as described above will be described below with reference to the drawings.

FIGS. 9A to 9C and FIGS.
(D) is a process diagram showing a method for manufacturing a multiple chip resistor in Embodiment 3 of the present invention.

First, as shown in FIG. 9 (a), a plurality of vertical and horizontal dividing grooves 68, 69 provided on the surface for dividing into strips and individual pieces in a later step are provided. A gold-based organic metal is contained in the sheet-like substrate 61 and the lateral dividing groove 69 across the lateral dividing groove 69 of the sheet-like substrate 61 containing 96% alumina having excellent insulating properties. After printing the resulting electrode paste, about 850
C. to form a plurality of pairs of first upper electrode layers 62. At this time, the electrode paste is divided into the horizontal dividing grooves 69.
Therefore, the first upper electrode layer 62 can be formed to the depth of the lateral division groove 69. Further, the sheet-like substrate 6 of the vertical and horizontal dividing grooves 68, 69 is formed.
The thickness of the sheet substrate 61 is formed so as to be not more than half the thickness of the sheet substrate 61 so as not to be broken during handling in the manufacturing process.

Next, as shown in FIG. 9B, a silver-based conductive powder and glass are applied on the upper surface of the sheet-like substrate 61 so as to partially overlap a plurality of pairs of the first upper electrode layers 62. The printed electrode paste is fired at about 850 ° C. to form a plurality of pairs of second upper electrode layers 63.

Next, as shown in FIG. 9C, the upper surface of the sheet-like substrate 61 is electrically connected to a plurality of pairs of second upper electrode layers 63 so that a resistance mainly composed of ruthenium oxide is formed on the upper surface. After printing the paste, the paste is fired at about 850 ° C. to form a plurality of resistance layers 64.

Next, as shown in FIG. 10A, in order to correct the resistance value of the resistance layer 64 to a predetermined value, trimming is performed by forming a trimming groove 70 with a YAG laser. At this time, the trimming probe for measuring the resistance value is set on the second upper electrode layer 63 to perform trimming.

Next, as shown in FIG. 10B, in order to protect the resistance layer 64 having the corrected resistance value, a paste containing glass as a main component is printed so as to cover at least the resistance layer 64, and about 600 The protective layer 65 is formed by baking at a temperature of ° C. In this case, the print pattern of the protective layer 65 may be formed so as to continuously cover the plurality of resistance layers 64 arranged in the horizontal direction across the divisional grooves 68 in the vertical direction.

Next, as shown in FIG. 10C, the sheet-like substrate 61 on which the first upper electrode layer 62, the resistance layer 64, the trimming groove 70, and the protective layer 65 are formed is divided into the horizontal dividing grooves 6.
9 to form a strip-shaped substrate 71. At this time, the first upper electrode layer 62 formed previously is formed on the side surface in the longitudinal direction of the strip-shaped substrate 71 to the depth of the horizontal dividing groove 69.

Finally, as shown in FIG. 10D, as a preparation step for plating the exposed first and second upper electrode layers 62 and 63, the strip-shaped substrate 71 is The substrate is divided along the division grooves 68 to form the individual pieces of the substrate 72. Then, the exposed first and second upper electrode layers 62,
A nickel plating layer (not shown) and a solder plating layer (not shown) are formed by electroplating so as to cover 63, and a multiple chip resistor is manufactured.

A description will be given of a state in which the multiple chip resistor constructed and manufactured in the third embodiment of the present invention is mounted on a mounting board such as a printed board by soldering.

FIG. 11A is a sectional view showing a mounted state of a multiple chip resistor according to the third embodiment of the present invention.
(B) is the same top view. When the multiple chip resistor according to the third embodiment of the present invention is mounted by soldering on the solder land pattern 73 of a mounting board such as a printed board with the protective layer 65 facing down, as shown in FIG. Substrate 6
Since the area of the side surface electrode layer (not shown) provided on the side surface of the substrate 1 is small, the side surface of the substrate 61 is hardly soldered, and the fillet 74 made of this solder is only slightly formed. That is, since the first and second upper electrode layers (not shown) provided on the side portions of the substrate 61 are soldered to the solder land patterns 73 of the mounting substrate, the fillets 74 are slightly formed by the solder. State. At this time, as shown in the top view of the mounting state of FIG. 11B, the area 76 for soldering the side surface to the component area 75 of the multiple chip resistor becomes small, and as a result, the mounting of these The area 77 can be reduced.

Further, as shown in FIG.
In a case where the area obtained by adding the area 5 necessary for soldering the side surface 5 and the area 76 becomes the mounting area 77, for example, 1.0 ×
When the mounting area is compared with a product having a conventional structure in which a multiple chip resistor having a size of 1.0 mm is mounted, a reduction of about 20% can be achieved. Therefore, according to the configuration of the present invention, since the area of the electrode provided on the side surface of the board 61 is small, when this multiple chip resistor is mounted on a mounting board such as a printed board, the soldering area occupying the mounting area is small. And the fillet 74 can be formed small, so that the amount of solder to be used can be reduced.

In the third embodiment of the present invention, the solder plating layer 67 and the protection layer 65 are flush with each other or the height of the solder plating layer 67 is made higher than the protection layer 65, so that the solder plating layer 67 and the protection layer 65 are mounted. Land pattern 73 of time
This makes it difficult for a gap to be formed between them, so that the mounting quality can be further improved.

In the third embodiment of the present invention, when the combination of the second upper electrode layer 63 and the protective layer 64 is made as shown in (Table 3), other characteristics are obtained as shown in (Table 3). It can be improved.

[0079]

[Table 3]

(Embodiment 4) Hereinafter, a multiple chip resistor and a method of manufacturing the same according to Embodiment 4 of the present invention will be described with reference to the drawings.

FIG. 12 is a sectional view of a multiple chip resistor according to the fourth embodiment of the present invention.

In FIG. 12, reference numeral 81 denotes an insulating substrate containing 96% of alumina. Reference numeral 82 denotes a plurality of pairs of first upper electrode layers made of a metal material provided from a side portion of the upper surface of the substrate 81 to a part of the side surface thereof by a gold-based sputtering method, and ridges of the first upper electrode layer 82. Is rounded. The area of the first upper electrode layer 82 provided on the side surface of the substrate 81 is less than half the area of the side surface of the substrate 81. Reference numeral 83 denotes a plurality of pairs of second top electrodes made of silver-based conductive powder provided with glass and provided on the upper surface of the substrate 81 so as to be electrically connected to the plurality of pairs of first top electrode layers 82. Layer. 84 is the second pair of the plurality
And a plurality of resistance layers mainly composed of ruthenium oxide provided on the upper surface of the substrate 81 so as to be electrically connected to the upper electrode layer 83 of FIG. 85 is at least the plurality of resistance layers 84
Is a protective layer made of glass, resin, or the like provided so as to cover the upper surface of. 86 and 87 are a nickel plating layer and a solder plating layer which are provided so as to cover the first and second upper electrode layers 82 and 83 as necessary, and which ensure reliability and the like at the time of soldering. .

A method of manufacturing the multiple chip resistor according to the fourth embodiment of the present invention having the above structure will be described below with reference to the drawings.

FIGS. 13 (a) to 13 (c) and FIG. 14 (a)
FIGS. 7A to 7D are process diagrams showing a method for manufacturing a multiple chip resistor according to Embodiment 4 of the present invention.

First, as shown in FIG. 13 (a), a plurality of vertical and horizontal dividing grooves 88, 89 provided on the surface for dividing into strips and individual pieces in a later step are heat-resistant. Gold is deposited on the entire upper surface of the sheet-like substrate 81 and the vertical and horizontal dividing grooves 88 and 89 by a sputtering method and containing 96% of alumina having excellent insulating properties. Thereafter, a heat treatment is performed on the deposited gold as a desired electrode pattern at a temperature of about 300 to 400 ° C. by a photolithography method to form a plurality of pairs of first upper electrode layers 82. At this time, since gold is deposited up to the inside of the lateral division groove 89, the first upper electrode layer 8 extends to the depth of the lateral division groove 89.
2 can be formed. Further, the depth of the vertical and horizontal dividing grooves 88, 89 with respect to the thickness of the sheet-like substrate 81 is formed so as to be not more than half of the thickness of the substrate 81 so as not to be broken during handling in the manufacturing process. ing.

Next, as shown in FIG. 13B, a silver-based conductive powder and glass are applied on the upper surface of the sheet-like substrate 81 so as to partially overlap a plurality of pairs of the first upper electrode layers 82. After printing the contained electrode paste, it is fired at about 850 ° C. to form a plurality of pairs of second upper electrode layers 83.

Next, as shown in FIG. 13C, a resistance mainly composed of ruthenium oxide is formed on the upper surface of the sheet-like substrate 81 so as to electrically connect a plurality of pairs of second upper electrode layers 83. After printing the paste, the paste is fired at about 850 ° C. to form a plurality of resistance layers 84.

Next, as shown in FIG. 14A, in order to correct the resistance value of the resistance layer 84 to a predetermined value, trimming is performed by applying a trimming groove 90 using a YAG laser. At this time, the trimming probe for measuring the resistance value is set on the second upper electrode layer 83 to perform trimming.

Next, as shown in FIG. 14B, in order to protect the resistance layer 84 having the corrected resistance value, a paste containing glass as a main component is printed so as to cover at least the resistance layer 84, and about 600 The protective layer 85 is formed by baking at a temperature of ° C. In this case, the print pattern of the protective layer 85 may be formed so as to continuously cover the plurality of resistive layers 84 arranged in the horizontal direction across the dividing grooves 88 in the vertical direction.

Next, as shown in FIG. 14C, the sheet-like substrate 81 on which the first upper electrode layer 82, the resistance layer 84, the trimming groove 90, and the protective layer 85 are formed is divided into the horizontal dividing grooves 8
9 to form a strip-shaped substrate 91. At this time, the first upper electrode layer 82 formed earlier is formed on the side surface in the longitudinal direction of the strip-shaped substrate 91 to the depth of the horizontal dividing groove 89.

Finally, as shown in FIG. 14D, as a preparation step for plating the exposed first and second upper electrode layers 82 and 83, the strip-shaped substrate 91 is The substrate is divided along the dividing groove 88 to form an individual substrate 92. Then, the exposed first and second upper electrode layers 82,
A nickel plating layer (not shown) and a solder plating layer (not shown) are formed by electroplating so as to cover 83, and a multiple chip resistor is manufactured.

The effect of soldering the multiple chip resistor constructed and manufactured as described above in the fourth embodiment of the present invention to a mounting substrate will be described with reference to the third embodiment of the present invention. Since they are the same, the description is omitted.

In the fourth embodiment of the present invention, the first upper electrode layer 82, a plurality of pairs of second upper electrode layers 83,
When the combination of the resistance layer 84 and the protective layer 85 is as shown in (Table 4), as shown in (Table 4), other characteristics can be improved.

[0094]

[Table 4]

[0095]

As described above, in the multiple chip resistor of the present invention, a plurality of pairs of upper electrode layers are provided from the side of the upper surface of the substrate to a part of the side surface, and the upper electrode layer provided on the side surface of the substrate is provided. Is less than half of the thickness of the board, and this top electrode layer is provided on only a part of the side face, not the entire side face of the board, so when this multiple chip resistor is mounted on the mounting board by soldering In addition, a portion where a solder fillet is formed can be reduced, and thereby, a soldering area occupying a mounting area can be reduced. Also, since it is a multiple chip, it is not necessary to form a plurality of pairs of solder fillets as compared with a single chip, and the area of a solder land pattern required at the time of mounting by soldering can be further reduced, furthermore, This has the effect that the mounting area can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a multiple chip resistor according to a first embodiment of the present invention.

FIGS. 2A to 2C are process diagrams showing a method for manufacturing the multiple chip resistor.

FIGS. 3A to 3C are process diagrams showing a method for manufacturing the multiple chip resistor.

FIG. 4A is a cross-sectional view showing a mounting state of the multiple chip resistor. FIG. 4B is a top view showing a mounting state of the multiple chip resistor.

FIG. 5 is a sectional view of a multiple chip resistor according to a second embodiment of the present invention.

FIGS. 6A to 6C are process diagrams showing a method for manufacturing the multiple chip resistor.

FIGS. 7A to 7C are process diagrams showing a method for manufacturing the multiple chip resistor.

FIG. 8 is a sectional view of a multiple chip resistor according to a third embodiment of the present invention.

FIGS. 9A to 9C are process diagrams showing a method for manufacturing the multiple chip resistor.

FIGS. 10A to 10D are process diagrams showing a method for manufacturing the multiple chip resistor.

11A is a cross-sectional view showing a mounting state of the multiple chip resistor. FIG. 11B is a top view showing a mounting state of the multiple chip resistor.

FIG. 12 is a sectional view of a multiple chip resistor according to a fourth embodiment of the present invention.

13A to 13C are process diagrams showing a method for manufacturing the multiple chip resistor.

FIGS. 14A to 14D are process diagrams showing a method for manufacturing the multiple chip resistor.

15A is a perspective view of a conventional multiple chip resistor, and FIG. 15B is a cross-sectional view of a conventional multiple chip resistor.

16A and 16B are process diagrams showing a method for manufacturing the multiple chip resistor.

FIGS. 17A and 17B are process diagrams showing a method for manufacturing the multiple chip resistor.

FIG. 18A is a cross-sectional view showing a mounting state of the multiple chip resistor. FIG. 18B is a top view showing a mounting state of the multiple chip resistor.

[Explanation of symbols]

 21, 41, 61, 81 Substrate 22, 42 Top electrode layer 23, 43, 64, 84 Resistive layer 24, 44, 65, 85 Protective layer 27, 47, 68, 88 Vertical division grooves 28, 48, 69, 89 Horizontal dividing groove 30, 50, 71, 91 Strip-shaped substrate 62, 82 First upper electrode layer 63, 83 Second upper electrode layer

Claims (14)

[Claims] 1. A substrate, a plurality of pairs of upper electrode layers provided from a side portion of an upper surface of the substrate to a part of a side surface, and a plurality of upper electrode layers provided to be electrically connected to the plurality of upper electrode layers. A multiple chip resistor comprising: a plurality of resistance layers; and a protection layer provided so as to cover at least the plurality of resistance layers. 2. A plurality of pairs of upper electrode layers are covered with a plurality of pairs of plating layers, and the plurality of pairs of plating layers and the protection layer are flush with each other or the height of the plurality of pairs of plating layers is higher than the protection layer. 2. The multiple chip resistor according to claim 1, wherein: 3. The multiple chip resistor according to claim 1, wherein the plurality of pairs of upper electrode layers are made of a metal material obtained by firing a gold-based organometallic compound. 4. The multiple chip resistor according to claim 1, wherein a plurality of pairs of upper electrode layers are formed of a metal material provided by a nickel-based or gold-based sputtering method. 5. The multiple chip resistor according to claim 1, wherein ridges of the plurality of pairs of upper electrode layers are rounded. 6. A substrate, a plurality of pairs of first upper electrode layers provided from a side portion of an upper surface of the substrate to a part of a side surface, and electrically connected to the plurality of pairs of first upper electrode layers. A plurality of pairs of second upper electrode layers provided on the upper surface of the substrate; and a plurality of resistance layers provided to be electrically connected to the plurality of pairs of second upper electrode layers. A multiple chip resistor comprising a protective layer provided so as to cover the plurality of resistance layers. 7. A plurality of pairs of the first upper surface electrode layer and the second upper surface electrode layer are covered with a plurality of pairs of plating layers, and the plurality of pairs of plating layers and the protective layer are flush with each other or the plurality of pairs of platings are provided. 7. The multiple chip resistor according to claim 6, wherein a height of the layer is higher than that of the protective layer. 8. A plurality of pairs of first upper electrode layers are formed of a metal material obtained by firing a gold-based organometallic compound.
A multiple chip resistor as described. 9. The multiple chip resistor according to claim 6, wherein a plurality of pairs of the first upper electrode layers are made of a metal material provided by a nickel-based or gold-based sputtering method. 10. The multiple chip resistor according to claim 6, wherein the ridges of the plurality of pairs of second upper electrode layers are rounded. 11. A step of forming a plurality of pairs of upper surface electrode layers by a printing method on the upper surface of the sheet-like substrate and in the division grooves over the division groove of the sheet-like substrate having the division grooves; A step of forming a plurality of resistive layers so as to electrically connect the upper electrode layers, a step of forming a protective layer so as to cover at least the plurality of resistive layers, and a step of forming the protective layer so as to cover the plurality of resistive layers. A method for manufacturing a multiple chip resistor, comprising: a step of dividing the sheet-like substrate into strip-shaped substrates by dividing grooves; and a step of dividing the strip-shaped substrate into individual pieces. 12. A step of forming a plurality of pairs of upper surface electrode layers by a sputtering method on the upper surface of the sheet-like substrate and in the division grooves so as to straddle the division grooves of the sheet-like substrate having the division grooves; A step of forming a plurality of resistive layers so as to electrically connect the upper electrode layers, a step of forming a protective layer so as to cover at least the plurality of resistive layers, and a step of forming the protective layer so as to cover the plurality of resistive layers. A method for manufacturing a multiple chip resistor, comprising: a step of dividing the sheet-like substrate into strip-shaped substrates by dividing grooves; and a step of dividing the strip-shaped substrate into individual pieces. 13. A step of forming a plurality of pairs of first upper surface electrode layers by a printing method on the upper surface of the sheet-like substrate and in the division grooves over the division grooves of the sheet-like substrate having the division grooves; Forming a plurality of pairs of second upper electrode layers so as to be electrically connected to the plurality of pairs of first upper electrode layers, and electrically connecting the plurality of pairs of second upper electrode layers. A step of forming a plurality of resistance layers, and a step of forming a protective layer so as to cover at least the plurality of resistance layers,
Production of a multiple chip resistor comprising: a step of dividing the sheet-like substrate into strip-shaped substrates by dividing grooves of the sheet-shaped substrate obtained in the previous step; and a step of dividing the strip-shaped substrate into individual pieces. Method. 14. A step of forming a plurality of pairs of first upper electrode layers by sputtering on the upper surface of the sheet-like substrate and in the divisional grooves over the divisional grooves of the sheet-like substrate having the divisional grooves; Forming a plurality of pairs of second upper electrode layers so as to be electrically connected to the plurality of pairs of first upper electrode layers, and electrically connecting the plurality of pairs of second upper electrode layers. A step of forming a plurality of resistance layers, a step of forming a protective layer so as to cover at least the plurality of resistance layers, and a step of dividing the sheet-shaped substrate into strip-shaped substrates by dividing the sheet-shaped substrate obtained in the previous step. And a step of dividing the strip-shaped substrate into individual pieces.