JP2000340652A - Thin-film semiconductor device, and its manufacture - Google Patents
Thin-film semiconductor device, and its manufactureInfo
- Publication number
- JP2000340652A JP2000340652A JP11152384A JP15238499A JP2000340652A JP 2000340652 A JP2000340652 A JP 2000340652A JP 11152384 A JP11152384 A JP 11152384A JP 15238499 A JP15238499 A JP 15238499A JP 2000340652 A JP2000340652 A JP 2000340652A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact hole
- lower electrode
- interlayer insulating
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 239000010409 thin film Substances 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 239000011229 interlayer Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000011521 glass Substances 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 claims description 99
- 230000000149 penetrating effect Effects 0.000 claims description 10
- 230000007423 decrease Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 claims 1
- 238000001259 photo etching Methods 0.000 abstract description 10
- 238000004528 spin coating Methods 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 2
- 238000005530 etching Methods 0.000 description 5
- 230000008961 swelling Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Photovoltaic Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、薄膜半導体装置及
びその製造方法に関する。The present invention relates to a thin film semiconductor device and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】薄膜半導体装置においては、層間絶縁膜
を挟んで電極は多層に形成されており、この多層の電極
を確実に導通させることが重要である。ここで、図３及
び図４を参照して、従来の薄膜半導体装置の製造方法に
ついて説明する。図３及び図４は、従来の薄膜半導体装
置の製造工程の一部を模式的に表した工程断面図であ
る。2. Description of the Related Art In a thin film semiconductor device, electrodes are formed in multiple layers with an interlayer insulating film interposed therebetween, and it is important to ensure conduction of the multilayer electrodes. Here, a conventional method of manufacturing a thin-film semiconductor device will be described with reference to FIGS. 3 and 4 are process cross-sectional views schematically showing a part of the manufacturing process of a conventional thin film semiconductor device.
【０００３】まず、図３（ａ）に示すように、ガラス基
板１の表面に、例えば、アルミニウムをスパッタ法を用
いて５００〜１０００ｎｍ程度の膜厚で成膜した後、フ
ォトエッチング技術を用いて所定の形状に加工して下部
電極２を形成する。続いて、例えば、窒化シリコン膜を
ＣＶＤ法を用いて４００〜５００ｎｍ程度の膜厚で成膜
し層間絶縁膜３を形成する。First, as shown in FIG. 3A, for example, aluminum is formed on a surface of a glass substrate 1 to a thickness of about 500 to 1000 nm by a sputtering method, and then a photo-etching technique is used. The lower electrode 2 is formed by processing into a predetermined shape. Subsequently, for example, a silicon nitride film is formed to a thickness of about 400 to 500 nm by using the CVD method, and the interlayer insulating film 3 is formed.
【０００４】次に、図３（ｂ）に示すように、層間絶縁
膜３上に、例えば、有機平坦化膜をスピンコート法で塗
布して平坦化膜５を形成する。次に、図３（ｃ）に示す
ように、フォトエッチング技術により、下部電極２まで
貫通するように、平坦化膜５と層間絶縁膜３に開口を形
成する。Next, as shown in FIG. 3B, an organic flattening film, for example, is applied on the interlayer insulating film 3 by spin coating to form a flattening film 5. Next, as shown in FIG. 3C, openings are formed in the planarizing film 5 and the interlayer insulating film 3 so as to penetrate to the lower electrode 2 by a photoetching technique.
【０００５】[0005]
【発明が解決しようとする課題】上述した従来の薄膜半
導体装置の製造方法では、コンタクトホール形成時に平
坦化膜５と層間絶縁膜３を同時にエッチングを行わなけ
ればならないが、層間絶縁膜３のエッチングレートが有
機平坦化膜に対して大きいため、層間絶縁膜３のエッチ
ングが進行しすぎて、平坦化膜５と層間絶縁膜３の界面
でオーバーハング８が起こるという問題が生じていた。In the above-mentioned conventional method for manufacturing a thin film semiconductor device, the planarizing film 5 and the interlayer insulating film 3 must be etched at the same time when the contact holes are formed. Since the rate is higher than that of the organic flattening film, the etching of the interlayer insulating film 3 progresses too much, causing a problem that an overhang 8 occurs at the interface between the flattening film 5 and the interlayer insulating film 3.
【０００６】このようなオーバーハングを防止する方法
として、図４に示すように、平坦化膜５と層間絶縁膜３
とを別々にエッチングする方法がある。この方法では、
図４（ａ）、（ｂ）に示すように、ガラス基板１上に下
部電極２を形成後、層間絶縁膜３と平坦化膜５を積層し
た後、図４（ｃ）に示すように、フォトエッチング技術
を用いて平坦化膜５のみのコンタクトホールを開口した
後、さらに、図４（ｄ）に示すように、フォトエッチン
グ技術を用いて層間絶縁膜にコンタクトホールを開口す
る。As a method for preventing such overhang, as shown in FIG. 4, a planarizing film 5 and an interlayer insulating film 3 are formed.
And etching separately. in this way,
As shown in FIGS. 4A and 4B, after the lower electrode 2 is formed on the glass substrate 1, the interlayer insulating film 3 and the flattening film 5 are laminated, and as shown in FIG. After a contact hole of only the flattening film 5 is opened by using the photo-etching technique, as shown in FIG. 4D, a contact hole is further opened in the interlayer insulating film by using the photo-etching technique.
【０００７】この製造方法では、図３（ｃ）に示したオ
ーバーハング８は防ぐことができる。しかし、平坦化膜
５である有機平坦化膜は、レジストを剥離するための有
機溶剤などを吸収しやすく、有機溶剤の吸収によって膨
潤９を引き起こす。この膨潤９により平坦化膜５と層間
絶縁膜３との界面でその後に形成するＩＴＯに亀裂が発
生してしまう。In this manufacturing method, the overhang 8 shown in FIG. 3C can be prevented. However, the organic planarizing film, which is the planarizing film 5, easily absorbs an organic solvent or the like for removing the resist, and causes swelling 9 due to the absorption of the organic solvent. The swelling 9 causes cracks to be formed in the subsequently formed ITO at the interface between the planarizing film 5 and the interlayer insulating film 3.
【０００８】上述した問題は、いずれの場合もコンタク
トホール内の平坦化膜５と層間絶縁膜３との界面で起き
ているため、下部電極２と上部電極とをつなぐ配線が段
切れを起こしてしまうという問題があった。In any case, since the above-mentioned problem occurs at the interface between the planarizing film 5 and the interlayer insulating film 3 in the contact hole, the wiring connecting the lower electrode 2 and the upper electrode is disconnected. There was a problem that it would.
【０００９】本発明は、上記問題点に鑑みてなされたも
のであって、その主たる目的は、下部電極と上部電極と
をつなぐ配線に段切れが生じることのない薄膜半導体装
置及びその製造方法を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a main object of the present invention is to provide a thin film semiconductor device in which a wiring connecting a lower electrode and an upper electrode is not disconnected, and a method of manufacturing the same. To provide.
【００１０】[0010]
【課題を解決するための手段】上記目的を達成するため
に、本発明は、第１の視点において、ガラス基板上に配
設された下部電極と、該下部電極上に形成される層間絶
縁膜及び平坦化膜を挟んで配設される上部電極とが、前
記層間絶縁膜及び前記平坦化膜に形成したコンタクトホ
ールを介して接続される薄膜半導体装置において、前記
層間絶縁膜に前記下部電極まで貫通する第１のコンタク
トホールを有し、前記平坦化膜に前記下部電極まで貫通
する第２のコンタクトホールを有し、該第２のコンタク
トホールの前記下部電極側の開口が、前記第１のコンタ
クトホールの開口の内側に形成されるものである。According to a first aspect of the present invention, there is provided a lower electrode provided on a glass substrate and an interlayer insulating film formed on the lower electrode. A thin film semiconductor device in which an upper electrode provided with a flattening film interposed therebetween is connected through a contact hole formed in the interlayer insulating film and the flattening film. A first contact hole penetrating therethrough, a second contact hole penetrating the planarization film to the lower electrode, and an opening of the second contact hole on the lower electrode side is the first contact hole; It is formed inside the opening of the contact hole.
【００１１】また、本発明は、第２の視点において、薄
膜半導体装置の製造方法を提供する。該製造方法は、ガ
ラス基板上に配設された下部電極と、該下部電極上に形
成される層間絶縁膜及び平坦化膜を挟んで配設される上
部電極とを、前記層間絶縁膜及び前記平坦化膜に形成し
たコンタクトホールを介して接続する薄膜半導体装置の
製造方法において、前記層間絶縁膜形成後、前記平坦化
膜形成前に、前記層間絶縁膜に前記下部電極まで貫通す
る第１のコンタクトホールを形成する工程と、前記平坦
化膜形成後、該平坦化膜に前記下部電極まで貫通する第
２のコンタクトホールを形成する工程と、を少なくとも
有するものである。The present invention provides, in a second aspect, a method of manufacturing a thin film semiconductor device. The manufacturing method includes: a lower electrode provided on a glass substrate; and an upper electrode provided with an interlayer insulating film and a planarizing film formed on the lower electrode interposed therebetween. In the method for manufacturing a thin film semiconductor device connected via a contact hole formed in a flattening film, a first step of penetrating the interlayer insulating film up to the lower electrode after forming the interlayer insulating film and before forming the flattening film. The method includes at least a step of forming a contact hole and a step of forming a second contact hole penetrating to the lower electrode in the flattening film after the formation of the flattening film.
【００１２】[0012]
【発明の実施の形態】本発明に係る薄膜半導体装置の製
造方法は、その好ましい一実施の形態において、ガラス
基板上に形成された下部電極を覆う層間絶縁膜（図２の
３）に予め第１のコンタクトホール（図２の４）を形成
し、その後に形成した平坦化膜（図２の５）に、底部の
開口が第１のコンタクトホールの開口の内側に収まる第
２のコンタクトホール（図２の６）を形成するものであ
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a preferred embodiment of the method for manufacturing a thin film semiconductor device according to the present invention, an interlayer insulating film (3 in FIG. 2) covering a lower electrode formed on a glass substrate is formed in advance. The first contact hole (4 in FIG. 2) is formed, and the second contact hole (5) in which the bottom opening is fit inside the opening of the first contact hole is formed in the flattening film (5 in FIG. 2) formed thereafter. This is to form 6) in FIG.
【００１３】[0013]
【実施例】上記した本発明の実施の形態についてさらに
詳細に説明すべく、本発明の実施例について図１及び図
２を参照して以下に説明する。図１及び図２は、本発明
の一実施例に係る薄膜半導体装置の製造工程の一部を模
式的に示す断面図である。なお、図１（ａ）〜（ｃ）及
び図２（ｄ）、（ｅ）は一連の工程を示す図であり、作
図の都合上分図したものである。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 1 and 2 are cross-sectional views schematically showing a part of a manufacturing process of a thin-film semiconductor device according to one embodiment of the present invention. 1 (a) to 1 (c) and FIGS. 2 (d) and 2 (e) are diagrams showing a series of steps, which are separated for convenience of drawing.
【００１４】まず、図１（ａ）に示すように、例えば、
ガラス基板１等の透明絶縁性基板の表面に、例えば、ア
ルミニウムをスパッタ法を用いて５００〜１０００ｎｍ
程度の膜厚で成膜した後、フォトエッチング技術を用い
て所定の形状に整形して下部電極２を形成し、例えば、
窒化シリコン膜をＣＶＤ法を用いて４００〜５００ｎｍ
程度の膜厚で成膜して層間絶縁膜３を形成する。First, for example, as shown in FIG.
On a surface of a transparent insulating substrate such as the glass substrate 1, for example, aluminum is sputtered to 500 to 1000 nm.
After the film is formed to a thickness of about the same, the lower electrode 2 is formed by shaping it into a predetermined shape by using a photo etching technique.
400-500 nm silicon nitride film by CVD
The interlayer insulating film 3 is formed by forming a film having a thickness of about the same.
【００１５】従来の薄膜半導体装置の製造方法では、こ
の層間絶縁膜３の形成に続いて平坦化膜５を形成する
が、本実施例では、前述した層間絶縁膜３と平坦化膜５
との界面での上部電極の段切れを防止するために、図１
（ｂ）に示すように、層間絶縁膜３に、下部電極２まで
貫通する第１コンタクトホール４をフォトエッチング技
術により開口する。その後、図１（ｃ）に示すように、
例えば、有機平坦化膜をスピンコート法で塗布して平坦
化膜５を形成する。In the conventional method of manufacturing a thin film semiconductor device, a planarizing film 5 is formed following the formation of the interlayer insulating film 3. In this embodiment, however, the above-described interlayer insulating film 3 and the planarizing film 5 are formed.
In order to prevent disconnection of the upper electrode at the interface with
As shown in FIG. 1B, a first contact hole 4 penetrating to the lower electrode 2 is opened in the interlayer insulating film 3 by a photo-etching technique. Then, as shown in FIG.
For example, an organic planarizing film is applied by a spin coating method to form the planarizing film 5.
【００１６】次に、図２（ｄ）に示すように、平坦化膜
５に下部電極２まで貫通する第２コンタクトホール６を
フォトエッチング技術により開口するが、このとき、第
２コンタクトホール６の底面の開口が第１コンタクトホ
ール４の内側に接触しないように開口径を設定する。す
なわち、第２コンタクトホールは平坦化膜５のみに形成
されることになる。Next, as shown in FIG. 2D, a second contact hole 6 penetrating to the lower electrode 2 is opened in the planarizing film 5 by a photo-etching technique. The opening diameter is set so that the opening on the bottom surface does not contact the inside of the first contact hole 4. That is, the second contact hole is formed only in the flattening film 5.
【００１７】そして次に、図２（ｅ）に示すように、例
えば、ＩＴＯ等の透明導電膜を成膜し、フォトエッチン
グ技術を用いて所定の形状に整形して上部電極７を形成
し、下部電極２と接続する。Then, as shown in FIG. 2 (e), for example, a transparent conductive film such as ITO is formed, and the upper electrode 7 is formed by shaping it into a predetermined shape using a photo-etching technique. Connect to lower electrode 2.
【００１８】このように、薄膜半導体装置では、下部電
極２と上部電極７の間に層間絶縁膜３と平坦化膜５が形
成されており、下部電極２と上部電極７とを電気接続す
るためにコンタクトホールを形成しなければならない
が、従来の製造方法では、層間絶縁膜３と平坦化膜５と
を形成した後に、両方の膜を同時にエッチングするか、
若しくは、平坦化膜５をエッチングした後に層間絶縁膜
３をエッチングしていたため、両方の膜の界面で電極の
段切れを起こすオーバーハング８又は膨潤９が生じてい
た。As described above, in the thin-film semiconductor device, the interlayer insulating film 3 and the flattening film 5 are formed between the lower electrode 2 and the upper electrode 7, so that the lower electrode 2 and the upper electrode 7 are electrically connected. In the conventional manufacturing method, after forming the interlayer insulating film 3 and the flattening film 5, both the films are etched at the same time.
Alternatively, since the interlayer insulating film 3 was etched after the flattening film 5 was etched, the overhang 8 or the swelling 9 causing disconnection of the electrode occurred at the interface between both films.
【００１９】しかしながら、本実施例の製造方法では、
層間絶縁膜３に第１のコンタクトホール４を形成した後
に平坦化膜５の形成を行い、この第１のコンタクトホー
ル４よりも小さい開口の第２のコンタクトホール６を平
坦化膜５に対してのみ開口しているために、第２のコン
タクトホール６の内壁は開口上部から底部に至るまで段
差が生じることがない。従って、従来問題となっていた
ような、層間絶縁膜３と平坦化膜５との界面での上部電
極７の段切れが生じることなく、確実に下部電極２と上
部電極７とを接続することが可能となる。However, in the manufacturing method of this embodiment,
After forming the first contact hole 4 in the interlayer insulating film 3, a flattening film 5 is formed, and the second contact hole 6 having an opening smaller than the first contact hole 4 is formed with respect to the flattening film 5. Since only the opening is provided, no step is formed on the inner wall of the second contact hole 6 from the top to the bottom of the opening. Therefore, the lower electrode 2 and the upper electrode 7 can be reliably connected without the step of the upper electrode 7 occurring at the interface between the interlayer insulating film 3 and the flattening film 5 which has conventionally been a problem. Becomes possible.
【００２０】なお、本実施例では、下部電極２と上部電
極７との間に、窒化シリコン膜からなる層間絶縁膜３と
有機物からなる平坦化膜５が形成される場合について説
明したが、本発明は上記実施例に限定されるものではな
く、下部電極２と上部電極７との間に、エッチングレー
トの異なる複数種の絶縁膜が形成され、かつ、その複数
種の絶縁膜を貫通するコンタクトホールが形成されるも
のであれば、同様に適用することができる。In this embodiment, the case where the interlayer insulating film 3 made of a silicon nitride film and the flattening film 5 made of an organic material are formed between the lower electrode 2 and the upper electrode 7 has been described. The present invention is not limited to the above embodiment, and a plurality of types of insulating films having different etching rates are formed between the lower electrode 2 and the upper electrode 7, and a contact penetrating the plurality of types of insulating films is provided. The same can be applied as long as holes are formed.
【００２１】[0021]
【発明の効果】以上説明したように、本発明によれば、
層間絶縁膜と平坦化膜との界面でおきていた膨潤や、エ
ッチングによるオーバーハングによる上部電極の段切れ
を防ぐことができるという効果を奏する。As described above, according to the present invention,
This has the effect of preventing swelling occurring at the interface between the interlayer insulating film and the planarizing film and disconnection of the upper electrode due to overhang due to etching.
【００２２】その理由は、層間絶縁膜に予め第１のコン
タクトホールを形成し、第２のコンタクトホールは平坦
化膜単独に形成しているため、コンタクトホールの側面
に層間絶縁膜との積層部分が存在することはなく、コン
タクトホールの側面の段差部分を無くすことができるか
らである。The reason is that the first contact hole is formed in the interlayer insulating film in advance, and the second contact hole is formed only in the planarization film. Is not present, and the step on the side surface of the contact hole can be eliminated.
【００２３】また、本発明によれば、コンタクトホール
の形成を容易に行うことができるという効果を奏する。
その理由は、本発明では、第２のコンタクトホールは単
層の平坦化膜に対して形成するため、エッチングの選択
比を考慮する必要がなくなるからである。Further, according to the present invention, there is an effect that a contact hole can be easily formed.
The reason is that in the present invention, since the second contact hole is formed in the single-layer flattening film, it is not necessary to consider the etching selectivity.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の一実施例に係る薄膜半導体装置の製造
方法の工程の一部を模式的に示す工程断面図である。FIG. 1 is a process sectional view schematically showing a part of a process of a method of manufacturing a thin film semiconductor device according to one embodiment of the present invention.
【図２】本発明の一実施例に係る薄膜半導体装置の製造
方法の工程の一部を模式的に示す工程断面図である。FIG. 2 is a process cross-sectional view schematically showing a part of the process of the method for manufacturing the thin film semiconductor device according to one embodiment of the present invention.
【図３】従来の薄膜半導体装置の製造工程の一部を示す
工程断面図である。FIG. 3 is a process cross-sectional view showing a part of a manufacturing process of a conventional thin-film semiconductor device.
【図４】従来の薄膜半導体装置の製造工程の一部を示す
工程断面図である。FIG. 4 is a process cross-sectional view showing a part of a manufacturing process of a conventional thin-film semiconductor device.
１ ガラス基板 ２ 下部電極 ３ 層間絶縁膜 ４ 第１コンタクトホール ５ 平坦化膜 ６ 第２コンタクトホール ７ 上部電極 ８ オーバーハング ９ 膨潤 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Lower electrode 3 Interlayer insulating film 4 First contact hole 5 Flattening film 6 Second contact hole 7 Upper electrode 8 Overhang 9 Swelling
Claims (5)
下部電極上に形成される層間絶縁膜及び平坦化膜を挟ん
で配設される上部電極とが、前記層間絶縁膜及び前記平
坦化膜に形成したコンタクトホールを介して接続される
薄膜半導体装置において、 前記層間絶縁膜に前記下部電極まで貫通する第１のコン
タクトホールを有し、前記平坦化膜に前記下部電極まで
貫通する第２のコンタクトホールを有し、該第２のコン
タクトホールの前記下部電極側の開口が、前記第１のコ
ンタクトホールの開口の内側に形成される、ことを特徴
とする薄膜半導体装置。A lower electrode provided on the glass substrate and an upper electrode provided on the lower electrode with an interlayer insulating film and a flattening film interposed therebetween; In the thin film semiconductor device connected via a contact hole formed in a flattening film, the interlayer insulating film has a first contact hole penetrating to the lower electrode, and the flattening film penetrates to the lower electrode. A thin-film semiconductor device having a second contact hole, wherein an opening of the second contact hole on the lower electrode side is formed inside an opening of the first contact hole.
下部電極上に形成される層間絶縁膜及び平坦化膜を挟ん
で配設される上部電極とを、前記層間絶縁膜及び前記平
坦化膜に形成したコンタクトホールを介して接続する薄
膜半導体装置の製造方法において、 前記層間絶縁膜形成後、前記平坦化膜形成前に、前記層
間絶縁膜に前記下部電極まで貫通する第１のコンタクト
ホールを形成する工程と、 前記平坦化膜形成後、該平坦化膜に前記下部電極まで貫
通する第２のコンタクトホールを形成する工程と、を少
なくとも有することを特徴とする薄膜半導体装置の製造
方法。A lower electrode provided on the glass substrate and an upper electrode provided on the lower electrode with an interlayer insulating film and a flattening film interposed therebetween; In the method for manufacturing a thin film semiconductor device connected via a contact hole formed in a flattening film, a first step of penetrating the interlayer insulating film to the lower electrode after forming the interlayer insulating film and before forming the flattening film. Forming a contact hole; and, after forming the planarizing film, forming a second contact hole penetrating the planarizing film to the lower electrode. Method.
極側の開口が、前記第１のコンタクトホールの開口の内
側に配設されるように、前記第２のコンタクトホールが
形成される、ことを特徴とする請求項２記載の薄膜半導
体装置の製造方法。3. The second contact hole is formed such that an opening of the second contact hole on the lower electrode side is disposed inside an opening of the first contact hole. 3. The method for manufacturing a thin film semiconductor device according to claim 2, wherein:
開口上部から開口底部に向かうに従って徐々に小さくな
り、該開口側壁がなだらかな傾斜を有する、ことを特徴
とする請求項２又は３に記載の薄膜半導体装置の製造方
法。4. An opening diameter of said second contact hole is:
4. The method for manufacturing a thin film semiconductor device according to claim 2, wherein the thickness gradually decreases from the upper part of the opening toward the bottom of the opening, and the side wall of the opening has a gentle slope.
極を形成する工程と、 （ｂ）前記下部電極上に層間絶縁膜を形成し、該層間絶
縁膜に前記下部電極に到達する第１のコンタクトホール
を形成する工程と、 （ｃ）前記層間絶縁膜上に平坦化膜を形成し、該平坦化
膜に、その底部の開口が前記第１のコンタクトホールの
開口よりも小さく、前記下部電極に到達する第２のコン
タクトホールを形成する工程と、 （ｄ）前記第２のコンタクトホールの壁面を介して前記
下部電極と接続される上部電極を、前記平坦化膜上層に
形成する工程と、を有することを特徴とする薄膜半導体
装置の製造方法。5. A step of (a) forming a lower electrode having a predetermined shape on a glass substrate; and (b) forming an interlayer insulating film on the lower electrode and reaching the lower electrode in the interlayer insulating film. Forming a first contact hole; and (c) forming a flattening film on the interlayer insulating film, wherein the flattening film has an opening at a bottom portion smaller than the opening of the first contact hole; Forming a second contact hole reaching the lower electrode; and (d) forming an upper electrode connected to the lower electrode through a wall surface of the second contact hole in the upper layer of the planarization film. And a method for manufacturing a thin-film semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11152384A JP2000340652A (en) | 1999-05-31 | 1999-05-31 | Thin-film semiconductor device, and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11152384A JP2000340652A (en) | 1999-05-31 | 1999-05-31 | Thin-film semiconductor device, and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000340652A true JP2000340652A (en) | 2000-12-08 |
Family
ID=15539355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11152384A Pending JP2000340652A (en) | 1999-05-31 | 1999-05-31 | Thin-film semiconductor device, and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000340652A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006093220A (en) * | 2004-09-21 | 2006-04-06 | Mitsubishi Electric Corp | Active matrix display device and manufacturing method thereof |
| CN105742238A (en) * | 2016-03-02 | 2016-07-06 | 京东方科技集团股份有限公司 | Pore structure and array substrate, manufacturing methods of pore structure and array substrate, detection device and display device |
-
1999
- 1999-05-31 JP JP11152384A patent/JP2000340652A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006093220A (en) * | 2004-09-21 | 2006-04-06 | Mitsubishi Electric Corp | Active matrix display device and manufacturing method thereof |
| CN105742238A (en) * | 2016-03-02 | 2016-07-06 | 京东方科技集团股份有限公司 | Pore structure and array substrate, manufacturing methods of pore structure and array substrate, detection device and display device |
| WO2017148014A1 (en) * | 2016-03-02 | 2017-09-08 | 京东方科技集团股份有限公司 | Hole structure and method for manufacturing same, array substrate and method for manufacturing same, detection device, and display device |
| US20180061856A1 (en) * | 2016-03-02 | 2018-03-01 | Boe Technology Group Co., Ltd. | Hole structure and array substrate and fabrication method thereof, detection device and display device |
| EP3425663A4 (en) * | 2016-03-02 | 2019-08-14 | BOE Technology Group Co., Ltd. | HOLE STRUCTURE AND MANUFACTURING METHOD THEREOF, NETWORK SUBSTRATE AND METHOD FOR MANUFACTURING SAME, DETECTION DEVICE, AND DISPLAY DEVICE |
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