JP2000340767A - Method for manufacturing semiconductor memory device - Google Patents

Abstract

(57) [Problem] When a heat treatment process for forming a ferroelectric film is performed after a lower electrode is formed, a large number of precipitates composed of Ir oxide are generated in the ferroelectric film. The object short-circuits the lower electrode and the upper electrode of the capacitor to increase the leakage current of the capacitor, and as a result, lowers the capacity and increases the operating current. A silicon oxide film is formed on a silicon substrate, and a barrier metal layer is formed on the silicon oxide film by a sputtering method. Further, an Ir lower electrode 4 is formed on the barrier metal layer 3 by a sputtering method. Thereafter, the surface of the Ir lower electrode 4 was flattened by a chemical mechanical polishing method. The amount of polishing was set to 5%, that is, about 10 nm with respect to the entire thickness of the Ir film of 210 nm, and the final thickness was set to 200 nm. Next, an SBT film 5 having a thickness of about 150 nm was formed on the Ir lower electrode 4, and then a Pt upper electrode was formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for manufacturing a semiconductor memory device using a ferroelectric capacitor as a charge storage capacitor.

[0002]

2. Description of the Related Art At present, the so-called 1T-1C type in which one memory cell includes one MOS transistor and one capacitor is most widely used in DRAM. In this 1T-1C type DRAM, a silicon oxide film, a silicon nitride film, or the like has been used as a capacitor insulating film. However, with the recent high integration, the memory cell area has been reduced, and the cell capacity has been secured. It's getting harder every year. Therefore, SrTiO ₃ or (B
(a, Sr) A method of using a high dielectric constant material such as TiO ₃ to secure the capacity and use it has been studied.

Further, with the development of thin film forming technology in recent years, a ferroelectric non-volatile memory (hereinafter referred to as "FeRAM") is formed by combining a ferroelectric material having a high dielectric constant and dielectric polarization characteristics with a semiconductor memory technology. Development) has been flourishing. FeRAM devices are not only replaced with conventional non-volatile memories such as EPROMs, EEPROMs, and flash memories, but also DRA, because of their high speed rewriting, low power consumption, and high rewriting endurance.
As a memory that can replace even M, research and development for practical use are actively performed.

At present, ferroelectric materials proposed for application to FeRAM include PbZr _x Ti ₁ -xO (hereinafter, referred to as “PZT”) and SrBi ₂ Ta ₂ O ₉ (hereinafter, “SBT”). "). PZT has been the most studied so far. However, when the polarization inversion is repeated 10 ⁸ to 10 ⁹ times, polarization degradation occurs, and when the film thickness is reduced, the polarization decreases and the leak current increases. Have various problems. On the other hand, SBT requires a heat treatment at about 800 ° C. and higher temperature than PZT in order to obtain ferroelectric characteristics, but has the advantage of less fatigue deterioration due to rewriting and low-voltage operation. . As a method of forming a ferroelectric film, a spin coating method in which a raw material solution synthesized based on an organic metal is applied to a substrate, dried, and a calcined thin film is crystallized and heat-treated in an oxygen atmosphere is mainly used. In addition, a sputtering method, a CVD method, and the like have been studied.

Conventionally, a Pt-based material excellent in high temperature resistance has been used as a capacitor electrode material. However, when a memory cell having a stacked capacitor structure (hereinafter, referred to as “STC structure”) capable of obtaining a high degree of integration by forming a capacitor element on a contact plug connected to a source or a drain of a transistor, Pt Since oxygen easily passes oxygen, there is a problem that the contact plug is oxidized to cause a contact failure, and that element diffusion between the ferroelectric and the plug occurs.

Therefore, recently, Ir-based materials having excellent oxygen barrier properties and mutual diffusion preventing properties have been attracting attention as electrode materials for STC structures. In recent years, in a capacitor using PZT as a ferroelectric material, when an Ir-based material is used for an electrode, it has been found that the fatigue characteristics of the capacitor have been improved.
For example, it is disclosed in JP-A-7-245237.

[0007]

However, when an Ir-based material is used for the lower electrode of the capacitor,
There are the following problems. That is, when a heat treatment process for forming a ferroelectric film is performed after the formation of the lower electrode, a large number of precipitates composed of an oxide of Ir are generated in the ferroelectric film. The precipitate short-circuits the lower electrode and the upper electrode of the capacitor to increase the leakage current of the capacitor, resulting in a decrease in capacity and an increase in operating current. In addition, the step due to the precipitate causes a wiring failure in a subsequent wiring process.

When Ir is heated in a state in which it is directly touched by oxygen, segregation of IrO ₂ occurs. Therefore, when dust or particles are present on the lower electrode surface, defects such as cracks are formed in the ferroelectric thin film, from which oxygen enters, reacts with Ir, and precipitates IrO ₂ . When a ferroelectric thin film is formed by a spin coating method, application and baking of a solution are repeated several times. At this time, the thickness of the SBT film formed by one coating and baking process is as thin as several tens nm. Therefore, not only dust and particles, but also unevenness on the surface of the lower electrode similarly forms an oxygen leak path. Further, when the surface of the lower electrode has large irregularities, a portion where Ir is directly exposed on the film after application of the solution is formed, which also becomes a nucleus for the formation of a precipitate.

An object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a highly reliable ferroelectric capacitor having a small leakage current at a high yield.

[0010]

The method of manufacturing a semiconductor memory device of the present invention According to an aspect of the lower electrode, a dielectric film and an upper electrode, at least the dielectric film lower electrode surface layer Ir or IrO ₂ in contact with Forming a lower electrode material film, removing the surface of the lower electrode material film by a predetermined amount, thereby flattening the surface of the lower electrode material film. Forming a dielectric film and an upper electrode material film on the lower electrode material film, and then patterning the upper electrode material film, the dielectric film, and the lower electrode material film into a predetermined shape. The removal amount of the film surface is 1% or more of the film thickness when the lower electrode material film is formed, and the thickness of the lower electrode material film after removal is 50 nm or more.

The present invention is characterized in that, in addition to the above-described structure, the lower electrode material film is flattened by chemical mechanical polishing or dry etching.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor memory device according to the present invention will be described in detail based on an embodiment.

FIG. 1 is a view showing a manufacturing process of a ferroelectric capacitor used for a semiconductor memory device according to a first embodiment of the present invention, and FIG. 2 is a view showing a relationship between a polishing amount and a film surface roughness. FIG. 3 shows SrBi ₂ Ta ₂ O ₉ (hereinafter referred to as “SB
FIG. 4 is a cross-sectional view of a configuration of a semiconductor memory device according to a third embodiment of the present invention, and FIG. 5 is a diagram showing a structure formed using the present invention. FIG. 4 is a diagram illustrating hysteresis characteristics of a ferroelectric capacitor. (First Embodiment) First, as shown in FIG. 1A, a silicon oxide film 2 having a thickness of 300 nm is formed on a silicon substrate 1 by thermal oxidation, and a barrier is formed on the silicon oxide film 2 by a sputtering method. The metal layer 3 is formed to a thickness of 50 nm. Furthermore, I is formed on the barrier metal layer 3 by sputtering.
The lower electrode 4 is formed.

Thereafter, as shown in FIG. 1B, the surface of the Ir lower electrode 4 was flattened by a chemical mechanical polishing (Chemical Mechanical Polishing) method (hereinafter referred to as "CMP method"). . 3 carriers per minute for loading wafers
5 rotations, the platen where the polishing cloth is installed is 25 times per minute,
The wafer was rotated in the same direction while applying a pressure of 10 PSI between the wafer and the rotating cloth. The slurry amount was 200 SCCM. The amount of polishing was set to about 5%, that is, about 10 nm with respect to the total thickness of 210 nm of the Ir film, and the final thickness was set to 200 nm. If the polishing amount is smaller than 1% with respect to the initial film thickness, as shown in FIG. 2, sufficient planarization cannot be performed by the CMP method. The thickness of the Ir film serving as the lower electrode material after the removal is preferably 50 nm or more. If the thickness is less than 50 nm, the oxygen barrier property is deteriorated, and hillocks and the like accompanying the electrodes are likely to be generated.

The surface roughness of the Ir film before CMP was 30 nm on average in the wafer surface, whereas the film surface roughness after CMP was 5 nm on average in the wafer surface. Here, the film surface roughness is the difference between the maximum value and the minimum value of the cross-sectional shape.
In the present invention, the film surface roughness after CMP is better if it is small, but if it is 50 nm or less, the number of precipitates after ferroelectric formation is sufficiently small, and the leakage current of the capacitor is further reduced. Effective suppression can be achieved.

Next, as shown in FIG. 1C, a MOD (Metal Organic Deposit) is formed on the Ir lower electrode 4.
A ferroelectric thin film was formed by a composition method. SBT solution (solution composition ratio is Sr / Bi /
Ta = 8/24/20) 30 nm per layer by spin coating
After applying about 250 ° C and drying for 5 minutes,
A crystallization heat treatment in an oxygen atmosphere was performed at a substrate temperature of 700 ° C. for 30 minutes. This process is repeated 5 times in total, and the film thickness is 1
An SBT film 5 of about 50 nm was obtained.

Thereafter, the surface of the ferroelectric film was observed using a microscope. FIG. 3 is a plot of the number of foreign particles having a size of 0.3 μm square or more under SBT heat treatment conditions. Graph 31 shows the case where the Ir electrode surface was not processed by the CMP method, and graph 32 shows the case where the Ir electrode surface was processed by the CMP method. As shown in FIG. 3, in the case where the Ir electrode was treated by the CMP method, it can be seen that almost no IrO ₂ precipitate was observed on the SBT surface even after the heat treatment at 700 ° C. (Second Embodiment) In the above-described first embodiment, the CMP method is used as the lower electrode flattening step. However, in the second embodiment, the lower electrode thin film is flattened by dry etching. Was performed. The steps up to the step of forming the Ir lower electrode thin film are the same as those of the first embodiment.

Thereafter, the surface of the lower electrode thin film was etched using an ECR plasma etching apparatus. As the etching gas, the flow rate of chlorine was 36 SCCM, the flow rate of C ₂ F ₆ was 36 SCCM, the flow rate of methane was 4 SCCM, the pressure at the time of etching was 1.4 mTorr, the microwave output was 1000 W, and the RF output was 100 W.

The etching amount is the total film thickness 2 immediately after the film formation.
About 5% of 10 nm was set to 10 nm, and the final film thickness was set to 200 nm. The surface roughness of the Ir film before dry etching was 30 nm on the average on the wafer surface, whereas the film surface roughness after dry etching was 5 nm on the average on the wafer surface. In the present invention, the smaller the surface roughness of the film after dry etching, the better.
nm or less.

Thereafter, the surface of the ferroelectric film was observed using a microscope. As in the case of the first embodiment, it can be seen that almost no IrO ₂ deposition was observed on the SBT surface even after the heat treatment at 700 ° C. for the device in which the Ir electrode was dry-etched. (Third Embodiment) First, as shown in FIG. 4, a LOCOS oxide film 12 having a thickness of about 5000.degree.
Is formed to form an element isolation region. Next, after a selection transistor including the gate electrode 13 and the source / drain regions 14a and 14b is formed, CV is formed as an interlayer insulating film.
A first silicon oxide film 15 is formed to a thickness of about 5000 ° by Method D, and then a contact hole having a diameter of 0.6 μm is formed.

Next, after the polysilicon is buried in the contact hole by the CVD method, the surface is flattened by the CMP method to form a polysilicon plug. Next, as shown in the first embodiment, the surface of the polysilicon plug 16 is wet-processed with hydrofluoric acid on the polysilicon plug 16, and then the Ti is deposited by DC reactive magnetron sputtering.
A film 17 is formed on the polysilicon plug 16 by 200. Thereafter, the Ta _x Si _1-x N _y film 18 serving as a diffusion barrier film is formed by DC reactive magnetron sputtering.
(0.2 ≦ x ≦ 1, 0 ≦ y ≦ 1) on the Ti film 17 by 50
0 ° is formed.

Next, an Ir film 19 serving as a lower electrode is formed thereon by DC reactive magnetron sputtering.
0 nm is formed. Next, the Ir lower electrode 19 was flattened using a CMP method. Approximately 5% of the total Ir film thickness of 210 nm, 10 nm, and a final film thickness of 200 n
m.

Next, an SBT film 20 was formed on the Ir film 19 by using a spin-on method.

Next, after forming a Pt upper electrode 21 having a thickness of 1000 ° by DC reactive magnetron sputtering, the Pt upper electrode 21 is formed to have a size of 1 to 3 μm square by dry etching using Cl _2. did. The underlying SBT film 20 was processed by dry etching using C ₂ F ₆ and Ar. Subsequently, Ir lower electrode 19 formed _{underneath, Ta x Si 1-x N} y diffusion barrier film 1
8 and the Ti film 17 were processed by dry etching using Cl ₂ and C ₂ F ₆ .

After that, a second silicon oxide film 22 is formed as an interlayer insulating film by using a CVD method, a contact hole is formed, and an aluminum lead electrode 23 from the Pt upper electrode 21 of the ferroelectric capacitor is formed. Was formed by a DC reactive magnetron sputtering method.

Next, a contact hole is formed on the source region 14, and an aluminum lead electrode 24 is formed. Finally, a nonvolatile semiconductor memory device having a ferroelectric capacitor device as shown in FIG. 4 is manufactured.

By applying a triangular wave voltage between the Pt upper electrode 21 and the aluminum extraction electrode 23 from the source region 14 to the aluminum extraction electrode 24 from the source region 14 of the capacitor manufactured by the above-described process, as shown in FIG. A hysteresis curve was obtained. The applied triangular wave has an electric field strength of 150 kV / cm and a frequency of 7 kV / cm.
5 Hz. Ferroelectric properties are as follows: Pr = 6 μC / c
m ² , Ec = 35 kV / cm, leak current density when applying +3 V is 8 × 10 ⁻⁸ A / cm ² , and withstand voltage is 10 V
That was all. As a result, ferroelectric characteristics of a sufficient size for use as a ferroelectric capacitor were obtained. Almost no IrO ₂ was deposited on the surface of the SBT film.

In the third embodiment, the lower electrode is planarized by using the CMP method as in the first embodiment. However, the dry etching method is performed in the same manner as in the second embodiment. May be used.

In the above embodiment of the present invention, the ferroelectric
SrBi as film_TwoTa_TwoO₉Was used, but BaBi_TwoNb
_TwoO₉, BaBi_TwoTa_TwoO₉, PbBi_TwoNb_TwoO₉, PbB
i_FourTi_FourO₁₅, SrBi_FourTi_FourO₁₅, BaBi_FourTi_FourO
₁₅, Sr_TwoBi_FourTi_FiveO₁₈, Ba_TwoBi_FourTa_FiveO₁₈, Pb
_TwoBi_FourTi_FiveO₁₈, Na_0.5Bi_4.5Ti_FourO₁₅, K_0.5B
i_4.5Ti_FourO₁₅, SrBi_Two(Ta_xNb_1-x)_TwoO₉,
(SrBi_TwoTa_TwoO₉)_{0. 7}・ (Bi_ThreeTiTa
O₉)_0.3, (SrBi_Two(Ta_xNb_1-x)_TwoO₉)_0.7・
(Bi _ThreeTiTaO₉)_0.3, Bi_FourTi_ThreeO₁₂Bisma, etc.
-Based layered structure compound material or perovska containing lead
A similar effect can be obtained in the case of a compound having a site structure.

Although the MOD method is used as a method for forming a ferroelectric film in the above-described embodiment of the present invention, a sputtering method, a vacuum evaporation method, an MOCVD method, or the like may be used.

Further, in the above embodiment, the lower electrode is made of Ir / TaSiN / Ti.
A laminated electrode of IrO ₂ and Ir (IrO ₂ / Ir), Ir
A laminated electrode of O ₂ , Ir and TaSiN (IrO ₂ / Ir
/ TaSiN), and a laminated electrode of IrO ₂ , Ir, TaSiN, and Ti (IrO ₂ / Ir / TaSiN / Ti) can provide the same effect.

[0032]

As described in detail above, the lower electrode,
In a method of manufacturing a semiconductor memory device having a capacitor comprising a dielectric film and an upper electrode, and a lower electrode surface layer at least in contact with the dielectric film being made of Ir or IrO ₂ , after forming a lower electrode material film, Flattening the surface of the lower electrode material film by removing a predetermined amount of the electrode material film surface; and forming a dielectric film and an upper electrode material film on the lower electrode material film, and then removing the upper electrode material film. Patterning the film, the dielectric film and the lower electrode material film into a predetermined shape, wherein the removal amount is 1% or more of the film thickness when the lower electrode wiring material is formed, and the lower electrode after the removal is removed. By using the present invention in which the thickness of the material is 50 nm or more, generation of an oxygen leak path is suppressed, and
The leakage current of the capacitor can be suppressed by suppressing the exposure of the projection on the lower electrode surface from the dielectric film, which is a nucleus of the formation of the precipitate, which occurs when the dielectric film is formed. As a result, a decrease in the capacitance of the capacitor and an increase in the operating current can be suppressed. In addition, by reducing the step due to the precipitate generated conventionally, a wiring defect can be suppressed in a subsequent wiring step.

Further, a predetermined amount of the lower electrode surface can be easily removed by chemical mechanical polishing or dry etching.

[Brief description of the drawings]

FIG. 1 is a process diagram of forming a capacitor of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a polishing amount and a film surface roughness.

FIG. 3 is a diagram showing a relationship between an SBT formation temperature and the number of foreign substances.

FIG. 4 is a configuration sectional view of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a hysteresis characteristic of a ferroelectric capacitor using the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Silicon oxide film 3 TaSiN barrier metal film 4 Lower electrode Ir layer 5 SrBi ₂ Ta ₂ O ₉ film 11 Silicon substrate 12 Locos film 13 Gate electrode 14a Source region 14b Drain region 15 First silicon oxide film 16 Polysilicon plug 17 Ti film _{18 Ta x Si 1-x N} y film 19 Ir lower electrode 20 SBT film 21 Pt upper electrode 22 and the second silicon oxide film 23 first aluminum extraction electrode 24 and the second aluminum lead electrode

 ────────────────────────────────────────────────── ─── Continued on the front page F term (reference) 5F004 AA11 AA16 BA14 CA02 CA03 DA00 DA02 DA04 DB08 EB02 5F083 AD21 AD49 FR02 GA06 JA13 JA14 JA15 JA17 JA36 JA38 JA39 JA40 JA43 MA05 MA06 MA17 PR03 PR21 PR22 PR23 PR33 PR39 PR40

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor memory device comprising a capacitor comprising a lower electrode, a dielectric film and an upper electrode, wherein a lower electrode surface layer at least in contact with said dielectric film is made of Ir or IrO _2. After forming the film, a step of flattening the surface of the lower electrode material film by removing a predetermined amount of the surface of the lower electrode material film; and forming a dielectric film and an upper electrode material film on the lower electrode material film. Patterning the upper electrode material film, the dielectric film, and the lower electrode material film into a predetermined shape after the formation, and the removal amount of the surface of the lower electrode material film is reduced when the lower electrode material film is formed. 1% or more of the film thickness, and the thickness of the lower electrode material film after removal is 50 nm or more,
A method for manufacturing a semiconductor memory device. 2. The method according to claim 1, wherein the lower electrode material film is planarized by chemical mechanical polishing or dry etching.