JP2000341111A - Variable frequency divider - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable frequency divider whose jitter characteristic is improved. SOLUTION: This variable frequency divider is provided with a variable frequency divider 2, that alternately applies 1/N frequency division (N is an integer) and 1/(N+1) frequency division to an input signal, a 1st output means 6 that synchronously outputs a signal with the output of the variable frequency divider 2, a 2nd output means 9 that outputs a signal which delays a signal synchronously with the output of the variable frequency divider 2 by 1/2 frequency division with respect to the input signal, and a selection circuit 10 that selects the output of the 1st output means 6, when the variable frequency divider 2 conducts 1/N frequency division and selects the output of the 2nd output means 9 when the variable frequency divider 2 conducts 1/(N+1) frequency division.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a variable frequency dividing device.

[0002]

2. Description of the Related Art Conventionally, this type of apparatus is disclosed in, for example,
No. 261048. According to this publication, a variable frequency divider that alternately divides an input signal by N and divides by N + 1, a first output unit, a second output unit that delays an input signal by 分, and a selection circuit Is provided.
Then, when the variable frequency divider performs frequency division by N, the selection circuit
When the output of the second output means is selected and the variable frequency divider performs N + 1 frequency division, the output of the first output means is selected. As a result, a signal of N + ／ is output.

[0003]

The above-described apparatus has a drawback that jitter characteristics are poor. That is, N + 1/2 frequency division is not output accurately. The present inventor has investigated the cause and found that the reason is that an inverter is provided between the input signal and the second output means. That is, the inverter inverts the input signal and causes the second output means to delay the input signal by １ ／.

[0004] However, due to the device characteristics of the inverter, the output signal of the second output means is further delayed from the 遅 延 frequency division delay, and therefore, the frequency division of N + ／ is not performed accurately. Was. Therefore, the present invention provides a variable frequency divider with improved jitter characteristics (accurate frequency division to N + 1/2) in consideration of such conventional disadvantages.

[0005]

In order to solve the above-mentioned problems, according to the present invention, there is provided a variable frequency divider for alternately dividing an input signal by N (N is an integer) and N + 1. When,
First output means for outputting a signal synchronized with the output of the variable frequency divider; and a second output means for outputting a signal obtained by delaying the signal synchronized with the output of the variable frequency divider by 1/2 the frequency of the input signal. When the two output means and the variable frequency divider divide N, the output of the first output means is selected. When the variable frequency divider divides N + 1, the output of the second output means is selected. And a blocking means for preventing the output signal of the second output means from being further delayed from the 1/2 frequency division delay.

[0006] According to the second aspect of the present invention, the blocking means includes:
The first output means or the second output means has a built-in input inversion function.

According to the third aspect of the present invention, the blocking means includes:
A first output means provided between the first output means and the selection circuit;
An inverter and a second inverter provided between the input signal and the second output means.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a variable frequency dividing device 1 according to a first embodiment of the present invention will be described with reference to the block diagram of FIG. In FIG. 1, a signal D0 for specifying whether to perform 1/2 frequency division and a frequency dividing ratio N (N is an integer) are supplied to the variable frequency dividing device 1.
D1 to D4 designating a voltage control oscillator (described later)
Is input. D0 to D4 are Low
(0) or High (1) signal, and A1 is, for example,
This is a pulse signal in which the Low time and the High time are equal to each other.

The variable frequency divider 2 comprises, for example, four toggle flip-flops TFF1, TFF2, TFF3, TFF4
Are connected in series. Each of the toggle flip-flops TFF1 to TFF4 has a built-in input inversion function.

The variable frequency divider 2 uses the inverted signal of the input signal B1 as a clock pulse, counts down at the frequency division ratio N applied to the input terminals D1 to D4, and outputs a signal B9 (described later) applied to the terminal PE. Preset down count by Low.

The matching circuit 3 includes an inverter 4, an AND gate 5, and the like. Toggle flip-flops TFF1, TFF
Each output terminal Q of FF3 and TFF4 is connected to the input terminal of AND gate 5, respectively. The output terminal Q of the toggle flip-flop TFF2 is connected to A
It is connected to the input terminal of the ND gate 5. Thus, when the output of the variable frequency divider 2 becomes “2”, the coincidence circuit 3 outputs the detection signal B2 which becomes High.

The first output means 6 is, for example, a D-flip-flop having a built-in input inverting function.
A signal B3 obtained by delaying the output B2 of the matching circuit 3 by 1/2 the frequency of the input signal B1 using the inverted signal of
Is output from the terminal Q.

The flip-flop 7 is, for example, a D-flip-flop (DFF2) having a built-in input inversion function. The flip-flop 7 outputs from a terminal Q a signal B4 obtained by delaying B3 by 1 and dividing the signal B5 by inverting the signal B5 by using an inverted signal of the input signal B1 as a clock pulse.
Is output from the terminal inversion Q.

The flip-flop 8 is, for example, a D-flip-flop (DFF3). The flip-flop 8 feeds back its own inverted output B8 as an input signal with B5 as a clock pulse. When the signal B6 (output from the terminal D0) input to the inverted PRE is High, a signal B7 that repeats on and off is output from the terminal Q in synchronization with the rise of B5, and a signal obtained by inverting B7. B8 is output from the terminal Q. When the signal B6 is Low, B7 becomes High and B8 becomes Low.

The second output means 9 is, for example, a D flip-flop (DFF4). The second output means 9 outputs from a terminal Q a signal B10 obtained by delaying B3 by 分 and using the input signal B1 as a clock pulse. This is because the first output means 6 inputs a signal obtained by inverting B1 as a clock pulse, and the second output means 9 inputs B1 as a clock pulse. Therefore, the signal B10 outputs the signal B3 and the input signal B1. It is a signal that has been delayed by a factor of two.

The selection circuit 10 is, for example, a NAND gate 1
1, a NAND gate 12, a NAND gate 13, and the like. The NAND gate 11 outputs a signal B11 which is the NAND of B3 and B7. NAND gate 12 is B
A signal B12, which is the NAND of 10 and B8, is output.
The NAND gate 13 outputs a signal B13 which is the NAND of B11 and B12.

Since B7 and B8 are in an inverse relationship to each other, B13 is a signal that alternately outputs B11 and B12 in synchronization with B7 and B8. That is, the selection circuit 10 including the three NAND gates 11, 12, and 13 alternately outputs two signals B 3,
B10 is switched and output.

The NAND gate 14 outputs a signal that is the NAND of B8 and B4. NAND gate 15 is B7
And a signal that is the NAND of B3. The NAND gate 16 outputs a signal that is the NAND of the two signals to each PE terminal of the variable frequency divider 2. With the above parts,
The variable frequency dividing device 1 is configured.

Next, FIGS. 1 and 2 (showing the waveform of each signal)
, The operation of the variable frequency dividing device 1 will be described. For example, an operation of dividing the frequency by N + ／ = 5.5 with N = 5 will be described. For example, "1", "1", "0"
“1” and “0” are input. In this state, the input signal B1 having the local oscillation frequency is input to the variable frequency divider 2, and when "2" is detected by the coincidence circuit 3, a detection signal B2 which becomes "High" at "2" is output. (See FIG. 2).

The output B3 of the first output means 6 is 1 more than B2.
/ 2 delay. Outputs B4 and B5 of flip-flop 7
Is delayed by one division from B3. Output B of flip-flop 8
7 and B8 are repeatedly turned on and off in synchronization with the rise of B5 because B6 is High. As described above, the output B10 of the second output means 9 is delayed by 1/2 the frequency of B3 (see FIG. 2).

The output B11 of the NAND gate 11 is B3
AND of B7 and High of B3 on the divide-by-5 side
Is extracted. The output B12 of the NAND gate 12 is B1
This is the NAND of 0 and B8, and B10 on the divide-by-6 side is extracted. The output B13 of the NAND gate 13 is B11 and B
12 is a NAND, and combines the extraction units of B11 and B12. That is, as described above, B13 is a signal that alternately outputs B3 and B10 in synchronization with the flip-flop 8. Since B3 and B11 are shifted by 1/2 of B1, the frequency of B13 is 5.5.

The above is summarized. A variable frequency divider 2 for alternately dividing the input signal B1 by N (for example, N = 5) and N + 1 is provided, and the first output means 6 for outputting a signal synchronized with the output of the variable frequency divider is provided. Provide. Then, a signal synchronized with the output of the variable frequency divider 2 is １ ／ of the input signal B1.
A second output means 9 for outputting the signal B10 delayed in frequency division is provided.

When the variable frequency divider 2 performs frequency division by N (frequency division by 5), the selection circuit 10 selects the output B3 of the first output means 6. When the variable frequency divider 2 performs N + 1 frequency division (frequency division by 6),
The selection circuit 10 selects the output B10 of the second output means 9.

The blocking means 17 comprises the first output means 6, the second output means 9, and the like. As described above, the first output means 6 is, for example, a D-flip-flop having a built-in input inversion function, and the second output means 9 is, for example, a D-flip-flop having no input inversion function.
-A flip-flop.

With this configuration, the input signal B1 is inverted in the first output means 6, and the inverted signal is input to the first output means 6 as a clock pulse. The second output means 9 receives the input signal B1 as a clock pulse. Therefore, the blocking means 17 prevents the second output means 9 from further delaying the output of the first output means 6 from the 1/2 frequency division delay.

When the output B6 of the terminal D0 is 1 due to the blocking means 17, the variable frequency dividing device 1 converts the input signal B1 having the local oscillation frequency into a frequency dividing ratio N + 1/2 (for example, 5 + 5 shown in FIG. 2). .5 division), the frequency can be accurately divided. Also, when B6 is 0, the variable frequency dividing device 1 converts the input signal B1 into
Frequency division is performed at the frequency division ratio N.

The blocking means 17 may have the second output means 9 with an input inversion function instead of the first output means 6 with an input inversion function.

Next, the PLL circuit 18 using the variable frequency divider 1 will be described with reference to the block diagram of FIG. In FIG. 3, the reference signal B14 output from the reference oscillator 19 is
It is input to the phase comparator 20. The signal (feedback signal) B13 output from the variable frequency dividing device 1 is also input to the phase comparator 20.

The phase comparator 20 compares the phase and frequency of the feedback signal B13 with the phase and frequency of the reference signal B14. As a result of the comparison, the phase comparator 20 outputs a pump-up signal and a pump-down signal to the charge pump 21.

The charge pump 21 follows the above two signals,
The error signal is output to the low-pass filter 22. Low-pass filter 22 outputs a control voltage to voltage-controlled oscillator 23 in response to the error signal. The voltage controlled oscillator 23 outputs an output signal B1 in response to the control voltage.

Next, the characteristics of the output signal B1 in the PLL circuit 18 will be described with reference to FIG. In FIG.
The horizontal axis indicates the elapsed time, and the vertical axis indicates the voltage value of B1. FIG. 4 shows the case of frequency division by N (for example, frequency division by 5). A characteristic 24 indicates a steady state of the output signal B1. Line 25 indicates the lower threshold of output signal B1, for example 2.04 volts, line 26 indicates the upper threshold of output signal B1,
For example, 2.47 volts. The reference time 27 is a line 25
And 26, the time width of the output signal B1 which is between about 800 picoseconds.

Similarly, FIG. 5 is a characteristic diagram of the output signal B1 in the PLL circuit 18 in the case of N + 1/2 frequency division (for example, 5.5 frequency division). In FIG. 5, characteristic 28 indicates the steady state of output signal B1, and lines 29 and 30 indicate the lower and upper thresholds of output signal B1, respectively. Line 29
And 30 are, for example, 2.48 volts and 2.83 volts. The reference time 31 indicates a time width of the output signal B1 existing between the lines 29 and 30, and is about 800 picoseconds.

In the case of the frequency division by N (for example, frequency division by 5) shown in FIG. 4, when the variable frequency divider 2 performs frequency division by 5, the first frequency division is performed.
Only the output means 6 is selected. Therefore, the generation of jitter by selecting the second output means 9 (do not accurately divide by N)
There is no.

However, the reference time 27 by dividing by N,
The reference time 31 based on the N + 1/2 frequency division is the same. Therefore, when the variable frequency dividing device 1 is used, it can be seen that no jitter occurs even when the frequency is divided by N + ／ (the frequency is accurately divided by N + ／).

Next, a variable frequency dividing device 32 according to a second embodiment of the present invention will be described with reference to the block diagram of FIG. FIG.
The feature of the variable frequency dividing device 32 is that a blocking means 33 is provided. The blocking means 33 includes a first inverter 34 and a second inverter 7a.

The first inverter 34 is connected to the first output means 4a
And the NAND gate 12 of the selection circuit 15a.
a. The second inverter 7a has substantially the same device characteristics as the first inverter 34, for example, and is provided between the input signal A1 and the second output means 8a.

With such a configuration, A5 is a signal obtained by inverting the output A4 of the first output means 4a. The signal A5 is inverted again by the first inverter 34, and the signal A5 is delayed from the output A4 by the eigenvalue of the first inverter 34.
5a. The eigenvalue depends on the device characteristics of the first inverter 34 (caused by the resistance and the capacitance of the capacitor).

A second inverter 7a is provided between the input signal A1 and the second output means 8a. Therefore, the second
The output A11 of the output means 8a is a signal which is delayed from the output A4 of the first output means 4a by half of the frequency of the input signal A1 and the eigenvalue of the second inverter 7a.

The first inverter 34 and the second inverter 7a
Since the device characteristics are substantially the same, the eigenvalues of both are also substantially the same. Therefore, the phase difference between the signals A5a and A11 is obtained by subtracting the eigenvalue of the first inverter 34 from the sum of the 分 frequency division of the input signal A1 and the eigenvalue of the second inverter 7a. However, since the two eigenvalues are the same, the phase difference is exactly 1/2 the frequency of the input signal A1.

As described above, the blocking means 33 causes the output signal A11 of the second output means 8a to be further delayed from the output signal A4 of the first output means 4a by a 分 frequency division delay of the input signal A1. It can be almost completely prevented. as a result,
The variable frequency dividing device 32 can accurately divide the frequency by N + ／.

[0041]

As described above, according to the first aspect of the present invention, a variable frequency divider that alternately divides an input signal by N (N is an integer) and an N + 1 frequency is provided. First output means for outputting a signal synchronized with the output, second output means for outputting a signal obtained by delaying the signal synchronized with the output of the variable frequency divider by に 対 し with respect to the input signal, and variable frequency division A selection circuit for selecting the output of the first output means when the frequency divider performs frequency division by N, and selecting the output of the second output means when the variable frequency divider performs frequency division by N + 1;
Blocking means for preventing the output signal of the second output means from further delaying from the 1/2 frequency division delay.

With this configuration, the output signal of the second output means is exactly delayed from the output signal of the first output means by １ ／ of the input signal. As a result, exactly N
+1/2 frequency division is performed, and the jitter characteristic is improved.

According to the second aspect of the present invention, the blocking means includes:
The first output means or the second output means has a built-in input inversion function. As described above, since the input inversion function is built-in, the delay of the eigenvalue due to the device characteristics of the external inverter is eliminated unlike the related art. As a result, the output signal of the second output means is exactly delayed from the output signal of the first output means by half the frequency of the input signal.

According to the third aspect of the present invention, the blocking means includes:
It comprises a first inverter provided between the first output means and the selection circuit, and a second inverter provided between the input signal and the second output means. With this configuration, the phase difference between the output of the first output means and the output of the second output means is reduced to 1/2 the frequency of the input signal because the eigenvalue delay of the first inverter and the eigenvalue delay of the second inverter cancel each other. It is almost equal. As a result, N + 1/2 frequency division is performed accurately, and the jitter characteristics are improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a variable frequency dividing device 1 according to Embodiment 1 of the present invention.

FIG. 2 is a timing chart of signals used in the variable frequency divider 1.

FIG. 3 is a PLL circuit 1 using the variable frequency dividing device 1;
8 is a block diagram of FIG.

FIG. 4 is an output signal characteristic diagram (at the time of dividing by N) of a voltage controlled oscillator 23 used in the PLL circuit 18.

FIG. 5 is an output signal characteristic diagram (N
(+1/2 frequency division).

FIG. 6 shows a variable frequency dividing device 32 according to a second embodiment of the present invention.
It is a block diagram of.

[Explanation of symbols]

 2 Variable frequency divider 6 First output means 9 Second output means 10 Selection circuit 17 Blocking means

Claims (3)

[Claims] 1. A variable frequency divider for alternately dividing an input signal by N (N is an integer) and dividing by N + 1, and a first output means for outputting a signal synchronized with an output of the variable frequency divider And second output means for outputting a signal obtained by delaying a signal synchronized with the output of the variable frequency divider by 分 frequency with respect to the input signal,
A selection circuit for selecting the output of the first output means when the variable frequency divider performs frequency division by N, and selecting the output of the second output means when the variable frequency divider performs frequency division by N + 1; And a blocking means for preventing the output signal of the second output means from further delaying from the 1/2 frequency division delay. 2. The variable frequency dividing device according to claim 1, wherein said blocking means has a built-in input inversion function in said first output means or said second output means. 3. The method according to claim 2, wherein the blocking unit includes a first inverter provided between the first output unit and the selection circuit, and a second inverter provided between the input signal and the second output unit. The variable frequency dividing device according to claim 1, wherein the variable frequency dividing device is configured.