JP2000350097A - Solid-state imaging device - Google Patents

Abstract

(57) [Problem] To prevent deterioration of image quality caused by a difference in accumulation time of signal charges between rows or fields. SOLUTION: A plurality of photoelectric conversion units arranged two-dimensionally in a row direction and a column direction to generate electric charge according to the amount of incident light, and a plurality of photoelectric conversion units provided corresponding to a plurality of photoelectric conversion units arranged in a column direction. A plurality of vertical signal lines from which electric signals corresponding to the signal charges stored in the conversion unit are read, and a read operation of the electric signals corresponding to the signal charges to the vertical signal lines is performed by interlaced scanning. In the imaging device, each photoelectric conversion unit is initialized before the read operation, and a period from the initialization operation to the read operation is constant in each row.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a technique for improving the image quality of a CMOS solid-state imaging device.

[0002]

2. Description of the Related Art In recent years, as a solid-state imaging device, a CMOS type (sometimes called an amplification type or an APS type) solid-state imaging device (CMOS image sensor) has been developed as a low power consumption type solid-state imaging device for mobile devices. It has been commercialized. Further, this CMOS image sensor will be used in a PC camera capable of handling moving image information, a digital camera, a DV camera, an ATV camera, etc., which require high image quality, by utilizing the feature of low power consumption. And Currently used NTSC / PAL cameras and DV cameras perform an interlacing operation in which addition is performed inside the sensor. In interlaced operation, the first
In the field, a read operation is started from an odd row, and in the second field, a read operation is started from an even row. FIG. 10 shows an interlacing operation of a conventional CMOS image sensor. In the figure, FI is a field index, V
D indicates a vertical synchronization signal, HD indicates a horizontal synchronization signal, and BLK indicates a vertical blanking period. A conventional CMOS image sensor, as shown in FIG.
(2nd line + 3rd line), (4th line + 5th line), (6th line +
In the seventh row), an electric signal corresponding to the signal charge stored in the photodiode is read. In the odd-numbered fields, (first line + second line),
An electric signal corresponding to the signal charge stored in the photodiode is read out as (3rd line + 4th line), (5th line + 6th line), and so on.

Accordingly, as shown in FIG. 1, the accumulation period of the second row of the odd field is 262.5H + α (H is 1
The horizontal period, α is a value that depends on the read timing in the horizontal blanking period.) The accumulation period of the third row is 263.5.
H-α (262.5H + 1H-α). The accumulation period of the second row of the even field is 262.5H-α, and the accumulation period of the third row is 261.5H + α (262.5H−α).
H-1H + α). That is, even in the same field, the accumulation period differs between the even-numbered row and the odd-numbered row.
Further, even in the same row, the accumulation period differs between the even field and the odd field. Such a problem does not occur in a sensor having synchronization such as a CCD image sensor. However, in a line readout sensor having no synchronization such as a CMOS image sensor, such a problem occurs when interlaced scanning is performed. The problem of non-uniformity of the accumulation time occurs. When the accumulation period is long, such non-uniformity of the accumulation period does not greatly affect the image quality. However, when the accumulation period is short (for example, the accumulation period due to the electronic shutter operation when capturing a bright image). (For example, when the length of the image data becomes short), the non-uniformity of the accumulation period greatly affects the image quality.

On the other hand, when a CMOS image sensor is used under a fluorescent lamp, a fluorescent lamp flicker having a cycle different from the cycle of the vertical period may adversely affect image quality. The problem of flicker is that when performing interlaced scanning,
This also occurs when performing progressive scanning for sequentially reading out signals for one frame.

[0005]

As described above, the conventional C
In the MOS type solid-state imaging device, when performing the interlacing operation, the accumulation time of the photoelectrically converted signal charges is different between the even-numbered rows and the odd-numbered rows or between the even-numbered fields and the odd-numbered fields. Had the problem of adversely affecting In addition, the conventional CMOS solid-state imaging device has a problem that image quality is adversely affected by flicker having a cycle different from the cycle of the vertical period (the cycle of one frame or one field). SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and has a problem of deterioration of image quality caused by a difference in signal charge accumulation time between rows or fields, or a flicker having a cycle different from the cycle of the vertical period. It is an object of the present invention to provide a solid-state imaging device capable of solving the problem of image quality degradation that occurs.

[0006]

According to the present invention, there is provided an image section in which a plurality of photoelectric conversion sections for generating charges corresponding to the amount of incident light are two-dimensionally arranged in a row direction and a column direction, and a plurality of the image sections. A row selection circuit for selecting a pixel row of the image section, and an electric signal corresponding to each signal charge generated in the plurality of photoelectric conversion sections in the selected pixel row, provided corresponding to the plurality of pixel columns of the image section. Outputting a control signal to the plurality of vertical signal lines to be read and the row selection circuit to read out the electric signal to the vertical signal line based on interlaced scanning; The row selection circuit can select three or more pixel rows at the same time, and reads out from the initialization operation of each photoelectric conversion unit. Wherein the period until the work is to select a plurality of pixel rows to be constant in each pixel row.
According to the present invention, each photoelectric conversion unit is initialized before the read operation is performed by the row selection circuit, so that the period from the initialization operation to the read operation is constant in each row. Therefore, the accumulation period of the signal charge in each photoelectric conversion unit can be made equal between different fields (even and odd fields) and between different rows (even and odd rows), and due to the non-uniformity of the accumulation period. It is possible to prevent deterioration of image quality. Furthermore, the row selection circuit
Since three or more pixel rows can be selected at the same time, the accumulation period of signal charges in the same field can be made constant for each row and the accumulation period can be made different for each field (even field and odd field) as desired. it can.

Further, the present invention provides an image section in which a plurality of photoelectric conversion sections for generating electric charges corresponding to the amount of incident light are two-dimensionally arranged in a row direction and a column direction, and a plurality of pixel rows of the image section. A row selection circuit to be selected, and a plurality of electric signals corresponding to respective signal charges generated in the plurality of photoelectric conversion units in the selected pixel row, which are provided corresponding to the plurality of pixel columns of the image unit. A vertical signal line, and a control circuit that outputs a control signal to the row selection circuit, causes the electric signal to be read to the vertical signal line, and initializes each photoelectric conversion unit before the read operation. In the solid-state imaging device, the row selection circuit includes:
It is possible to select three or more pixel rows at the same time, and to select a plurality of pixel rows so that the period from the initialization operation to the read operation of each photoelectric conversion unit corresponds to the period of flicker of ambient light. It is characterized by. According to the present invention, each photoelectric conversion unit is initialized before the read operation is performed by the row selection circuit, so that a period from the initialization operation to the read operation corresponds to a period of flicker of ambient light. . Therefore, the influence of flicker can be equalized between the accumulation periods, and deterioration in image quality due to flicker having a cycle different from the cycle of the vertical period (the cycle of one frame or one field) can be prevented. Further, since the row selection circuit can simultaneously select three or more pixel rows, the signal charge accumulation period in the same field or the same frame is fixed for each row, and the accumulation period for each field or frame is set as desired. Can be different.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an overall configuration of a CMOS solid-state imaging device (CMOS image sensor) according to the present invention. The CMOS type solid-state imaging device shown in FIG. 1 mainly includes an image unit 11, a system generator 12, vertical registers 13a to 13c, a pulse selector 14, a timing generator 15, a line memory 16, a horizontal register 17, and an output unit 18. These components are formed on the same semiconductor substrate (such as a silicon substrate). The image unit 11 includes a large number of unit cells and the like arranged two-dimensionally in a row direction and a column direction. FIG. 2 shows a configuration of a unit cell. Each unit cell includes a photodiode 21 serving as a photoelectric conversion unit, a readout transistor 22, an amplification transistor 23, an address transistor 24, a reset transistor 25, a detection unit 26, and the like. It is configured.
A common vertical signal line 27 is connected to each amplifying transistor 23 in each unit cell arranged in the column direction, and the vertical signal line 27 is connected to an electric current corresponding to signal charges stored in the photodiode 21. The signal is read. The read transistor 22, the address transistor 24, and the reset transistor 25 in each unit cell arranged in the row direction have a common read control line 28, address control line 29, and reset control line 30.
Is connected. Further, a common power supply line 31 is connected to each address transistor 24 and each reset transistor 25 in each unit cell arranged in the column direction.

The system generator 12 includes a vertical synchronizing signal, a horizontal synchronizing signal, a selection signal for interlaced scanning / progressive scanning, a field index signal (FI signal) for switching between even and odd fields,
Various control signals such as an address signal at the time of random access and an electronic shutter control signal are externally supplied. The system generator 12 generates an internal control signal for controlling the operation of the CMOS image sensor in cooperation with the timing generator 15 based on these external control signals, and outputs the internal control signal to the vertical registers 13a to 13c, the horizontal register 17, and the like. I do. The vertical register (vertical register for signal reading) 13a is for selecting each unit cell provided in the row direction of the image unit 11 at a predetermined timing, and is provided with a photodiode in each selected unit cell. An electric signal corresponding to the stored signal charge is read out to the vertical signal line. The vertical registers (vertical registers for initialization) 13b and 13c also select each unit cell provided in the row direction of the image unit 11 at a predetermined timing, and accumulate in the photodiode in each selected unit cell. Unnecessary charges are discharged, and the photodiode is brought into an initial state. The reason why two vertical registers for setting the photodiodes to the initial state are provided is that the setting timing of the initial state differs depending on the even field and the odd field of the interlaced scanning.

The signals output from the vertical registers 13a, 13b and 13c make it possible to keep the signal charge accumulation period of each photodiode constant between different fields and different rows. The pulse selector 14 includes vertical registers 13a, 13b and 13c.
Supplies a selection signal to the row specified by. Specifically, upon receiving a timing signal from the timing generator 15, the read control line 28, the address control line 29 and the reset control line 30 of the selected row are selected.
, A control signal is supplied at a predetermined timing.
In the example shown in the figure, the vertical registers 13a to 13c and the pulse selector 14 are arranged on the left and right, but they may be arranged on one side. Furthermore, the three vertical registers 13a to 13c are not indispensable in this embodiment as long as the unit cells for three rows can be simultaneously selected by the multiplex output row selection circuit. For example, by adopting a logic circuit configuration in which shift operations of three or more rows can be performed in parallel only by the vertical register 13a and the pulse selector 14, it is possible to significantly reduce the circuit area. The line memory 16 stores an electric signal read through a vertical signal line, and includes a noise canceller circuit or the like. The signal read to the line memory 16 is sequentially output to the outside from an output unit 18 by a horizontal register 17. It has become.

Next, a first operation example of the present embodiment will be described. First, an operation principle will be described with reference to FIG.
FIG. 3 shows an image area corresponding to the image unit 11 shown in FIG. The image area has N × M pixels in N rows in the vertical direction and M columns in the horizontal direction. An effective pixel area for sensing light and OB (optical black) pixels provided outside the effective pixel area and outputting a black signal are provided. It is composed of regions. Specifically, the first 12
The row and the last two rows are OB pixel areas, and the remaining 494 rows are effective pixel areas. In the horizontal direction, the first fixed column and the last fixed column are OB pixel regions, and the remaining columns are effective pixel regions. In this example, when reading the signal on the x-th row in a certain horizontal blanking period, (x−k) in the odd field in the same period.
The row is initialized, and (x−k−
1) Initialize the row. As described above, by performing the read operation and the initialization operation for each horizontal blanking period, the storage time of the photodiode provided in each row can be made equal between the even field and the odd field. As described in the section of the related art, especially when the accumulation period is short (for example, when the accumulation period is shortened by an electronic shutter operation when capturing a bright image), the image quality is deteriorated due to the unevenness of the accumulation period. However, by using this method to keep the accumulation period constant,
Image quality can be improved.

On the other hand, in the present embodiment, the two vertical registers 13b and 13c for initialization are controlled so as to be switched on a field-by-field basis, so that signal accumulation is automatically performed in accordance with the output level of the light receiving sensor. For example, when it is desired to change the period, the signal accumulation period in each field can be made variable while the signal accumulation period in the same field is fixed in each row. The reason will be described below. FIG. 4 shows a CMOS solid-state imaging device having a single initialization vertical register. First, the relative timing relationship between the signal readout and initialization vertical registers is fixed, and the accumulation period in each field is fixed. It shows the operation timing in the case of. In FIG. 4, a read control pulse is a signal for starting a row selection operation of a vertical register for signal reading, and an initialization control pulse is a signal for starting a row selection operation of a vertical register for initialization. As shown in FIG. 4, the timing (timing t1, t2) at which the vertical register for initialization performs row selection prior to the vertical register for signal reading is fixed. In other words, the time difference between the initialization and the signal read-out vertical register selecting a row is always constant (t2−t1). As described above, when the row selection timings of the signal reading and initialization vertical registers are relatively fixed, both the signal reading vertical register and the initialization vertical register are effective in a certain field. The row selection operation from the first stage to the last stage of the (or effective) pixel region is performed, and then the process returns to the first stage and the row selection operation of the next field can be started.

Next, in the CMOS type solid-state imaging device having a single vertical register for initialization, the timing at which the vertical register for initialization performs row selection before the vertical register for signal reading is changed. FIG. 5 shows the operation timing when the accumulation period in each field is variable. In FIG. 5, in the first field, the row selection operation of the vertical register for initialization is started by the initialization control pulse generated at the same timing t1 as in FIG. Thereafter, the first operation is performed for the initialization operation corresponding to the second field.
It is assumed that an initialization control pulse is generated at the timing t3 in FIG. 5 before the row selection operation of the vertical register for initialization in the field (1) has not reached the final stage. At this time, in the vertical register for initialization, the row selection operation from the first stage started at the timing t1 corresponding to the first field is interrupted at the timing t3, and thereafter, the row selection for the second field is performed. The operation returns to the first stage and is performed. Accordingly, based on the read control pulse generated at the timing t2 in FIG. 5, when the row selection operation of the vertical register for signal reading is started to perform the signal reading of the first field, the row started at the timing t1 is read. A difference in the accumulation period occurs between the pixel row selected and designated by the selection operation and the pixel row not selected and designated. When the difference in the accumulation period occurs, the readout output level fluctuates depending on the position of the pixel row, and causes image noise such as horizontal stripes when the output signal of the solid-state imaging device is displayed on the display device. Becomes

On the other hand, in the CMOS type solid-state imaging device of this embodiment having two initialization vertical registers, FIG.
FIG. 6 shows the operation timing when the accumulation period in each field is variable as in the case of FIG. In this case, the accumulation period in each field is variable by changing the timing at which the vertical registers for initialization 13b and 13c perform row selection before the vertical registers for reading signals. Further, as can be seen from FIG. 6, in the solid-state imaging device according to the present embodiment, two initialization vertical registers 13 are provided.
b and 13c are alternately operated in field units. That is, the row selection operation for initialization is performed by two vertical registers 13b and 13c for each field.
It is distributed alternately. Therefore, even if an initialization control pulse for the initialization operation corresponding to the second field is generated before the row selection operation of the initialization vertical register 13b in the first field has reached the final stage. Here, the row selection operation of the initialization vertical register 13b is started without interruption in the middle of the row selection operation of the initialization vertical register 13b. In this way, it is possible to control such that the accumulation period in the same field is always kept constant while the accumulation period in each field is variable.

Next, a first operation example will be described with reference to a timing chart shown in FIG. In the figure, FI indicates a field index, VD indicates a vertical synchronization signal, HD indicates a horizontal synchronization signal, BLK indicates a vertical blanking period, and IS indicates an initialization start signal. By the interlaced scanning, in the even field, the signal charges accumulated in the photodiode are changed to (2nd line + 3rd line), (4th line + 5th line), (6th line + 7th line). The corresponding electrical signal is read. In the odd-numbered fields, (1st line + 2nd line), (3rd line + 4th line), (5th line + 6th line), an electric field corresponding to the signal charge accumulated in the photodiode is set. The signal is read. System generator 1 shown in FIG.
2, a vertical synchronizing signal VD, a horizontal synchronizing signal HD, a field index signal FI, and the like are externally supplied, and the field index signal FI is in a high state (corresponding to an even field) or a low state (corresponding to an odd field). ), The vertical registers 13b and 1
The initialization start signal IS supplied to 3c is changed by one horizontal period for each field. That is, the generation timing of the initialization start signal IS for the vertical synchronization signal VD is changed between the even field and the odd field. Thus, the accumulation period of each row is 261 horizontal periods (261H) in both the even field and the odd field.
Becomes

Hereinafter, the specific operation will be described in more detail. In the even field, the read operation starts from (second row + third row). In the odd field 261 horizontal periods earlier, the initialization start signal IS for the second and third rows is generated. Initialization of each photodiode provided in the third and third rows is performed. Similarly, for (4th line + 5th line) and thereafter, the initialization start signal IS is generated 261 horizontal periods before the read operation, and the photodiode is initialized in the same manner ((4th line + 5). For the subsequent lines), the initialization start signal IS is not shown). In the odd field, the read operation starts from (1st row + 2nd row). In the even field 261 horizontal periods before that, the initialization start signal IS for the 1st row and the 2nd row is generated. Initialization of each photodiode provided in the second row and the second row is performed. Similarly,
(3rd line + 4th line) and thereafter, read operation 2
The initialization start signal IS is generated 61 horizontal periods ago, and the initialization of the photodiode is performed in the same manner ((3rd + 4th rows) and thereafter, the initialization start signal IS
Are not shown).

In the case of performing a read operation of (2nd row + 3rd row) in the even field, for example, the second row is read in the first half of the horizontal blanking period based on a signal from the vertical register 13a shown in FIG. Read operation is performed,
The reading operation of the third row is performed in the latter half of the horizontal blanking period. First, in the first half of the horizontal blanking period, the address transistor 24 provided in each unit cell (see FIG. 2) in the second row is turned on. further,
By turning on the reset transistor 25, the potential of the detection unit 26 is reset to a predetermined potential. Subsequently, when the read transistor 22 is turned on,
The voltage of the detection unit 26 changes in accordance with the electric charge stored in the parasitic capacitance of the photodiode 21, and the signal voltage of the detection unit 26 changes via the amplification transistor 23 to the vertical signal line 27.
Is read out. In the latter half of the horizontal blanking period, the same operation is performed for each unit cell in the third row. As described above, the signals for two rows read to the vertical signal line 27 in the first half and the second half of the horizontal blanking period are added in the line memory 16, and the added signals are output to the outside via the output unit 18. Is output.

The initialization of (2nd line + 3rd line) is performed in a horizontal blanking period 261 horizontal periods before the read operation of (2nd line + 3rd line). At the time of initialization, an initialization start signal IS is supplied from the system generator 12 shown in FIG. 1 to the vertical register 13b. Based on this initialization start signal IS, the read transistor 22 provided in each unit cell (see FIG. 2) in the second row in the first half of the horizontal blanking period is turned on, and the third row in the second half of the horizontal blanking period. The read transistor 22 provided in each unit cell is turned on. As a result, unnecessary charges accumulated in the photodiodes 21 in the second and third rows are discharged in the first half and the second half of the horizontal blanking period, respectively, and each photodiode 21 is initialized. As described above, since the read operation and the initialization operation are performed in each horizontal blanking period, there are rows where the read operation is performed and rows where the initialization operation is performed in the same horizontal blanking period. Note that, for example, the read operation of (first row + second row) and the initialization operation of (first row + second row) in the odd-numbered fields are basically the same as the above-described operations. At this time, the initialization start signal IS is supplied from the system generator 12 to the vertical register 13c.

Next, a second operation example of the present embodiment will be described with reference to a timing chart shown in FIG. In the present operation example, when interlaced scanning is performed, the accumulation period of each row is fixed, and the deterioration of image quality due to fluorescent lamp flicker is reduced. In order to suppress the influence of the fluorescent lamp flicker, the accumulation period is set to correspond to the flicker cycle. Note that the overall configuration and basic operation are the same as in the first operation example described above. In the first operation example described above, the generation timing of the initialization start signal IS is set so that each accumulation period is 261 horizontal periods. In this example, each accumulation period is 158 horizontal periods (1
58H), the generation timing of the initialization start signal IS is set, thereby suppressing the influence of the fluorescent lamp flicker of 100 Hz. (60/100) is (15
8 / 262.5), and by setting the accumulation period to 158 horizontal periods, it is possible to reduce the flicker of 100 Hz fluorescent light. Note that, also in this case, the timings at which the row selection operation is started for the two initialization vertical registers may be changed from one another, and the accumulation period in each field may be made variable. In this case, 100
In order to suppress the influence of the fluorescent lamp flicker of Hz, the accumulation period of each field may be changed while satisfying, for example, a relationship of an integral multiple of 158 horizontal periods. Further, the frequency of flicker may be other than 100 Hz, and the accumulation period, that is, the generation timing of the initialization start signal IS is appropriately changed according to the frequency of flicker.

Next, a third operation example of the present embodiment will be described with reference to a timing chart shown in FIG. In the present operation example, when performing the progressive scanning, the accumulation period of each row is made constant, and the deterioration of the image quality due to the fluorescent lamp flicker is reduced. In order to suppress the influence of the fluorescent lamp flicker, the accumulation period is set to correspond to the flicker cycle. Note that the overall configuration and basic operation are the same as in the first operation example described above. Since this operation example is progressive scanning, as shown in the figure, one frame has 525 horizontal periods, and image signals for one row are read out in each horizontal period. The generation timing of the initialization start signal IS is set such that the 315 horizontal period of the 525 horizontal periods for one frame is the accumulation period, thereby suppressing the influence of the fluorescent lamp flicker of 100 Hz. That is, (315
/ 525) is almost equal to (60/100), and by setting the accumulation period to 315 horizontal periods, it is possible to reduce the flicker of the 100 Hz fluorescent lamp. Again, 2
The timing at which the row selection operation is started for the initialization vertical register of the book may be changed from one another, and the accumulation period in each frame may be made variable. In this case, in order to suppress the influence of the 100 Hz fluorescent lamp flicker, the accumulation period of each frame may be changed while satisfying, for example, a relationship of an integral multiple of 315 horizontal periods. Further, the frequency of flicker may be other than 100 Hz, and the accumulation period, that is, the generation timing of the initialization start signal IS is appropriately changed according to the frequency of flicker.

As a method of performing interlaced scanning, NT
The SC / PAL system and the DV system include progressive scanning, and the ATV system is a system for performing progressive scanning. The present invention can be applied to each of these systems. that's all,
Although the embodiment of the present invention has been described, the present invention is not limited to the above-described embodiment, and can be variously modified and implemented without departing from the gist thereof.

[0022]

According to the present invention, by initializing each photoelectric conversion unit before the read operation, it is possible to prevent the deterioration of the image quality due to the unevenness of the accumulation period or the deterioration of the image quality due to the flicker. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of the overall configuration of a CMOS solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is an electric circuit diagram showing an example of a configuration of a unit cell which is a main component of the image section shown in FIG.

FIG. 3 is an explanatory diagram showing a configuration example of an image area corresponding to the image section shown in FIG. 1;

FIG. 4 shows a CMOS having one vertical register for initialization.
FIG. 5 is an operation timing chart in the case where the accumulation period in each field is fixed in the solid-state imaging device.

FIG. 5 shows a CMOS having one vertical register for initialization.
FIG. 4 is an operation timing chart in a case where the accumulation period in each field is variable in the solid-state imaging device.

FIG. 6 shows a CMOS having two vertical registers for initialization.
FIG. 4 is an operation timing chart in a case where the accumulation period in each field is variable in the solid-state imaging device.

FIG. 7 is a timing chart showing a first operation example of the CMOS solid-state imaging device according to the present invention.

FIG. 8 is a timing chart showing a second operation example of the CMOS solid-state imaging device according to the present invention.

FIG. 9 is a timing chart showing a third operation example of the CMOS solid-state imaging device according to the present invention.

FIG. 10 is a timing chart showing an operation example of a CMOS solid-state imaging device according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Image part 12 ... System generator 13a, 13b, 13c ... Vertical register 14 ... Pulse selector 15 ... Timing generator 16 ... Line memory 17 ... Horizontal register 18 ... Output part 21 ... Photodiode 22 ... Readout transistor 23 ... Amplification transistor 24 ... Address transistor 25 ... Reset transistor 26 ... Detector 27 ... Vertical signal line 28 ... Read control line 29 ... Address control line 30 ... Reset control line 31 ... Power supply line

Claims (3)

[Claims] 1. An image section in which a plurality of photoelectric conversion sections that generate electric charges according to the amount of incident light are two-dimensionally arranged in a row direction and a column direction, and a row selection section that selects a plurality of pixel rows of the image section. A plurality of vertical signal lines provided corresponding to a plurality of pixel columns of the image section, and read out of electrical signals corresponding to respective signal charges generated in a plurality of photoelectric conversion sections in a selected pixel row. A control circuit that outputs a control signal to the row selection circuit, reads the electric signal to the vertical signal line based on interlaced scanning, and initializes each photoelectric conversion unit before the read operation. The row selection circuit can select three or more pixel rows at the same time, and the period from the initializing operation of each photoelectric conversion unit to the reading operation is constant in each pixel row. In duplicate A solid-state imaging device, wherein a number of pixel rows are selected. 2. An image section in which a plurality of photoelectric conversion sections that generate electric charges according to the amount of incident light are two-dimensionally arranged in a row direction and a column direction, and a row selection section that selects a plurality of pixel rows of the image section. A plurality of vertical signal lines provided corresponding to a plurality of pixel columns of the image section, and read out of electrical signals corresponding to respective signal charges generated in a plurality of photoelectric conversion sections in a selected pixel row. A control circuit that outputs a control signal to the row selection circuit, causes the electric signal to be read out to the vertical signal line, and initializes each photoelectric conversion unit before the readout operation. The row selection circuit is capable of simultaneously selecting three or more pixel rows, and a plurality of pixel rows such that a period from an initialization operation to a read operation of each photoelectric conversion unit corresponds to a flicker cycle of ambient light. Pixel rows A solid-state imaging device characterized by selecting. 3. The method according to claim 1, wherein the row selection circuit includes first and second initialization circuits.
And a third vertical register for signal readout, wherein the control circuit operates by switching the first and second vertical registers for each frame or each field. 3. The solid-state imaging device according to 1 or 2.