JP2000350103A - Photoelectric conversion device - Google Patents
Photoelectric conversion deviceInfo
- Publication number
- JP2000350103A JP2000350103A JP11155340A JP15534099A JP2000350103A JP 2000350103 A JP2000350103 A JP 2000350103A JP 11155340 A JP11155340 A JP 11155340A JP 15534099 A JP15534099 A JP 15534099A JP 2000350103 A JP2000350103 A JP 2000350103A
- Authority
- JP
- Japan
- Prior art keywords
- pixel
- photoelectric conversion
- signal
- pixel group
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
- H10F39/12—Image sensors
- H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10F39/186—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors having arrangements for blooming suppression
- H10F39/1865—Overflow drain structures
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
- H04N25/44—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by partially reading an SSIS array
- H04N25/441—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by partially reading an SSIS array by reading contiguous pixels from selected rows or columns of the array, e.g. interlaced scanning
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
- H04N25/44—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by partially reading an SSIS array
- H04N25/445—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by partially reading an SSIS array by skipping some contiguous pixels within the read portion of the array
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
- H04N25/621—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming
- H04N25/623—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming by evacuation via the output or reset lines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
- H10F39/12—Image sensors
- H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10F39/182—Colour image sensors
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
(57)【要約】
【課題】 静止画撮像の場合には全画素を読み出すこと
で全画素をリセットし、光電荷のあふれを防止できる
が、動画を撮影する場合の間引き読み出しの場合の間引
きされた画素による光電荷のあふれの影響を防止するこ
とを課題とする。
【解決手段】 複数の光電変換素子と前記光電変換素子
をリセットするリセットスイッチとからなる画素をマト
リクス状に配列し、各画素の信号を読み出すための垂直
走査手段および水平走査手段を有する光電変換装置にお
いて、前記画素の信号を読み出す第一の画素群と前記画
素の信号を読み出さない第二の画素群とを有し、前記第
一の画素群の信号電荷の蓄積期間中の少なくとも一部の
期間で、前記第二の画素群に含まれる光電変換素子を前
記リセットスイッチによりリセットすることを特徴とす
る。
(57) [Summary] [PROBLEMS] In the case of still image capturing, all pixels are reset by reading out all pixels, and overflow of photoelectric charges can be prevented. It is an object of the present invention to prevent the influence of photoelectric charge overflow due to a pixel. A photoelectric conversion device includes a plurality of photoelectric conversion elements and a reset switch for resetting the photoelectric conversion elements, the pixels being arranged in a matrix, and a vertical scanning unit and a horizontal scanning unit for reading a signal of each pixel. Has a first pixel group that reads out the signal of the pixel and a second pixel group that does not read out the signal of the pixel, and at least a part of the signal charge accumulation period of the first pixel group The photoelectric conversion element included in the second pixel group is reset by the reset switch.
Description
【0001】[0001]
【発明の属する技術分野】本発明は、行列上に配列され
た光電変換装置に関するものであり、デジタルスチルカ
メラやビデオカムコーダーなどの撮像機器に応用される
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device arranged in a matrix, and is applied to an imaging device such as a digital still camera or a video camcorder.
【0002】[0002]
【従来の技術】図7は従来の光電変換回路をあらわす模
式説明図である。同図において、光電変換素子(フォト
ダイオードなど)1は入射光量に応じた電荷を蓄積する
ものであり、2次元状に4個×4個の例にて配置されて
いる。光電変換素子1の一端は増幅型ソースフォロワ入
力MOS(Metal Oxide Silicon Transistor)2のゲー
トに接続し、ソースフォロワ入力MOS2のドレインは
垂直選択スイッチMOS3のソースに接続し、またソー
スフォロワ入力MOS2のソースは垂直出力線6を経て
負荷電流源7へと接続し、垂直選択スイッチMOS3の
ドレインは電源線4を経て電源端子5に接続されてお
り、これらは全体でソースフォロワ回路を構成してい
る。14はリセットスイッチであり、そのソースはソー
スフォロワ入力MOS2のゲートに接続し、ドレインは
電源線4を経て電源端子5に接続されている。2. Description of the Related Art FIG. 7 is a schematic explanatory view showing a conventional photoelectric conversion circuit. In FIG. 1, photoelectric conversion elements (photodiodes and the like) 1 accumulate electric charges according to the amount of incident light, and are arranged two-dimensionally in an example of 4 × 4. One end of the photoelectric conversion element 1 is connected to the gate of an amplification type source follower input MOS (Metal Oxide Silicon Transistor) 2, the drain of the source follower input MOS 2 is connected to the source of a vertical selection switch MOS3, and the source of the source follower input MOS 2 Is connected to a load current source 7 via a vertical output line 6, and the drain of the vertical selection switch MOS3 is connected to a power supply terminal 5 via a power supply line 4, and these constitute a source follower circuit as a whole. A reset switch 14 has a source connected to the gate of the source follower input MOS 2 and a drain connected to the power supply terminal 5 via the power supply line 4.
【0003】本回路は各画素の光電変換素子1に蓄積さ
れた電荷に応じてソースフォロワ入力MOS2のゲート
に信号電圧が発生し、それをソースフォロワ回路で電流
増幅して読み出すものである。In this circuit, a signal voltage is generated at the gate of a source follower input MOS 2 according to the electric charge stored in the photoelectric conversion element 1 of each pixel, and the signal voltage is amplified by a source follower circuit and read out.
【0004】垂直選択スイッチMOS3のゲートは垂直
ゲート線8で垂直走査回路9に接続する。リセットスイ
ッチ14のゲートはリセットゲート線15で垂直走査回
路9に接続する。また、ソースフォロワ回路の出力信号
は、垂直出力線6、水平転送MOSスイッチ10、水平
出力線11、出力アンプ12を通して外部に出力され
る。水平転送MOSスイッチ10のゲートは水平走査回
路13にそれぞれ接続している。The gate of the vertical selection switch MOS 3 is connected to a vertical scanning circuit 9 by a vertical gate line 8. The gate of the reset switch 14 is connected to the vertical scanning circuit 9 by a reset gate line 15. The output signal of the source follower circuit is output to the outside through the vertical output line 6, the horizontal transfer MOS switch 10, the horizontal output line 11, and the output amplifier 12. The gates of the horizontal transfer MOS switches 10 are connected to the horizontal scanning circuit 13, respectively.
【0005】本回路の動作を図8のタイミング図を用い
て説明する。ここで各画素行の垂直ゲート線に印加され
るパルスをそれぞれSEL1〜SEL4、リセットゲー
ト線15に印加されるパルスをRES1〜RES4とす
る。パルスSEL1〜SEL4、RES1〜RES4は
垂直走査回路9で発生されるものである。また、H1〜
H4は水平走査回路13で発生された水平走査パルスで
あり水平転送MOSスイッチ10のゲートに印加され
る。PD1、PD2はそれぞれ第一行第一列目、第二行
第一列目の光電変換素子(フォトダイオード)の電位の
変化を示したものである。The operation of this circuit will be described with reference to the timing chart of FIG. Here, the pulses applied to the vertical gate lines of each pixel row are SEL1 to SEL4, and the pulses applied to the reset gate line 15 are RES1 to RES4. The pulses SEL1 to SEL4 and RES1 to RES4 are generated by the vertical scanning circuit 9. Also, H1
H4 is a horizontal scanning pulse generated by the horizontal scanning circuit 13, and is applied to the gate of the horizontal transfer MOS switch 10. PD1 and PD2 indicate changes in the potentials of the photoelectric conversion elements (photodiodes) in the first row and first column and the second row and first column, respectively.
【0006】まず時刻t0にパルスRES1をハイレベ
ルにしてリセットスイッチ14を導通状態にすることに
より光電変換素子PD1をリセットする。次に蓄積動作
に入る。ソースフォロワ入力MOS2のゲートには蓄積
された信号電荷の量に応じて信号電圧が発生する。蓄積
時間終了後、時刻t2に、垂直走査回路9および水平走
査回路13によって生成されたパルスSEL1およびH
1がそれぞれ対応するスイッチ3および10に印加さ
れ、選択された光電変換素子PD1の信号はソースフォ
ロワ回路によって増幅された後、出力アンプ12を通し
て出力される。First, at time t0, the pulse RES1 is set to a high level to turn on the reset switch 14, thereby resetting the photoelectric conversion element PD1. Next, the storage operation is started. A signal voltage is generated at the gate of the source follower input MOS 2 in accordance with the amount of accumulated signal charge. After the end of the accumulation time, at time t2, the pulses SEL1 and H generated by the vertical scanning circuit 9 and the horizontal scanning circuit 13 are output.
1 are applied to the corresponding switches 3 and 10, respectively, and the signal of the selected photoelectric conversion element PD1 is amplified by the source follower circuit and then output through the output amplifier 12.
【0007】以下、順次H2〜H4パルスを印加するこ
とで第一行目に配列された光電変換素子からの信号が出
力される。同様に第二行目に配列された光電変換素子か
らの信号は、パルスRES1、SEL1、H1〜H4に
よって制御され出力される。たとえばPD2は、時刻t
1にリセットされ次に蓄積動作に入る。蓄積時間終了
後、時刻t3に光電変換素子PD2からの信号が出力さ
れるものである。Hereinafter, signals are output from the photoelectric conversion elements arranged in the first row by sequentially applying the H2 to H4 pulses. Similarly, the signals from the photoelectric conversion elements arranged in the second row are controlled and output by the pulses RES1, SEL1, and H1 to H4. For example, PD2 is at time t
It is reset to 1 and then enters the accumulation operation. After the end of the accumulation time, a signal from the photoelectric conversion element PD2 is output at time t3.
【0008】また、別の動作を図9の動作タイミング図
を用いて説明する。本タイミングは全画素分の信号を読
み出すのではなく、一部を間引いて読み出すものであ
る。同図において、垂直走査回路9からパルスSEL
2、SEL4、RES2、RES4に対応する信号を発
生させずに、SEL1、RES1に続いてSEL3、R
ES3パルスを発生することで、第2行目、第4行目の
信号を読み飛ばして第1行目、第3行目の信号を読み出
すものである。Another operation will be described with reference to an operation timing chart of FIG. In this timing, a signal for all pixels is not read out, but a part of the signal is read out. Referring to FIG.
2, SEL4, RES2, RES4, and SEL3, R
By generating the ES3 pulse, the signals in the second and fourth rows are skipped, and the signals in the first and third rows are read.
【0009】たとえば高精細な静止画を撮像する際は全
画素の信号を読み出し、動画を出力する際は信号を間引
いてそのかわり高速な信号読み出しをおこなう、画素配
列のうちの一部のブロックの信号を読み出し、その信号
を用いて自動焦点合わせや自動露出を行うといった使い
方ができる。For example, when capturing a high-definition still image, signals of all pixels are read, and when outputting a moving image, signals are thinned out and high-speed signal reading is performed instead. A signal can be read, and the signal can be used to perform automatic focusing and automatic exposure.
【0010】[0010]
【発明が解決しようとする課題】しかしながら、本回路
構成および動作タイミングでは読み飛ばされた光電変換
素子(たとえば図7、図9のPD2)はリセットが行わ
れないため光電変換素子に蓄積する電荷は光照射後いず
れ飽和電荷量に達し、飽和電荷量を越えて発生した電荷
は隣接する光電変換素子に流入し、隣接画素に偽信号を
発生させる原因となっていた。However, the photoelectric conversion element (for example, PD2 in FIGS. 7 and 9) which has been skipped in the present circuit configuration and operation timing is not reset, so that the electric charge accumulated in the photoelectric conversion element is small. After the light irradiation, the charge reaches the saturated charge amount, and the charge generated beyond the saturated charge amount flows into the adjacent photoelectric conversion element, causing a false signal to be generated in the adjacent pixel.
【0011】さらに詳しく説明するために図10に光電
変換素子の模式断面図とそのポテンシャル図を示す。図
10(a)に光電変換素子の模式断面図である。同図に
おいて図7と同一番号は同一部材を示す。図10(a)
において、401は第一導電型のSi半導体基板、40
2は基板1と反対の第二導電型のウエル領域、403は
第一導電型の拡散領域であり、ウエル領域402との間
でPNフォトダイオードを形成している。PNフォトダ
イオードには、逆バイアスが印加され、その接合容量に
入射した光量に応じて発生した光電荷が蓄積される。光
電荷数に応じて発生した電圧振幅を、ソースフォロワア
ンプで検出して外部に電器信号として出力されるもので
ある。FIG. 10 is a schematic cross-sectional view of a photoelectric conversion element and a potential diagram thereof for explaining it in more detail. FIG. 10A is a schematic sectional view of the photoelectric conversion element. 7, the same numbers as those in FIG. 7 indicate the same members. FIG. 10 (a)
, 401 is a first conductivity type Si semiconductor substrate;
Reference numeral 2 denotes a second conductivity type well region opposite to the substrate 1, and reference numeral 403 denotes a first conductivity type diffusion region, which forms a PN photodiode with the well region 402. A reverse bias is applied to the PN photodiode, and photocharges generated according to the amount of light incident on the junction capacitance are accumulated. The voltage amplitude generated according to the number of photocharges is detected by a source follower amplifier and output to the outside as an electric signal.
【0012】また、403−aを図7のPD1、403
−bを図7のPD2したとき、図10(b)〜(d)は
それぞれ、図9の時刻t4、t5、t6における各部の
ポテンシャルの状態を示している。Further, 403-a is replaced with PD1, 403 in FIG.
When −b is changed to PD2 in FIG. 7, FIGS. 10B to 10D show the potential states of the respective parts at times t4, t5, and t6 in FIG. 9, respectively.
【0013】図10(b)に示したように読み飛ばされ
た画素のフォトダイオードPD2はリセットが行われな
いため電荷が蓄積しており、図10(c)に示したよう
にフォトダイオードPD1の蓄積期間の途中で飽和に達
してしまう。そのため図10(d)に示したようなフォ
トダイオードPD2からあふれた電荷はポテンシャル障
壁を越えて隣接画素、たとえばPD1に流入し偽信号と
なってしまう。As shown in FIG. 10B, since the photodiode PD2 of the skipped pixel is not reset, electric charge is accumulated, and as shown in FIG. Saturation is reached during the accumulation period. Therefore, the charge overflowing from the photodiode PD2 as shown in FIG. 10D flows into a neighboring pixel, for example, PD1, over a potential barrier and becomes a false signal.
【0014】本発明は、静止画撮像の場合には全画素を
読み出すことで全画素をリセットし、光電荷のあふれを
防止できるが、動画を撮影する場合の間引き読み出しの
場合の間引きされた画素による光電荷のあふれの影響を
防止することを課題とする。According to the present invention, all pixels are reset by reading out all pixels in the case of capturing a still image, and overflow of photoelectric charges can be prevented. It is an object of the present invention to prevent the influence of the overflow of the photocharge due to the above.
【0015】[0015]
【課題を解決するための手段および作用】本発明は上記
問題点を解決する手段として、複数の光電変換素子と前
記光電変換素子をリセットするリセットスイッチとから
なる画素をマトリクス状に配列し、各画素の信号を読み
出すための垂直走査手段および水平走査手段を有する光
電変換装置において、信号を読み出す第一の画素群と信
号を読み出さない第二の画素群とを有し、前記第一の画
素群の信号電荷の蓄積期間中の少なくとも一部の期間
で、前記第二の画素群に含まれる光電変換素子を前記リ
セットスイッチによりリセットするようにしたものであ
る。According to the present invention, as a means for solving the above-mentioned problems, pixels each including a plurality of photoelectric conversion elements and a reset switch for resetting the photoelectric conversion elements are arranged in a matrix, and In a photoelectric conversion device having a vertical scanning unit and a horizontal scanning unit for reading pixel signals, the first pixel group includes a first pixel group for reading signals and a second pixel group for not reading signals. The photoelectric conversion element included in the second pixel group is reset by the reset switch during at least a part of the signal charge accumulation period.
【0016】また、本発明は、複数の光電変換素子と、
前記光電変換素子に発生した信号電荷を受ける増幅手段
と、前記増幅手段に電荷を転送する転送スイッチ手段
と、前記光電変換素子を前記転送スイッチ手段を介して
リセットするリセットスイッチとからなる画素をマトリ
クス状に配列し、各画素の信号を読み出すための垂直走
査手段および水平走査手段を有する光電変換装置におい
て、前記画素の信号を読み出す第一の画素群と前記画素
の信号を読み出さない第二の画素群とを有し、前記第一
の画素群の信号電荷の蓄積期間中の少なくとも一部の期
間で、前記第二の画素群に含まれる光電変換素子を前記
転送スイッチ手段を介して前記リセットスイッチにより
リセットすることを特徴とし、画素の信号を読み出さな
い第二の画素群による過電荷の蓄積を防止し、隣接画素
の第一の画素群への影響を防止するようにしたものであ
る。Further, the present invention provides a plurality of photoelectric conversion elements,
A matrix comprising: an amplifying unit that receives a signal charge generated in the photoelectric conversion element; a transfer switch unit that transfers the charge to the amplifying unit; and a reset switch that resets the photoelectric conversion element via the transfer switch unit. In a photoelectric conversion device having a vertical scanning unit and a horizontal scanning unit for reading out the signal of each pixel, a first pixel group that reads out the signal of the pixel and a second pixel that does not read out the signal of the pixel And at least a part of the signal charge accumulation period of the first pixel group during a period in which the photoelectric conversion elements included in the second pixel group are connected to the reset switch via the transfer switch means. To prevent accumulation of overcharge by the second pixel group that does not read out the signal of the pixel, and to store the adjacent pixel in the first pixel group. It is obtained so as to prevent the sound.
【0017】また、本発明は、複数の光電変換素子と前
記光電変換素子をリセットするリセットスイッチとから
なる画素をマトリクス状に配列し、各画素の信号を読み
出すための垂直走査手段および水平走査手段を有する光
電変換装置において、前記画素の信号を読み出す第一の
画素群と前記画素の信号を読み出さない第二の画素群と
を有し、前記第二の画素群に含まれる光電変換素子を前
記リセットスイッチにより常時リセットする手段を設け
たことを特徴とし、画素の信号を読み出さない第二の画
素群による光電荷を電源ラインに常時放電することによ
り、隣接する第一の画素群への光電荷漏れ等の悪影響を
削減したものである。Also, the present invention provides a vertical scanning means and a horizontal scanning means for arranging pixels comprising a plurality of photoelectric conversion elements and a reset switch for resetting the photoelectric conversion elements in a matrix, and reading out signals of each pixel. In a photoelectric conversion device having a first pixel group that reads the signal of the pixel and a second pixel group that does not read the signal of the pixel, the photoelectric conversion element included in the second pixel group A means for constantly resetting by a reset switch is provided, and by constantly discharging a photocharge from a second pixel group that does not read out a pixel signal to a power supply line, a photocharge to an adjacent first pixel group is provided. This is to reduce adverse effects such as leakage.
【0018】[0018]
【発明の実施の形態】本発明による実施形態について、
図面を参照しつつ詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments according to the present invention will be described.
This will be described in detail with reference to the drawings.
【0019】[第一実施形態]本発明の第一実施形態に
よる光電変換装置の回路構成図は図7に示したものと同
一である。図7は上述した通りの構成を示しており、再
掲すると、光電変換素子(フォトダイオードなど)1は
入射光量に応じた電荷を蓄積するものであり、2次元状
に4個×4個の例にて配置されている。光電変換素子1
の一端は増幅型ソースフォロワ入力MOS(Metal Oxid
e Silicon Transistor)2のゲートに接続し、その他端
は半導体基板のサブストレートに接続され、ソースフォ
ロワ入力MOS2のドレインは垂直選択スイッチMOS
3のソースに接続し、またソースフォロワ入力MOS2
のソースは垂直出力線6を経て負荷電流源7へと接続
し、垂直選択スイッチMOS3のドレインは電源線4を
経て電源端子5に接続されており、これらは全体でソー
スフォロワ回路を構成している。14はリセットスイッ
チであり、そのソースは光電変換素子1のカソード側と
ソースフォロワ入力MOS2のゲートに接続し、ドレイ
ンは電源線4を経て電源端子5に接続され、ゲートはリ
セットラインRES1に接続されている。[First Embodiment] The circuit configuration diagram of the photoelectric conversion device according to the first embodiment of the present invention is the same as that shown in FIG. FIG. 7 shows the configuration as described above. In other words, the photoelectric conversion element (such as a photodiode) 1 accumulates charges according to the amount of incident light. It is arranged at. Photoelectric conversion element 1
One end of the amplifier is an amplified source follower input MOS (Metal Oxid
e Silicon Transistor) 2, the other end is connected to the substrate of the semiconductor substrate, and the source follower input MOS2 drain is a vertical selection switch MOS
3 and the source follower input MOS2
Are connected to a load current source 7 via a vertical output line 6, and the drain of the vertical selection switch MOS3 is connected to a power supply terminal 5 via a power supply line 4, and these constitute a source follower circuit as a whole. I have. Reference numeral 14 denotes a reset switch whose source is connected to the cathode side of the photoelectric conversion element 1 and the gate of the source follower input MOS 2, whose drain is connected to the power supply terminal 5 via the power supply line 4, and whose gate is connected to the reset line RES 1. ing.
【0020】本回路はリセットスイッチ14によりリセ
ットした後、各画素の光電変換素子1に蓄積された電荷
に応じてソースフォロワ入力MOS2のゲートに信号電
圧が発生し、それをソースフォロワ回路で電流増幅して
読み出すものである。In this circuit, after resetting by the reset switch 14, a signal voltage is generated at the gate of the source follower input MOS 2 according to the electric charge accumulated in the photoelectric conversion element 1 of each pixel, and the signal voltage is amplified by the source follower circuit. And read it out.
【0021】図1に本発明の第一の実施形態の動作タイ
ミング図を示す。同図において、動画の撮像の際の間引
き動作のために、選択スイッチパルスSEL2,SEL
4は常にローレベルであり、選択スイッチパルスSEL
1をハイレベルとした後に、時刻t0でリセットスイッ
チパルスRES1をハイレベルとしてPD1をリセット
し、次に選択スイッチパルスSEL1をハイレベルと
し、時刻t9で水平走査パルスH1をハイレベルとして
蓄積されたPD1の光電荷を出力線6を介して読み出
す。FIG. 1 shows an operation timing chart of the first embodiment of the present invention. In the figure, selection switch pulses SEL2 and SEL are used for a thinning operation at the time of capturing a moving image.
4 is always at the low level, and the selection switch pulse SEL
After 1 is set to the high level, the reset switch pulse RES1 is set to the high level at time t0 to reset the PD1, then the selection switch pulse SEL1 is set to the high level, and the horizontal scanning pulse H1 is set to the high level at the time t9. Is read out via the output line 6.
【0022】ここで、リセットスイッチパルスRES
2、RES4を常にハイレベルにしているので、光電変
換素子PD2の電荷はリセットスイッチ14を介して、
電源線4を経て電源端子5に接続されて排出され、隣接
画素への電荷の流入が抑制され偽信号が発生しないもの
である。また、時刻t9の後、水平走査パルスH1をハ
イレベルとしても、PD2に光電荷は蓄積されていない
ので、光電荷は出力されない。Here, the reset switch pulse RES
2, RES4 is always at a high level, so the electric charge of the photoelectric conversion element PD2 passes through the reset switch 14,
It is connected to the power supply terminal 5 via the power supply line 4 and is discharged. The charge is prevented from flowing into the adjacent pixels and no false signal is generated. After the time t9, even if the horizontal scanning pulse H1 is set to the high level, no photocharge is output since no photocharge is accumulated in the PD2.
【0023】さらに詳しく説明するために図2に光電変
換素子の模式断面図とそのポテンシャル図を示す。図2
(a)は光電変換素子の模式断面図である。同図におい
て、図7、図10と同一番号は同一部材を示し重複する
説明を省略する。図2(a)において、403−aを図
7のPD1、403−bを図7のPD2としたとき、図
2(b)〜(d)はそれぞれ、図1の時刻t0、t7、
t8、t9における各部のポテンシャルの状態を示して
いる。FIG. 2 shows a schematic cross-sectional view of a photoelectric conversion element and a potential diagram thereof for explaining it in more detail. FIG.
(A) is a schematic sectional view of a photoelectric conversion element. 7, the same reference numerals as those in FIGS. 7 and 10 denote the same members, and a duplicate description will be omitted. In FIG. 2A, when 403-a is PD1 in FIG. 7 and 403-b is PD2 in FIG. 7, FIGS. 2B to 2D respectively show times t0, t7,
The potential state of each part at t8 and t9 is shown.
【0024】図2(b)に示したように、読み飛ばされ
た画素のフォトダイオードPD2はリセットが行われて
いるため電荷が蓄積しておらず、そのため、図2(c)
及び(d)に示したように、フォトダイオードPD2で
発生した電荷はポテンシャル障壁を越えて隣接画素、た
とえばPD1に流入することなく偽信号を発生させない
ものである。As shown in FIG. 2B, since the photodiode PD2 of the skipped pixel has been reset, no electric charge is accumulated, and as a result, the photodiode PD2 of FIG.
As shown in (d), the charges generated by the photodiode PD2 do not generate a false signal without flowing into an adjacent pixel, for example, PD1, beyond the potential barrier.
【0025】上記動作によって、偽信号の発生を防止す
ると共に、スミア、ブルーミング、混色のない高品質の
画像が得られるものである。By the above operation, generation of a false signal is prevented, and a high-quality image free from smear, blooming, and color mixture is obtained.
【0026】[第二実施形態]図3は本発明の第二実施
形態による動作を実現するための垂直走査回路9の模式
回路図である。[Second Embodiment] FIG. 3 is a schematic circuit diagram of a vertical scanning circuit 9 for realizing the operation according to the second embodiment of the present invention.
【0027】図3において、501はシフトパルス発生
回路、502は第一の転送スイッチ、503は第二の転
送スイッチ、504はORゲート、505は動画と静止
画等の読みだしモード切り替え信号入力端子である。In FIG. 3, reference numeral 501 denotes a shift pulse generating circuit, 502 denotes a first transfer switch, 503 denotes a second transfer switch, 504 denotes an OR gate, and 505 denotes a read mode switching signal input terminal for a moving image and a still image. It is.
【0028】読みだしモード切り替え信号入力端子50
5にローレベルが入力されているときは、第一の転送ス
イッチ502が導通、第二の転送スイッチ503が非導
通となるため、RES1、SEL1〜RSE4、SEL
4パルスが順次出力され、全画素の信号が読み出され
る。Read mode switching signal input terminal 50
5, when the low level is input, the first transfer switch 502 is turned on and the second transfer switch 503 is turned off, so that RES1, SEL1 to RSE4, SEL
Four pulses are sequentially output, and signals of all pixels are read.
【0029】次に読みだしモード切り替え信号入力端子
505にハイレベルが入力されているときは、第一の転
送スイッチ502が非導通、第二の転送スイッチ503
が導通となるため、2番目、4番目のシフトパルス発生
回路501にはシフトパルスが転送されない。そのため
SEL2、SEL4として常にローレベルが出力され、
このパルスが印加される垂直ゲート線8に接続した画素
から信号は読み出されないことになる。またこの時に、
ORゲート504の一方の端子には読みだしモード切り
替え信号入力端子505からハイレベルが印加されてい
るため、RES2,RES4として常にハイレベルが出
力され、このパルスが印加されるリセットゲート線15
に接続した画素、つまり読み飛ばされた画素の光電変換
素子をリセットするリセットスイッチ14は常に導通状
態に保持されるので、電荷はすみやかに電源端子5に排
出され偽信号を発生させないものである。Next, when a high level is input to the read mode switching signal input terminal 505, the first transfer switch 502 is turned off and the second transfer switch 503 is turned on.
Are turned on, no shift pulse is transferred to the second and fourth shift pulse generation circuits 501. Therefore, a low level is always output as SEL2 and SEL4,
No signal is read from the pixel connected to the vertical gate line 8 to which this pulse is applied. At this time,
Since a high level is applied to one terminal of the OR gate 504 from the read mode switching signal input terminal 505, a high level is always output as RES2 and RES4, and the reset gate line 15 to which this pulse is applied is applied.
Since the reset switch 14 for resetting the photoelectric conversion element of the pixel connected to the pixel, that is, the skipped pixel, is always kept in a conductive state, the electric charge is immediately discharged to the power supply terminal 5 and a false signal is not generated.
【0030】モード切り替え信号入力端子505には、
高密度で高画質を求められる静止画の場合にはローレベ
ルを入力し、動画を撮影する場合の高速フレーム変換を
要求される場合にはハイレベルとして、光電変換素子の
半分の光電荷を読み出すようにする。また、上記実施形
態で、奇数垂直線を活かして偶数垂直線を読み出さない
例を示したが、これを逆としても良く、また、1列を読
み出してn列を読み出さないようにしても良く、例えば
オートフォーカスの焦点レンズ位置を設定する場合や、
オート露光の場合等の画質を重視しない場合等に適用で
きる。The mode switching signal input terminal 505 has:
When a still image requires high density and high image quality, input a low level. When a high-speed frame conversion is required when shooting a moving image, set it to a high level and read out half of the photoelectric charge of the photoelectric conversion element. To do. Further, in the above-described embodiment, an example in which the odd-numbered vertical lines are not used to read out the even-numbered vertical lines has been described. However, this may be reversed, or one column may be read and n columns may not be read. For example, when setting the focus lens position for auto focus,
This can be applied to a case where the image quality is not important such as in the case of auto exposure.
【0031】本回路構成のように、シフトパルス発生回
路の後段にORゲートを追加して、その一方の入力に読
みだし、モード切り替え信号を入力することより、新規
に制御パルスを追加することなく所望の動作を実現した
ものである。As in the present circuit configuration, an OR gate is added at the subsequent stage of the shift pulse generating circuit, a read is performed at one of its inputs, and a mode switching signal is input, so that a new control pulse is not added. The desired operation is realized.
【0032】[第三実施形態]図4は本発明の第三実施
形態による別の画素構成に応用した例である。同図にお
いて、図7と同一番号は同一部材を示している。本実施
形態の画素はソースフォロワ増幅手段を用いず、フォト
ダイオード1に蓄積された信号電荷を直接読み出す方式
のものである。本構成の画素においても、読み出さない
画素のリセットスイッチ14を導通させて、蓄積した電
荷を電源線4に排出することにより偽信号の発生を抑制
することができる。[Third Embodiment] FIG. 4 shows an example applied to another pixel configuration according to a third embodiment of the present invention. 7, the same reference numerals as those in FIG. 7 indicate the same members. The pixel of the present embodiment is of a type that directly reads out signal charges stored in the photodiode 1 without using a source follower amplifying unit. Also in the pixel having this configuration, the generation of the false signal can be suppressed by turning on the reset switch 14 of the pixel that is not read out and discharging the accumulated charge to the power supply line 4.
【0033】図4において、フォトダイオード1は、M
OSFETのリセットスイッチ14のソースを接続さ
れ、転送MOSFET3のソースにも接続され、リセッ
トスイッチ14のゲートはリセットパルスRES2に接
続され、転送MOSFET3のゲートは選択パルスSE
L2に、そのドレインは出力線6に接続されている。他
の各光電変換装置も同様な周辺回路に接続され、特にフ
ォトダイオード1をPD2とする場合、リセットスイッ
チ14のゲートを常にハイレベルとするリセットパルス
RES2に接続されているので、リセットスイッチ14
は常に導通状態となり、PD2に光電荷を蓄えることな
く放電されて、過充電もない。一方、通常動作の1列目
や3列目は、リセットパルス及び選択パルスは通常通り
に印加されるので、所定の走査時間にリセットされ、フ
ォトダイオード1に所定時間の光電荷の蓄積後に読み出
される。In FIG. 4, the photodiode 1 has an M
The source of the reset switch 14 of the OSFET is connected to the source of the transfer MOSFET 3, the gate of the reset switch 14 is connected to the reset pulse RES2, and the gate of the transfer MOSFET 3 is connected to the selection pulse SE.
L2 has its drain connected to output line 6. Each of the other photoelectric conversion devices is also connected to a similar peripheral circuit. In particular, when the photodiode 1 is the PD2, it is connected to the reset pulse RES2 that always sets the gate of the reset switch 14 to the high level.
Is always in a conductive state, is discharged without storing photocharges in PD2, and there is no overcharge. On the other hand, in the first and third columns of the normal operation, since the reset pulse and the selection pulse are applied as usual, they are reset for a predetermined scanning time, and are read out after the photodiode 1 has accumulated photocharges for a predetermined time. .
【0034】[第四実施形態]図5は本発明の第四実施
形態によるさらに別の画素構成に応用した画素の回路図
例である。同図においても、図7と同一番号は同一部材
を示している。同図において、901は光電変換素子1
からソースフォロワ入力MOS2の入力ゲートへ信号電
荷を完全空乏転送する電荷転送スイッチである。902
は転送スイッチ901を制御する転送ゲート線である。
一般に、光電変換装置の感度を向上させるために、光電
変換素子1のサイズを大きくし、信号電荷量を増す方法
がとられるが、それにともないソースフォロワ入力MO
S2のゲートに寄生する容量値もおおきくなり、効率よ
く感度を向上できないという問題点があったが、本構造
をとり、ソースフォロワ入力MOS2の入力ゲートの容
量値を光電変換素子1(フォトダイオードなど)の容量
値より小さく設計しておき、完全空乏転送をおこなうこ
とで、感度を向上させることができる。[Fourth Embodiment] FIG. 5 is an example of a circuit diagram of a pixel applied to still another pixel configuration according to a fourth embodiment of the present invention. Also in this figure, the same numbers as those in FIG. 7 indicate the same members. In the figure, reference numeral 901 denotes a photoelectric conversion element 1
Is a charge transfer switch for completely depleting transfer of the signal charge from the gate to the input gate of the source follower input MOS2. 902
Is a transfer gate line for controlling the transfer switch 901.
In general, in order to improve the sensitivity of the photoelectric conversion device, a method of increasing the size of the photoelectric conversion element 1 and increasing the amount of signal charges is adopted.
The parasitic capacitance of the gate of S2 also becomes large, and there is a problem that the sensitivity cannot be improved efficiently. However, with this structure, the capacitance of the input gate of the source follower input MOS2 is changed to the photoelectric conversion element 1 (photodiode or the like). The sensitivity can be improved by designing the capacitance value to be smaller than the value in (1) and performing the complete depletion transfer.
【0035】全画素を読み出す通常時は、選択パルス8
の印加と、リセットパルス15の印加とがタイミング通
りに供給され、リセットパルス15の印加後、所定時間
後に選択パルス8の印加の前に、転送ゲート線902に
パルスを印加して電荷転送スイッチ901を導通する。
そして、フォトダイオード1に蓄積された光電荷をソー
スフォロワ入力MOS2のゲートに転送し、その後選択
パルス8の印加により選択スイッチ3を導通して、ソー
スフォロワ入力MOS2のソースの出力線6に電力増幅
して出力する。At the normal time when all pixels are read, the selection pulse 8
And the application of the reset pulse 15 are supplied according to the timing. After the application of the reset pulse 15, a pulse is applied to the transfer gate line 902 after a predetermined time and before the application of the selection pulse 8, and the charge transfer switch 901 is applied. Is conducted.
Then, the optical charge accumulated in the photodiode 1 is transferred to the gate of the source follower input MOS 2, and then the selection switch 3 is turned on by the application of the selection pulse 8, and the power is amplified to the output line 6 of the source of the source follower input MOS 2. And output.
【0036】また、偶数画素を間引き読み出す場合に
は、上記転送ゲート線902を常時ハイレベルとして電
荷転送スイッチ901を導通して、リセットパルス15
を常時ハイレベルとしてリセットスイッチ14も同時に
導通状態として、フォトダイオード1に蓄積される光電
荷を常に電源ラインに放電され、過充電状態を無くし、
隣接フォトダイオードへの影響を無くしている。When thinning out and reading out even-numbered pixels, the transfer gate line 902 is always set to the high level, the charge transfer switch 901 is turned on, and the reset pulse 15 is reset.
Is always at a high level, and the reset switch 14 is also turned on at the same time, so that the photocharge accumulated in the photodiode 1 is constantly discharged to the power supply line, eliminating the overcharge state,
The influence on the adjacent photodiode is eliminated.
【0037】本画素構成においても、読み出さない画素
のリセットスイッチおよび転送スイッチを通電させてお
く蓄積した電荷を排出することにより偽信号の発生を抑
制することができる。Also in the present pixel configuration, generation of a false signal can be suppressed by discharging the accumulated electric charge that keeps the reset switch and the transfer switch of the pixel that is not read out.
【0038】[第五実施形態]図6は本発明の第五実施
形態を示す動作タイミング図である。本実施形態による
基本的な回路構成は図7と同様である。図6に示したよ
うに、読み飛ばされた画素のリセットスイッチ14の駆
動パルスRES2、RES4を少なくとも1映像期間に
一度ハイレベルにすることによっても、同様の効果が得
られるものである。従来例として説明した図8のタイミ
ングとは異なり、フォトダイオード1のPD1とPD2
とを時刻t0,t10に同時にリセットし、選択パルス
SEL2を常にローレベルとしているので、PD1とP
D2とは同一光電荷が蓄積され、同時にリセットパルス
が加わり、所定時間後の時刻t2にPD1の蓄積電荷が
読み出される。こうして、PD1とPD2とが共に過電
荷を蓄積することはなく、PD2による隣接画素PD1
への影響もなくなる。[Fifth Embodiment] FIG. 6 is an operation timing chart showing a fifth embodiment of the present invention. The basic circuit configuration according to the present embodiment is the same as that in FIG. As shown in FIG. 6, the same effect can be obtained by setting the drive pulses RES2 and RES4 of the reset switch 14 of the skipped pixel to high level at least once in one video period. Unlike the timing of FIG. 8 described as a conventional example, PD1 and PD2 of the photodiode 1 are different.
Are simultaneously reset at times t0 and t10, and the selection pulse SEL2 is always at the low level.
The same photocharge is accumulated in D2, and at the same time, a reset pulse is applied, and the accumulated charge in PD1 is read out at time t2 after a predetermined time. Thus, neither PD1 nor PD2 accumulates overcharge, and the adjacent pixel PD1 by PD2 does not accumulate.
There is no effect on
【0039】また、上記従来例では部分読みだし時とし
て1画素行ごとに読み飛ばす場合を例にとって説明した
がこれに限るものではなく、本発明は用途に応じて任意
の読み飛ばしを行ったときにも適用できることはいうま
でもない。In the above-described conventional example, the case of skipping one pixel row at a time of partial reading has been described as an example. However, the present invention is not limited to this, and the present invention is applicable to a case where arbitrary skipping is performed according to the application. Needless to say, it can be applied to
【0040】[0040]
【発明の効果】以上説明したように、本発明の構造をと
ることにより偽信号の発生を抑制でき、ブルーミングが
発生しない、スミアが発生しない、混色が生じない、高
画質が得られる光電変換装置を得ることができるもので
ある。As described above, by adopting the structure of the present invention, the generation of a false signal can be suppressed, and no blooming occurs, no smear occurs, no color mixing occurs, and a high-quality photoelectric conversion device can be obtained. Can be obtained.
【図1】本発明による第一の実施形態の動作タイミング
図である。FIG. 1 is an operation timing chart of a first embodiment according to the present invention.
【図2】本発明による第一の実施形態の画素模式断面図
およびポテンシャル図である。FIG. 2 is a schematic sectional view and a potential diagram of a pixel according to the first embodiment of the present invention.
【図3】本発明による第二の実施形態の走査回路模式説
明図である。FIG. 3 is a schematic diagram illustrating a scanning circuit according to a second embodiment of the present invention.
【図4】本発明による第三の実施形態の画素回路模式説
明図である。FIG. 4 is a schematic diagram illustrating a pixel circuit according to a third embodiment of the present invention.
【図5】本発明による第四の実施形態の画素回路模式説
明図である。FIG. 5 is a schematic diagram illustrating a pixel circuit according to a fourth embodiment of the present invention.
【図6】本発明による第五の実施形態の動作タイミング
図である。FIG. 6 is an operation timing chart of a fifth embodiment according to the present invention.
【図7】従来の光電変換装置の模式説明図である。FIG. 7 is a schematic explanatory view of a conventional photoelectric conversion device.
【図8】従来の光電変換装置の全画素読みだし時動作タ
イミング図である。FIG. 8 is an operation timing chart at the time of reading all pixels of a conventional photoelectric conversion device.
【図9】従来の光電変換装置の部分読みだし時動作タイ
ミング図である。FIG. 9 is an operation timing chart at the time of partial reading of the conventional photoelectric conversion device.
【図10】従来例の画素模式断面図およびポテンシャル
図である。FIG. 10 is a schematic sectional view and a potential diagram of a conventional pixel.
1 光電変換素子(フォトダイオードなど) 2 増幅型ソースフォロワ入力MOS(Metal Oxide Si
licon Transistor) 3 垂直選択スイッチMOS 4 電源線 5 電源端子 6 垂直出力線 7 負荷電流源 8 垂直ゲート線 9 垂直走査回路 10 水平転送MOSスイッチ 11 水平出力線 12 出力アンプ 13 水平走査回路 14 リセットスイッチ 15 リセットゲート線 401 半導体基板 402 ウェル 403 フォトダイオード(PN結合) 501 走査パルス発生器 502,503 転送スイッチ 504 OR回路 505 モード切替端子 901 転送スイッチ 902 転送スイッチパルス線1 Photoelectric conversion element (photodiode, etc.) 2 Amplification type source follower input MOS (Metal Oxide Si
3 vertical select switch MOS 4 power supply line 5 power supply terminal 6 vertical output line 7 load current source 8 vertical gate line 9 vertical scanning circuit 10 horizontal transfer MOS switch 11 horizontal output line 12 output amplifier 13 horizontal scanning circuit 14 reset switch 15 Reset gate line 401 Semiconductor substrate 402 Well 403 Photodiode (PN coupling) 501 Scan pulse generator 502, 503 Transfer switch 504 OR circuit 505 Mode switching terminal 901 Transfer switch 902 Transfer switch pulse line
Claims (6)
をリセットするリセットスイッチとからなる画素をマト
リクス状に配列し、各画素の信号を読み出すための垂直
走査手段および水平走査手段を有する光電変換装置にお
いて、 前記画素の信号を読み出す第一の画素群と前記画素の信
号を読み出さない第二の画素群とを有し、前記第一の画
素群の信号電荷の蓄積期間中の少なくとも一部の期間
で、前記第二の画素群に含まれる光電変換素子を前記リ
セットスイッチによりリセットすることを特徴とする光
電変換装置。1. A photoelectric conversion device comprising: a plurality of photoelectric conversion elements and pixels each including a reset switch for resetting the photoelectric conversion elements arranged in a matrix, and having a vertical scanning unit and a horizontal scanning unit for reading out a signal of each pixel. In the device, comprising a first pixel group that reads the signal of the pixel and a second pixel group that does not read the signal of the pixel, at least a part of the first pixel group during the signal charge accumulation period A photoelectric conversion device, wherein a photoelectric conversion element included in the second pixel group is reset by the reset switch during a period.
子に発生した信号電荷を受ける増幅手段と、前記増幅手
段に電荷を転送する転送スイッチ手段と、前記光電変換
素子を前記転送スイッチ手段を介してリセットするリセ
ットスイッチとからなる画素をマトリクス状に配列し、
各画素の信号を読み出すための垂直走査手段および水平
走査手段を有する光電変換装置において、 前記画素の信号を読み出す第一の画素群と前記画素の信
号を読み出さない第二の画素群とを有し、前記第一の画
素群の信号電荷の蓄積期間中の少なくとも一部の期間
で、前記第二の画素群に含まれる光電変換素子を前記転
送スイッチ手段を介して前記リセットスイッチによりリ
セットすることを特徴とする光電変換装置。A plurality of photoelectric conversion elements, amplification means for receiving signal charges generated in the photoelectric conversion elements, transfer switch means for transferring charges to the amplification means, and transfer transfer means for connecting the photoelectric conversion elements to each other. Pixels consisting of a reset switch that resets through a matrix are arranged in a matrix,
A photoelectric conversion device having a vertical scanning unit and a horizontal scanning unit for reading a signal of each pixel, comprising: a first pixel group for reading the signal of the pixel, and a second pixel group for not reading the signal of the pixel. Resetting the photoelectric conversion elements included in the second pixel group by the reset switch via the transfer switch means in at least a part of the signal charge accumulation period of the first pixel group. Characteristic photoelectric conversion device.
をリセットするリセットスイッチとからなる画素をマト
リクス状に配列し、各画素の信号を読み出すための垂直
走査手段および水平走査手段を有する光電変換装置にお
いて、 前記画素の信号を読み出す第一の画素群と前記画素の信
号を読み出さない第二の画素群とを有し、前記第二の画
素群に含まれる光電変換素子を前記リセットスイッチに
より常時リセットする手段を設けたことを特徴とする光
電変換装置。3. A photoelectric conversion device comprising a plurality of photoelectric conversion elements and pixels each including a reset switch for resetting the photoelectric conversion elements, arranged in a matrix, and having a vertical scanning unit and a horizontal scanning unit for reading a signal of each pixel. In the device, a first pixel group that reads the signal of the pixel and a second pixel group that does not read the signal of the pixel, the photoelectric conversion element included in the second pixel group is constantly controlled by the reset switch. A photoelectric conversion device comprising a reset unit.
て、前記第一と前記第二の画素群を選択する選択手段を
有し、前記選択手段によって同時に前記常時リセット手
段を制御することを特徴とする光電変換装置。4. The photoelectric conversion device according to claim 2, further comprising a selection unit that selects the first and second pixel groups, wherein the selection unit controls the constant reset unit at the same time. Photoelectric conversion device.
電変換装置において、 前記第一の画素群と前記第二の画素群とで両画素群とも
に画素の信号を読み出す第1のモードと、前記第一の画
素群の画素の信号を読み出して前記第二の画素群の画素
の信号を読み出さない第2のモードとを有し、前記第1
のモード時は静止画を撮像し、前記第2のモード時は動
画を撮像することを特徴とする光電変換装置。5. The photoelectric conversion device according to claim 1, wherein the first pixel group and the second pixel group read pixel signals from both pixel groups. A first mode in which a signal of a pixel in the first pixel group is read out and a signal of a pixel in the second pixel group is not read out, and
The photoelectric conversion device captures a still image in the second mode and captures a moving image in the second mode.
て、 前記第1のモードと前記第2のモードとの切替は、前記
画素の読み出しを選択する選択パルスと、前記画素をリ
セットするリセットパルスとを変化させて切替え、前記
第2のモードの際に前記リセットパルスは前記読み出さ
ない画素を常時放電させることを特徴とする光電変換装
置。6. The photoelectric conversion device according to claim 5, wherein the switching between the first mode and the second mode includes a selection pulse for selecting reading of the pixel and a reset pulse for resetting the pixel. Wherein the reset pulse constantly discharges the unread pixels in the second mode.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15534099A JP3554224B2 (en) | 1999-06-02 | 1999-06-02 | Photoelectric conversion device |
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| JP3554224B2 JP3554224B2 (en) | 2004-08-18 |
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