JP2001077832A - Protocol processing device and ATM cell storage method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a protocol processing apparatus capable of improving the processing speed of the entire apparatus and improving the use efficiency of a memory when relaying a network for transmitting VC-multiplexed ATM cells, and the like. An object of the present invention is to provide an ATM cell storage method. SOLUTION: A communication signal input / output means 100 having an ATM framer 110 and a VC separation module 130 and an AT
An ATM cell processing means 200 having an M cell storage memory 201 and an ATM cell information extraction module 202 and an upper header processing means 300 having an upper header storage memory 301 and an upper header information extraction module 302 are connected in series and connected to receive the communication signal. A protocol processing device, wherein the output means 100, the ATM cell processing means 200, and the upper header processing means 300 are provided with control means which operate independently.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a protocol processing apparatus and an ATM cell storage method that can be used in a system used for relaying a network for transmitting ATM (Asynchronous Transfer Mode) cells.

[0002]

2. Description of the Related Art As a prior art of a device used for relaying a network for transmitting ATM cells, for example, JP-A-9-98189 and JP-A-11-4226 are known. Japanese Patent Laid-Open No. 9-98189 proposes extracting a network layer protocol header from the first cell of a packet and extracting information necessary for routing the packet before all cells of one packet arrive. are doing.

Japanese Patent Application Laid-Open No. H11-4226 proposes providing a plurality of AAL layer processing modules and parallelizing the processing.

[0004]

However, when processing is performed using a single processor as disclosed in Japanese Patent Laid-Open No. 9-98189, processing of all layers is performed in order, so that the entire apparatus is processed. No improvement in processing speed can be expected.

Also, TCP / IP (Transmission Control)
In order to refer to or change various information of an upper layer such as an ol protocol / Internet protocol, it is necessary to access a plurality of ATM cells included in each packet. Is not applicable. In an environment in which a plurality of VCs (virtual channels) are transmitted in a multiplexed state, it is necessary to separate ATM cells sequentially received for each VC and store them in a memory. When storing ATM cells in a memory secured as an array as disclosed in JP-A-9-98189, each V
An area for storing the received ATM cell group must be reserved for each C. Therefore, the memory is reserved for the ATM cells which are not actually received, so that the memory use efficiency is low.

The present invention provides a protocol processing apparatus and an ATM cell storage method capable of improving the processing speed of the entire apparatus and improving the use efficiency of a memory when relaying a network for transmitting VC-multiplexed ATM cells. The purpose is to provide.

[0007]

An ATM framer is connected to a transmission line capable of forming a plurality of virtual channels and inputs and outputs ATM cells to and from the transmission line. A VC separation module for separating the ATM cells input from the transmission line by the ATM framer for each virtual channel; an ATM cell storage memory for storing the ATM cells input by the ATM framer from the transmission line; and an ATM cell storage memory. An ATM cell information extraction module for extracting information from the transferred ATM cells; an upper header storage memory for storing at least payload information of the ATM cells input from the transmission line by the ATM framer; and an upper header storage memory. Processing of the ATM cell information extraction module from the transferred ATM cell A communication signal input / output means including the ATM framer and VC separation module; and an ATM cell storage memory and an ATM. An ATM cell processing means having a cell information extraction module and an upper header processing means having the upper header storage memory and the upper header information extraction module are connected in series and connected, and the communication signal input / output means, the ATM cell processing means, The header processing means is provided with a control means which operates independently.

The communication signal input / output means performs input / output of ATM cells and separation of VC. ATM cell processing means is AT
Information is extracted for each M cell. The upper header processing means,
For example, it extracts and corrects information related to upper layer protocols such as TCP and IP. In claim 1,
Since the communication signal input / output unit, the ATM cell processing unit, and the upper header processing unit which are connected in series operate independently of each other, the entire processing can be pipelined. That is, when each processing device has the necessary information, the information is transferred to the next processing device, so that a plurality of processing devices (communication signal input / output means, ATM cell processing means, upper header processing means) are optimized. Processing can be executed in parallel at the timing. As a result, the processing speed of the entire apparatus is increased.

According to a second aspect of the present invention, when the ATM cell received by the ATM framer is transferred to the ATM cell storage memory, the virtual channel of the inputted ATM cell changes. Unless otherwise, a predetermined number of ATM cells are
A transfer control means for continuously transferring a plurality of stored ATM cells after waiting until they are stored in the TM framer is provided.

For example, when DMA (direct memory access) is employed to realize high-speed data transfer between memories, it is necessary to initialize DMA control every time transfer is performed. Is transferred to D
A transfer delay occurs due to the initialization of the MA. Claim 2
In this case, since a plurality of ATM cells are continuously transferred after waiting until a plurality of ATM cells are stored in the ATM framer, a transfer delay time can be reduced. However, when the virtual channel of the input ATM cell changes, the transfer is started even before a predetermined number of ATM cells are accumulated. As a result, ATM cells can be separated and stored for each virtual channel.

According to a third aspect of the present invention, in the protocol processing apparatus of the first aspect, a plurality of upper header processing means independent from each other are connected to the ATM cell processing means, and
The high-order header processing means of the transfer destination of the ATM cell is switched according to the difference of the virtual channel to which each ATM cell input to the TM cell processing means belongs, and the ATM cells belonging to a plurality of virtual channels are parallelized by the plurality of high-order header processing means. It is characterized in that

According to the third aspect, when ATM cells of a plurality of packets multiplexed by VC are received in a mixed manner, the
Since the processing can be executed in parallel by the upper header processing means independent of each other, each packet can be processed at high speed.

According to a fourth aspect of the present invention, in the protocol processing apparatus of the first aspect, a plurality of identical processors each including at least a processor for executing a program, a program memory, a direct memory access control circuit, a programmable gate array, a bus interface, and an internal bus. Different hardware is mounted on the hardware, and each hardware is configured as the ATM cell processing means and the upper header processing means.

In the fourth aspect, since the ATM cell processing means and the higher-order header processing means are constituted by using the same hardware, the design cost and the manufacturing cost of the hardware can be reduced by commonization. According to a fifth aspect of the present invention, in the protocol processing device of the first aspect, a CR of a packet for each virtual channel received by the ATM framer from a transmission path is used.
First CRC calculation means for calculating C information in the AAL5 layer, and AAL5 for each packet for each virtual channel corrected by the processing of the upper header processing means.
A second CRC calculating means for calculating CRC information of a layer, and an ATM cell to be transmitted based on a result calculated by the second CRC calculating means when at least a packet is modified by the processing of the upper header processing means. Is corrected, and C is calculated based on the calculation result of the first CRC calculation means.
When an RC error is detected, a CRC control means for reflecting the information of the CRC error on an ATM cell to be transmitted is further provided.

Generally, CR is used to detect a transmission error.
C (Cyclic Redundancy Check) is used. To correct the contents of a packet when relaying the packet, it is necessary to recalculate the CRC. However, if an error has occurred in the received packet and the packet with the changed CRC is transmitted, the occurrence of the error in the received packet cannot be known from the content of the transmitted packet.

In the fifth aspect, the CRC of the received packet
Since the error information is reflected in the ATM cell to be transmitted,
The CRC error information during the relay can be recognized by referring to the contents of the transmitted packet. According to a sixth aspect of the present invention, in the protocol processing device of the fourth aspect, the plurality of identical hardware are connected to each other using a plurality of buses.

In the protocol processing device of the present invention, it is necessary to transfer data between the communication signal input / output means and the ATM cell processing means and between the ATM cell processing means and the upper header processing means. Further, there is a case where data is transferred from the communication signal input / output means to the ATM cell processing means, and a case where data is transferred from the ATM cell processing means to the communication signal input / output means.

The same applies to data transfer between the ATM cell processing means and the upper header processing means. Furthermore, when preparing a plurality of upper header processing means, it is necessary to transfer data between each of the plurality of upper header processing means and the ATM cell processing means. When performing high-speed data transfer between a plurality of independent units, data is generally transferred via a bus which is an aggregate of various signal lines. However, even when a plurality of units use one set of buses, a plurality of units cannot use one set of buses at the same time.

Therefore, it is necessary to control the priority of a plurality of units with respect to the use of the bus. When transferring data processed in a predetermined procedure, the priority of the bus must be controlled in accordance with the data processing procedure. Further, when another unit is using the bus, it may be necessary to wait until the use is completed.

In claim 6, a plurality of sets of buses are provided in parallel, so that a plurality of sets of buses can be used simultaneously. For example, when the communication signal input / output means and the ATM cell processing means are connected by a plurality of sets of buses, data is transferred from the communication signal input / output means to the ATM cell processing means using the first set of buses. In this case, data can be transferred from the ATM cell processing means to the communication signal input / output means using the second set of buses.

Therefore, restrictions on the order of data transfer and the timing of starting data transfer are reduced, and data can be transferred efficiently, so that processing can be executed efficiently. In addition, since a plurality of units connected via a plurality of buses have the same hardware configuration, there is no restriction on the arrangement of the plurality of units, and even when the arrangement is changed, it is determined according to the function required for each unit. If software is installed, desired functions can be realized as a whole device.

[0022] An ATM for separating ATM cells received from a transmission path capable of forming a plurality of virtual channels for each virtual channel and storing the ATM cells in a storage device.
A cell storage method, which uses a free list formed by sequentially and logically connecting unused storage areas of a fixed size for holding a header, a payload, and link information to a next storage area, and Holding the reception management data including at least the information indicating the start position of the area storing the ATM cell for each virtual channel of the ATM cell, and sequentially storing each storage area from the free list for each received ATM cell. Each ATM cell is stored in the reserved storage area, and the reserved storage area is connected to the end of the reception buffer holding each ATM cell received so far.

The free list is formed by connecting storage areas of a fixed size. Each storage area can store ATM cells. By using the link information, the position (address, etc.) of the next storage area connected to the storage area
You can know. That is, the free list is a set of small storage areas, and the positions of the storage areas need not be consecutive.

According to the seventh aspect, the storage area can be sequentially reserved from the free list.
The size of the reception buffer can be dynamically changed by linking the storage area secured at the end of the reception buffer for storing the M cells. Each storage area of the free list and the secured reception buffer may be discontinuous. In the case of VC multiplexing, a large number of ATM cells having different VCs appear sequentially, but the size of a reception buffer required for each VC cannot be specified. However, according to the seventh aspect, it is only necessary to sequentially secure a storage area for each VC for an actually received ATM cell, so there is no need to specify the size of the reception buffer, and it is not necessary to secure a fixed memory in advance. Therefore, the use efficiency of the memory is good.

According to an eighth aspect of the present invention, in the ATM cell storage method according to the seventh aspect, a first storage area for storing a plurality of ATM cells is secured from the free list, and the first storage area after processing is stored in the first storage area. The payload of the ATM cell is stored, the header of the ATM cell of the same virtual channel stored in the reception buffer is written in the first storage area, and the end of the transmission buffer holding the ATM cell to be transmitted is stored. And the remaining data following the data held in the first storage area among the data of the same virtual channel stored in the reception buffer is connected to the first storage area. It is characterized by doing.

The first storage area secured from the free list is used as a transmission buffer. That is, the first storage area is used to store processed ATM cells. Since only the payload of the ATM cell is processed in the upper layer such as TCP and IP, in claim 8 the payload of the processed ATM cell is stored in the secured first storage area, and then the header of the ATM cell is stored. Write.
The first storage area is linked at the end of the transmission buffer.

Since ATM cells that do not need to be processed in the upper layer remain in the reception buffer, the storage area of the reception buffer in which the remaining ATM cells are stored is connected to the end of the transmission buffer. A part of the reception buffer is used as it is as a transmission buffer. For this reason, it is not necessary to secure the storage area of the transmission buffer for all ATM cells, and wasteful consumption of memory is suppressed.

It should be noted that the storage area of the transmission buffer for which transmission has been completed is unnecessary, so that the area can be released and returned to the free list. Also, the area of the receiving buffer that is not linked to the transmitting buffer can be released and returned to the free list when it becomes unnecessary.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) One embodiment of a protocol processing apparatus and an ATM cell storage method according to the present invention will be described with reference to FIGS. This embodiment corresponds to claims 1 to 5, claim 7, and claim 8.

FIG. 1 is a block diagram showing a functional configuration of the protocol processing apparatus of this embodiment. FIG. 2 is a block diagram showing hardware of the protocol processing device of this embodiment. FIG. 3 is a memory map showing the configuration of the storage area on the ATM cell storage memory. FIG. 4 is a memory map showing the configuration of the storage area for reception. FIG. 5 is a flowchart showing the operation of the communication signal input / output unit and the ATM cell processing unit at the time of cell reception. FIG. 6 shows a multi-cell DMA.
It is a flowchart which shows the content of transfer. FIG. 7 is a flowchart showing the operation of the upper header processing unit.
8 is a flowchart showing a transmission process of the ATM cell processing unit. FIG. 9 is a time chart showing the operation of the communication signal input / output unit when the VC of each cell is different. FIG. 10 is a time chart showing the operation of the communication signal input / output unit when cells of the same VC continue. FIGS. 11 and 12 are memory maps showing the configuration of the storage area on the ATM cell storage memory.

In this embodiment, the ATM framer, the VC separation module, the ATM cell storage memory, the AT
M cell information extraction module, upper header storage memory, upper header information extraction module, communication signal input / output means, A
The TM cell processing means and the upper header processing means are respectively an ATM framer 110, a VC separation module 130,
TM cell storage memory 201, ATM cell information extraction module 202, upper header storage memory 301, upper header information extraction module 302, communication signal input / output unit 1
00, corresponding to the ATM cell processing unit 200 and the upper header processing unit 300.

The transfer control means of the present invention corresponds to steps S60 to S66. 5. The processor according to claim 4, a program memory, a direct memory access control circuit,
The programmable gate array, bus interface and internal bus are respectively composed of a microprocessor 230, a program memory 240, a DMA control circuit 220, an FPGA
250, C-PCI bus interface 280 and local bus 270.

The first CRC calculating means and the second CRC calculating means of claim 5
Of the input CRC calculation circuit 140
And a CRC recalculation module 204.
CRC control means corresponds to steps S39 to S41. The protocol processing device shown in FIG. 1 and FIG.
It is used as a relay device of a network including a transmission path for transmitting cells. As a transmission path, for example, SDH (Sync
hronous Digital Hierarchy) can be used.
In this type of repeater, the ATM of the signal to be relayed is
A function of referring to and correcting information for each cell or information for each packet is required. In this mode, IP, TCP
It is assumed that information up to the first layer is extracted.

In this case, IP is used as a protocol of the network layer, and RFC1577 (Classical IP and A) is used as a delivery method of an IP datagram over ATM.
RP over ATM), and the encapsulation method for IP datagrams is RFC14.
It is assumed that the method specified by the standard 83 is used and that the ATM adaptation uses the AAL5 format.

The protocol processing apparatus shown in FIG. 2 comprises a communication signal input / output unit 100 and an ATM cell processing unit 2
00 and a plurality of upper header processing units 300. The plurality of upper header processing units 300 have the same configuration and operate independently of each other. The communication signal input / output unit 100 includes an ATM framer 110, a DMA control circuit 120, a VC separation module 130, and an input CR.
A C calculation circuit 140 is provided.

The ATM cell processing unit 200 includes a data memory 210, a DMA control circuit 220, a microprocessor 230, a program memory 240, an FPGA
(Field programmable gate array) 250, Ethernet (registered trademark) interface 260, local bus 270, and C-PCI (compact PCI) bus interface 280.

The upper header processing unit 300 includes a data memory 310, a DMA control circuit 320, a microprocessor 330, a program memory 340, and an FPGA 3
50, an Ethernet interface 360, a local bus 370, and a C-PCI bus interface 380. As shown in FIG. 2, the hardware of the ATM cell processing unit 200 and the upper header processing unit 30
0 are almost the same, and are configured according to the same standard. However, the ATM cell processing unit 20
0 is different from the software installed in the upper header processing unit 300, so that each unit realizes a different function.

In this example, using the same hardware,
Since you can configure different types of units (200, 300)
The hardware design cost can be reduced, and the manufacturing cost can be reduced by common use.

When viewed functionally, as shown in FIG.
The M cell processing unit 200 has an ATM cell storage memory 2
01, a DMA control circuit 220, an ATM cell information extraction module 202, a VCI management memory 203, a CRC recalculation module 204, and an information input / output circuit 205. ATM cell storage memory 201 is data memory 2
10, the ATM cell information extraction module 202 corresponds to the microprocessor 230, the VCI management memory 203 corresponds to the data memory 210, the CRC recalculation module 204 corresponds to the FPGA 250, and the information input / output circuit 205 corresponds to the Ethernet. Corresponds to interface 260.

Similarly, the upper header processing unit 300 includes an upper header storage memory 301 and a DMA control circuit 32.
0, an upper header information extraction module 302 and an information input / output circuit 303 are provided. Upper header storage memory 3
01 corresponds to the data memory 310, the upper header information extraction module 302 corresponds to the microprocessor 330, and the information input / output circuit 303 corresponds to the Ethernet interface 360.

In this example, the communication signal input / output unit 10 as shown in FIG.
0, the ATM cell processing unit 200, and the upper header processing unit 300 are connected in series. In FIG. 1, only one upper header processing unit 300 is connected to the ATM cell processing unit 200. However, in practice, as shown in FIG. 2, a plurality of upper header processing units 300 are connected in parallel to the ATM cell processing unit 200. It is connected to the.

The communication signal input / output unit 100 transfers the received ATM cells to the ATM cell processing unit 200 while processing them internally. ATM cell processing unit 20
0 is the AT transferred from the communication signal input / output unit 100.
The payload is transferred to the upper header processing unit 300 while processing the M cell. Upper header processing unit 3
00 processes the information of the payload transferred from the ATM cell processing unit 200 and processes the upper layer protocol (IP, TC
The information of P) is extracted and corrected.

The upper header processing unit 300 transfers the processed ATM cell payload to the ATM cell processing unit 200. The ATM cell processing unit 200 stores the packet containing the modified ATM cell for transmission, and transfers the packet to the communication signal input / output unit 100. The communication signal input / output unit 100 sends the ATM cells of each packet to the transmission path.

The ATM framer 110 assembles the received signal input from the transmission line into ATM cells. Further, it decomposes the ATM cell to be transmitted and outputs it to the transmission path as a transmission signal. When the ATM framer 110 receives the ATM cell, the VC separation module 130 reads the content of the header from the received ATM cell, and reads out the VC contained in the header.
The virtual channel of the cell is identified from I (virtual channel identifier) (S11 in FIG. 5).

In this example, A received by each VC
The CID (connection ID) is acquired by the VC separation module 130 for each packet of the TM cell. Then, a list of CIDs associated with the VCI of each packet is formed on the VCI management memory 203 as a reception management table (see FIG. 4). By searching the reception management table, it is possible to know whether or not the CID of the received packet already exists. That is, a specific VC
When the first cell is received, the CID has not yet been acquired, and the reception management table stores the C
ID does not exist.

Therefore, when the first cell of a specific VC is received, one unused CID prepared in advance is acquired and added to the reception management table (S12 and S1 in FIG. 5).
3). For unused CIDs, for example, a required number of CIDs expected in a stack (last-in first-out memory) area may be prepared in the VCI management memory 203 in advance.

[0047] The acquired CID is the
After the TM cell is transmitted to the transmission line, it becomes unnecessary and is returned to the stack. Therefore, the acquired CID of each VC is released when the transmission of the packet is completed. VCI management memory 20
3 holds information for identifying whether the VC of the last received ATM cell matches the VC currently being processed, and information indicating the correspondence between each VCI and each acquired CID. ing.

In a certain VC, a cell of the same VC received after reception of the last cell is defined as a first cell of the VC. By referring to the PT value included in the header of the ATM cell, it is possible to identify whether the cell is the end cell of each VC. That is, the least significant bit “user-
If "user identification" is 1, it is the last cell of the AAL5 CPCS-PDU, otherwise it is not the last cell.

Since the size of each ATM cell is fixed,
In this example, a reception buffer for holding received ATM cells on the ATM cell storage memory 201 is configured by connecting fixed-length storage areas (see FIG. 4). As shown in FIG. 4, each fixed-length storage area has an area for storing a header (4 bytes) and a payload (48 bytes) of an ATM cell and link information to the next area (the head of the next storage area). (A pointer indicating an address: 4 bytes).

The storage area not currently used is the free list. By allocating a storage area as needed from the free list, a storage area can be added to the reception buffer. As for the transmission buffer, an area in which fixed-length storage areas are connected is similarly used.

As shown in FIG. 4, each CID has three pointers “Top”, “Send”,
"Tail", "flag", "CMAX", "IC
"RC", "OCRC", and "reserved".
“Top”, “Send”, “Tail”, “fla”
g "," CMAX "," ICRC "," OCRC ",
"Reserved" is assigned a 4-byte memory.

The pointer "Top" holds a value indicating the head address of the head storage area of the reception buffer. The pointer “Send” indicates the AT last transferred to the upper header processing unit 300 in the storage area on the reception buffer.
A value indicating the start address of the storage area holding the M cell is held. The pointer “Tail” holds a value indicating the start address of the last storage area of the reception buffer.

The input CRC calculation circuit 140 calculates a CRC for a packet received from the transmission line. In the case of VC multiplexing, an ATM cell of a packet belonging to another VC appears in the middle of the packet, so it is necessary to interrupt the CRC calculation in the middle. The intermediate result of the calculation in that case is held in the corresponding CID “ICRC” (see FIG. 4) (FIG. 5).
S14).

When the input of one packet is completed, the input CRC calculation circuit 140 compares the result of the CRC calculation with the value of the trailer of the AAL5 CPCS-PDU. If the result of the comparison does not match, an error relating to the input packet is detected (S15, S16 in FIG. 5). This input C
The information of the RC error is, for example, “fla” of the corresponding CID.
g "is reflected in the content of one bit.

When a certain condition is satisfied, the VC separation module 130 transfers one or a plurality of ATM cells received by the ATM framer 110 to the ATM cell storage memory 201. The actual transfer is performed by DMA under the control of the DMA control circuit 120. This transfer process corresponds to step S in FIG.
17 corresponds. Details of the processing are as shown in FIG.

In step S60, it is determined whether or not the current cell (the last received ATM cell) is the last cell. P
The least significant bit of the T value "user-user iden"
If the "tification" is 1, the AAL5 CPCS
-The last cell of the PDU, otherwise not the last cell. If the last cell is detected in step S60, the process proceeds to step S61, where the communication signal input / output unit 100
Irrespective of the number of cells stored in the cell reception queue of the ATM cell storage memory 2 by DMA transfer.
Transfer to 01.

In step S62, the VC is compared between the current cell and the cells stored in the cell reception queue of the communication signal input / output unit 100 so far. If the VCs do not match, the flow advances to step S63 to transfer all cells stored in the cell reception queue to the ATM cell storage memory 201 by DMA transfer. VC in step S62
If they match, the process proceeds to step S64 to accumulate the current cell in the cell reception queue. Also, in the next step S6
In step 5, the number of cells stored in the cell reception queue is compared with a transfer designation value (a constant of 2 or more in this example).

When the number of stored cells is equal to or larger than the designated transfer value,
In step S66, all cells stored in the cell reception queue are transferred to the ATM cell storage memory 2 by DMA transfer.
Transfer to 01. By the processing shown in FIG.
In the case of continuously transferring cells, the number of repetitions of the processing required for initial setting such as the transfer address and the number of transfer bytes in the case of performing DMA transfer is reduced, so that the transfer delay time is reduced.

Before performing the transfer in step S17 of FIG. 5, it is necessary to secure the transfer destination memory from the free list on the ATM cell storage memory 201. When the storage area is secured from the free list, it is necessary to change the pointer indicating the position of the free list so as to reflect the decrease in the area of the free list due to the secured area.

If the transfer of the ATM cell has been performed at step S17, the storage area of the transfer destination is set at AT18 at step S18.
It is connected after the reception buffer on the M cell storage memory 201. That is, the head address value of the storage area of the transfer destination is written in the link information of the last storage area of the reception buffer before the connection, and the head address of the last storage area of the connection is written in the CID pointer “Tail”. A value is written, and null (NULL: a numerical value that does not indicate a meaningful address) is written in the link information of the last linked storage area to indicate the end.

A specific example will be described assuming the example shown in FIG. In FIG. 11, fixed-length storage areas M connected to each other are shown.
11, M12, M13, and M14 exist as free lists, and are fixed-length storage areas M21 and M2 connected to each other.
2, M23 and M24 are allocated as reception buffers. In the state of FIG. 11, the storage area M1
1 is located at the head of the free list and its head address T1
1 is the head address of the free list. Also,
The storage area M21 is located at the head of the reception buffer, and its head address T21 is the head address of the reception buffer.
Further, the storage area M24 is located at the end of the reception buffer. CID pointers "Top", "Sen"
"d" and "Tail" are the start address T21 of the storage area M21, the start address T22 of the storage area M22, respectively.
The start address T24 of the storage area M24 is indicated.
Note that null is held in the link information of the last storage areas M24 and M14.

When transferring an ATM cell in step S17, an area is secured from the free list. For example, 1
When securing an area for storing one ATM cell, the first storage area M11 of the free list is secured.
With the reservation of the storage area M11, the head address of the free list is changed to T12. Secured storage area M11
When the ATM cell is transferred to the end of the receiving buffer, it is connected to the end of the receiving buffer. That is, the head address T11 of the storage area M11 is written as the link information of the storage area M24, and null is written in the link information of the storage area M11. The CID pointer "Tail" has a storage area M11.
Is written.

The number of cells stored in the ATM cell storage memory 201 is determined by the ATM cell information extraction module 202.
Managed by That is, the ATM cell information extraction module 202 compares the number of cells stored in the ATM cell storage memory 201 for each CID with the constant "CMAX" held in the CID (S19 in FIG. 5). In this example, 2 is assigned to the constant “CMAX”.

When the number of cells stored in the ATM cell storage memory 201 becomes equal to or greater than the constant "CMAX", the process proceeds to step S2.
0 and S21 are executed. In step S20, the CMAX ATs are transmitted from the ATM cell storage memory 201 to the upper header storage memory 301 using the DMA control circuit 220.
The payload of the M cell is DMA-transferred. When the cell is transferred to the upper header storage memory 301, the CID pointer "S" is used to enable the discrimination between the transferred cell and the non-transferred cell on the ATM cell storage memory 201.
"end" is changed to indicate the head position of the last cell to which the "end" has been transferred.

For example, when two ATM cells are transferred from the head of the reception buffer in the example shown in FIG.
The CID “Send” is rewritten so as to indicate the start address T22 of the second storage area M22 of the reception buffer. As shown in FIG.
When there are a plurality of CIDs, the transfer destination upper header processing unit 300 is switched for each VC or CID. Thereby, it becomes possible to process different packets in parallel by the plurality of upper header processing units 300.

In step S21, the CID information corresponding to the cell transferred in step S20 is transferred from the ATM cell information extraction module 202 to the upper header information extraction module 302, for example, in the form of a control command, and information to be processed is stored. Notify that was transferred.

Since the size of each CID is fixed (32 bytes), if the start address of the reception management table is CIDTOP, the start address Ax of the Nth CID is set.
Can be obtained from the following equation. Ax = (CIDTOP) + (N−1) × 32 By the processing of steps S19 to S21 shown in FIG. 5, two (CMAX) ATM cells are
When the data is stored in the M cell storage memory 201, two (C
MAX) ATM cells are continuously transferred from the ATM cell storage memory 201 to the upper header storage memory 301.
Immediately thereafter, the upper header information extraction module 302 can start processing the packet.

That is, when the IP and TCP protocols are adopted, in most cases, one AAL5 CPCS is used.
-In the first two ATM cells constituting the PDU,
Due to the fact that the information of the P and TCP protocols is included, the IP and TCP protocols are not considered when the first two ATM cells arrive without waiting for the arrival of all the cells constituting one packet. The upper header processing unit 300 can start processing such as information extraction.

The value of the CID constant "CMAX" may be 3 or more, but is preferably set to 2. Each upper header processing unit 30
At 0, the upper header information extraction module 302 operates as shown in FIG. In step S51, it is determined whether or not the information of the processing target cell (payload only) exists in the upper header storage memory 301. The ATM cell information extraction module 202 of the ATM cell processing unit 200 notifies the completion of the transfer that the upper header information extraction module 3
In the case where the notification is made to No. 02, whether or not the notification has been received by the upper header information extraction module 302 may be identified.

In step S52, the information of the payload of a plurality of cells in the upper header storage memory 301 is processed, and
The TCP / IP header information and the payload information accompanying it are extracted from the payload. Step S53
Then, the information extracted in step S52 is output to an external device via the information input / output circuit 303. Also, the information of the payload on the upper header storage memory 301 can be rewritten by information input from the outside via the information input / output circuit 303.

When the processing of the upper header information extraction module 302 for one packet is completed, the process proceeds from step S54 to S55. In step S55, a termination instruction indicating that the processing of the upper header processing unit 300 has been completed is sent from the upper header information extraction module 302 to the A.
In addition to notifying the ATM cell information extraction module 202 of the TM cell processing unit 200, the CID of the processed packet is notified to the ATM cell information extraction module 202.

In order to send the processed ATM cell to the transmission line again, the ATM cell processing unit 200
The M cell information extraction module 202 executes the processing shown in FIG. Hereinafter, the processing illustrated in FIG. 8 will be described. In step S30, it is determined whether or not the processing of the upper header processing unit 300, which is the upper unit, has been completed. Actually, in step S55 shown in FIG.
Since the information is input to the cell information extraction module 202, it is determined whether or not the end instruction has been input.

In step S31, it is determined whether or not the information extraction processing of the ATM cell information extraction module 202 relating to the ATM cell in the ATM cell storage memory 201 has been completed. When the upper header processing unit 300 has completed the processing or when the ATM cell information extraction module 202 has completed the processing, the process proceeds to step S32. In step S32, it is determined whether or not the upper header processing unit 300 has modified the payload during the processing. If corrected, the process proceeds to step S33.

In step S33, a storage area for storing CMAX ATM cells is secured from the free list on the ATM cell storage memory 201, and the payload of the CMAX cells existing on the upper header storage memory 301 is stored. The data is transferred to the storage area secured on the ATM cell storage memory 201. Actually, the DMA control circuit 22
DMA transfer is continuously performed using 0.

In step S33, since only the payload is transferred, the cell header does not yet exist in the storage use area of the transfer destination. Therefore, in the next step S34,
The upper header information extraction module 302 uses the CID notified in step S55 of FIG.
The header of the cell is obtained from the reception buffer on the ATM cell storage memory 201, and copied to the storage area secured in step S33.

In step S35, the storage area secured in step S33 is linked to the end of the transmission buffer. That is, CMAX processed ATM cells are added to the storage area to be transmitted. In step S36, the remaining cells in the reception buffer are connected to the end of the transmission buffer. That is,
The storage area of (Y-CMAX) ATM cells excluding the CMAX ATM cells transferred to the upper header processing unit 30 from the Y ATM cells stored in the reception buffer is connected to the transmission buffer.

A specific example will be described with reference to FIG. In FIG. 12, fixed-length storage areas M connected to each other are shown.
11, M12, M13, and M14 exist as free lists, and are fixed-length storage areas M21 and M2 connected to each other.
2, M23 and M24 are allocated as reception buffers and are connected to each other in fixed-length storage areas M31 and M3.
2, M33 and M34 are allocated as transmission buffers.

In the state shown in FIG. 12, the storage area M11 is located at the head of the free list, and its head address T11 is the head address of the free list. Also, the storage area M21 is located at the head of the reception buffer, and the storage area M24
Is located at the end of the reception buffer. Similarly, the storage area M31 is located at the head of the transmission buffer, and the storage area M3
4 is located at the end of the transmission buffer. Note that null is held in the link information of the last storage areas M24, M34, and M14.

When step S33 is executed, for example, the first two storage areas M1 of the free list in FIG.
1 and M12 are secured, and a 2-cell payload transferred from the upper header processing unit 300 is written in them.
In this case, the value of the pointer indicating the position of the free list is changed so that the storage area M13 is at the head of the free list. A null is written in the link information of the last storage area M12.

When step S35 is executed, the storage areas M11 and M12 secured in the free list are linked to the last storage area M34 of the transmission buffer. That is,
The head address T11 of the storage area M11 is written in the link information of the storage area M34. In step S36, the receiving buffers after the third storage area M23, which have not been transferred to the upper header storage memory 301 among the receiving buffers, are connected to the end of the transmitting buffer. That is, assuming that the storage area M12 connected in the above processing is the last of the transmission buffer, the link information of the storage area M12 is included in the link information of the storage area M12.
23 is written as the top address T23.

If there is no cell received from the upper header processing unit 300, in step S36, all storage areas of the reception buffer of the CID for which processing has been completed are connected to the transmission buffer. If the transmission buffer changes due to the concatenation, a pointer (Send) indicating the head position of each of the head and tail storage areas of the transmission buffer.
-Top, Send-Tail) is also corrected. Similarly, when the area of the reception buffer changes, the CID pointers “Top” and “Tail” are corrected accordingly. When the reception buffer becomes empty, the contents of the pointers “Top”, “Send”, and “Tai1” are all null.

In step S37 of FIG. 8, each CID
The CRC of the packet on the transmission buffer
The calculation is performed for each cell using the recalculation module 204. However, CRC calculation is omitted for CIDs that have not been modified by the upper header processing unit 300. Since the transmission buffer is VC-multiplexed, the C of one entire packet is
VC is switched before RC result is obtained, and C
The RC calculation process may be interrupted. Therefore, the intermediate result of the calculation is held in the corresponding CID “OCRC”.

In step S38, it is determined whether or not the CRC recalculation (S37) of the last cell has been completed for each CID. If the processing has been completed, the process proceeds to step S39. In step S39, the presence / absence of a CRC error detected at the time of CRC calculation at the time of input (see S16 in FIG. 5) is identified by referring to the “flag” of the corresponding CID. CR on input
If no C error is detected, step S40
To change the CRC value of the cell to the CRC value recalculated in step S37. If a CRC error is detected at the time of input, the process proceeds to step S41.

In step S41, some bits of the CRC obtained by the recalculation are inverted and errors are inserted therein. Then, the CRC value into which the error has been inserted is written to the cell being processed as a new CRC value. Step S
At 42, the data of the processed ATM cell is sequentially transferred to the ATM framer 110 of the communication signal input / output unit 100 from the head position of the transmission buffer.

Since the storage area in the transmission buffer holding the transmitted cell becomes unnecessary by this transfer, the unnecessary storage area is released and linked to the free list in the next step S43. For example, when the ATM cell in the storage area M31 of the transmission buffer shown in FIG. 12 is transferred, the value of the pointer indicating the start address of the transmission buffer is changed to the start address T32 of the storage area M32, and the last storage of the free list is performed. The head address T31 of the storage area M31 is written in the link information of the area M14, and the storage area M3
A null is written in the link information of No. 1. When the last cell has been transferred, null is written to the pointers indicating the start and end positions of the transmission buffer.

Each AT transferred to the ATM framer 110
The signals of the M cells are sequentially transmitted to the transmission path. Note that each V
When all the cells in the transmission buffer of the ATM cell storage memory 201 for C have been transferred to the ATM framer 110, the state of the corresponding VC in the VCI management memory 203 is changed to indicate the end of processing, and thereafter, The received ATM cells up to the last cell are output to the return transmission path in the communication signal input / output unit 100.

When transmission to the transmission line up to the last cell of one CID is completed, the CID is set as an unused CID,
Next, use the received VC. By such processing, each VC is multiplexed from the received VC multiplexed ATM stream.
Can be managed on a cell-by-cell basis for each packet, and packet information can be easily transferred to the upper header processing unit 300 as well.

As described above, the data received by the ATM framer 110 from the transmission line via the predetermined reception port is:
It is sequentially stored in the ATM framer 110. The VC separation module 130 determines the cell based on the information received by the ATM framer 110 and converts the cell as it is into the ATM framer 11.
0 or to transfer to the ATM cell processing unit 200 via the DMA control circuit 120. At this time, it is determined whether or not there is an error in the input packet based on the CRC value calculated by the input CRC calculation circuit 140.

Since the communication signal input / output unit 100 needs to separate cells for each VC, as shown in FIG. 9, cells C1 (1), C2 (2), C3 (3), C4 having different VCs from each other.
When (4) is sequentially received (assuming that the number in parentheses indicates VC), the ATM framer 11 is received in units of one cell.
From 0, transfer to the ATM cell storage memory 201 is performed. However, when cells of the same VC are continuous as shown in FIG. 10, cells are separated for each VC, and a plurality of cells are transferred from the ATM framer 110 to the ATM cell storage memory 201 by continuous DMA processing. .

When a plurality of cells are continuously transferred as shown in FIG. 10, the transfer can be completed in a short time because the DMA initialization delay time between cells can be omitted. The number of higher-order header processing units 300 connected to the ATM cell processing unit 200 may be changed according to the required processing speed or the like, and may be one or two or more.

The process of allocating the upper header processing unit 300 to be used from among a plurality of CIDs for each CID is performed by ATM.
This may be performed by the cell information extraction module 202. Various methods can be considered as an allocation method, such as allocation according to the lower bits of the CID. However, it is preferable that the allocation is performed so that a plurality of upper header processing units 300 operate simultaneously as much as possible.

In this example, the ATM cell processing unit 20
ATM to transfer from 0 to upper header processing unit 300
The number of cell payloads is fixed by CMAX. However, for example, when the upper header information extraction module 302 of the upper header processing unit 300 determines that the information of the cell of CMAX or more is necessary, a change may be made to transfer the payload of the further ATM cell.

When a control command for transferring an additional cell is issued from the upper header processing unit 300, the value of CMAX in the CID of the ATM cell processing unit 200 is automatically changed by the added amount. It may be controlled. In this example, the upper header processing unit 3
00 is used to extract information in packet units. However, a control mode in which information is extracted only by the ATM cell processing unit 200 without using the upper header processing unit 300 is added. May be changed.

In that case, the communication signal input / output unit 1
00 receives the received ATM cell in the ATM cell processing unit 2
00, and the ATM cells processed by the ATM cell processing unit 200 may be transferred to the communication signal input / output unit 100. Also in this case, ATM
When a correction is made in the cell processing unit 200, it is desirable to recalculate the CRC.

(Second Embodiment) Another embodiment of the protocol processing apparatus of the present invention will be described with reference to FIG. This embodiment corresponds to claim 6. FIG.
FIG. 3 is a block diagram showing hardware of the protocol processing device of this embodiment. This embodiment is a modification of the first embodiment. 13, elements corresponding to those in FIG. 2 are denoted by the same reference numerals.

In this embodiment, the plurality of sets of buses in claim 6 correspond to the local buses 190 and 270. Only parts different from the first embodiment will be described below. FIG.
Referring to FIG. 1, a local bus 190 is provided inside the communication signal input / output unit 100, and the ATM framer 1
10, DMA control circuit 120, VC separation module 13
0, the input CRC calculation circuit 140 is connected to the local bus 190. The communication signal input / output unit 100
Is provided with a bus selection circuit 180. The ATM cell processing unit 200 includes a bus selection circuit 290.

The bus selection circuit 180 selects one of the local bus 190 inside the communication signal input / output unit 100 and the local bus 270 inside the ATM cell processing unit 200, and connects it to the input of the ATM framer 110. The selection state of the bus selection circuit 180 is controlled by a signal SEL (1) output from the VC separation module 130.

The bus selection circuit 290 selects one of the local bus 270 inside the ATM cell processing unit 200 and the local bus 190 inside the communication signal input / output unit 100, and connects it to the input of the data memory 210. The selection state of the bus selection circuit 290 is controlled by a signal SEL (2) output from the microprocessor 230.

The DMA control circuit 120 and the VC separation module 130 in the communication signal input / output unit 100 are connected to two sets of local buses 190 and 270, respectively. The microprocessor 230 in the ATM cell processing unit 200 has two sets of local buses 190,
270 respectively. In the apparatus shown in FIG. 13, two sets of local buses 19 are used for data transfer between the ATM framer 110 of the communication signal input / output unit 100 and the data memory 210 of the ATM cell processing unit 200.
Both 0 and 270 can be used.

In the example of FIG. 13, when data is transferred from the ATM framer 110 to the data memory 210, the transfer is performed via the local bus 190 and the bus selection circuit 290. Also, the data memory 210 stores the ATM
When data is transferred to the framer 110, the data is transferred via the local bus 270 and the bus selection circuit 180.

The local bus 190 is also used for internal processing of the communication signal input / output unit 100, and the local bus 270 is also used for internal processing of the ATM cell processing unit 200. When data transfer is not performed between the ATM framer 110 and the data memory 210, the bus selection circuit 180 selects the local bus 190 by the signal SEL (1) output from the VC separation module 130. Also, the signal S output from the microprocessor 230
The EL (2) causes the bus selection circuit 290 to switch to the local bus 2
Select 70. In this state, the local bus 190 is used for processing inside the communication signal input / output unit 100, and the local bus 270 is used for the ATM cell processing unit 20.
0 is used for internal processing.

The communication signal input / output unit 100 sends the ATM
When transferring data to the cell processing unit 200, the VC separation module 130 in the communication signal input / output unit 100 generates a transfer instruction to the DMA control circuit 120. In this case, the DMA control circuit 120 sends the ATM cell processing unit 20 via the local bus 190.
0 sends an instruction to the microprocessor 230 inside.

This instruction causes the microprocessor 23
0 outputs the signal SEL (2), and the bus selection circuit 290 selects the local bus 190. Thereafter, data transfer is performed such that the data read from the ATM framer 110 is written into the data memory 210 under the control of the DMA control circuit 120. When data is transferred from the ATM cell processing unit 200 to the communication signal input / output unit 100, the ATM cell processing unit 20
0, the microprocessor 230 in the local bus 19
0, a transfer instruction is given to the DMA control circuit 120.

In this case, the DMA control circuit 120 controls the bus selection circuit 180 via the local bus 190 to select a signal on the local bus 270. after,
The data memory 21 is controlled by the DMA control circuit 120.
Data transfer is performed so that data read from 0 is written to the ATM framer 110. (Third Embodiment) Another embodiment of the protocol processing apparatus of the present invention will be described with reference to FIG. This embodiment corresponds to claim 6.

FIG. 14 is a block diagram showing hardware of the protocol processing apparatus of this embodiment. This embodiment is a modification of the first embodiment. In FIG. 14, FIG.
Elements corresponding to are denoted by the same reference numerals.

In this embodiment, the plural sets of buses in claim 6 correspond to the C-PCI buses 391 and 392. Only parts different from the first embodiment will be described below. FIG.
In the example of No. 4, the ATM cell processing unit 200 has two C-PCI bus interfaces 280 and 285 for connecting to the two C-PCI buses 391 and 392, respectively. Also, two C-PCI buses 391 and 3
Two C-PCI bus interfaces 380 and 385 are provided in each higher-level header processing unit 300 to connect to each of the upper-level header processing units 300 and 92.

The data memory 210 and the microprocessor 230 of the ATM cell processing unit 200 are connected to two C-PCI bus interfaces 280 and 285, respectively. C-PCI bus interface 28
0 is connected to the C-PCI bus 391,
The bus interface 285 is connected to the C-PCI bus 392.

The data memory 310 and the microprocessor 330 of each upper header processing unit 300 are connected to two C-PCI bus interfaces 380 and 385, respectively. The C-PCI bus interface 380 is connected to the C-PCI bus 392,
The PCI bus interface 385 is connected to the C-PCI bus 39.
Connected to 1.

Therefore, between the ATM cell processing unit 200 and each upper header processing unit 300, two sets of C
-Data can be transferred using the PCI buses 391 and 392 simultaneously. In the example of FIG. 14, the data (cell payload) in the direction from the ATM cell processing unit 200 to the upper header processing unit 300 is transferred using the C-PCI bus 391, and the upper header processing unit 300 transfers the data to the upper cell processing unit 200. For data (cell payload) transfer in the direction of
The CI bus 392 is used.

For this reason, the ATM cell processing unit 200
, And the data transfer in the direction from the upper header processing unit 300 to the ATM cell processing unit 200 can be performed at the same time. In the direction from the ATM cell processing unit 200 to the upper header processing unit 300,
When transferring the payload, the ATM cell processing unit 2
00 of the DMA control circuit 22
0 is given a transfer instruction.

In this case, the DMA control circuit 220 outputs the data (cell payload) read from the data memory 210 to the C-PCI bus interface 280. This data is stored in the C-PCI bus interface 28.
From 0, the data is input to the C-PCI bus interface 385 of any of the upper header processing units 300 through the C-PCI bus 391, and is written to the data memory 310.

When transferring a cell payload in a direction from each upper header processing unit 300 to the ATM cell processing unit 200, first, the microprocessor 330 of the upper header processing unit 300 to be transmitted transmits a DMA.
A transfer instruction is given to the control circuit 320. In this case, DMA
The control circuit 320 outputs the data (cell payload) read from the data memory 310 to the C-PCI bus interface 380. This data is input from the C-PCI bus interface 380 to the C-PCI bus interface 285 of the ATM cell processing unit 200 through the C-PCI bus 392, and is stored in the data memory 210.
Is written to.

(Fourth Embodiment) Another embodiment of the protocol processing apparatus of the present invention will be described with reference to FIGS. This embodiment corresponds to claim 6. FIG. 15 is a block diagram showing hardware of the protocol processing device of this embodiment. FIG. 16 is a time chart showing an example of data transfer timing. This embodiment is a modification of the first embodiment. 15, elements corresponding to those in FIG. 2 are denoted by the same reference numerals.

In this embodiment, the plural sets of buses in claim 6 correspond to the buses 501, 502 and 503. Only parts different from the first embodiment will be described below. FIG.
5, in this example, three sets of buses 501, 50
2,503 are provided. The communication signal input / output unit 100, the ATM cell processing unit 200, and the upper header processing units 300 (1), 300 (2), 300 (3)
All are commonly connected to each of the three sets of buses 501, 502, and 503.

That is, the communication signal input / output unit 100,
Each of the ATM cell processing unit 200 and the upper header processing units 300 (1), 300 (2), and 300 (3)
A set of buses 501, 502, and 503 can be shared, and the buses 501, 502, and 503 are separated from each other in terms of timing used by each unit according to a predetermined schedule or the like, so that data can be smoothly transferred between units. Transfer can be performed.

In the example of FIG. 15, the communication between the units is [(α) → (β)], [(β) → (α)], [(β) →
(Γ1)], [(β) → (γ2)], [(β) → (γ
3)], [(γ1) → (β)], [(γ2) →
(Β)] and [(γ3) → (β)].
The order of the data processing flow is (α) → (β) → (γ
1 or γ2 or γ3) → (β) → (α).

An example of actual data transfer between units will be described with reference to FIG. In the example of FIG. 16, the communication signal input / output unit 100 sends the ATM cell processing unit 2
00 is transferred three times, and the three sets of data output from the ATM cell processing unit 200 are transferred to three upper header processing units 300 (1), 300 (2), and 300.
It is assumed that each process is performed in (3).

In FIG. 16A, three buses 5
01, 502, and 503 are assumed to be used, and in FIG. 16B, a case is assumed in which only two sets of buses 501 and 502 are used. In (a) of FIG. 16, [(α) → (β)] and [(β) → (γ) using the bus 501.
1)], [(γ1) → (β)] and [(β) → (α)] are sequentially transferred, and [(α) → (β)], [(β ) → (γ2)], [(γ
2) → (β)], [(β) → (α)] are sequentially transferred, and using the bus 502, [(α) → (β)],
[(Β) → (γ3)], [(γ3) → (β)],
[(Β) → (α)] data transfer is performed sequentially.

Also, in FIG. 16B, using the bus 501, [(α) → (β)], [(β) → (γ1)],
[(Β) → (γ3)], [(γ1) → (β)], [(γ
3) → (β)], [(β) → (α)] are sequentially transferred, and using the bus 502, [(α) → (β)],
[(Α) → (β)], [(β) → (γ2)], [(γ
2) → (β)], [(β) → (α)], [(β) →
(Α)] is sequentially performed.

As shown in FIG. 16, there is a slight difference in the processing capacity depending on the number of buses that can be used simultaneously, but in any case, as shown in FIG. By using a common bus, data can be efficiently processed.
In addition, by sharing a plurality of buses with all units, all necessary data transfer can be realized with a minimum number of buses. Furthermore, as shown in FIG. 15, all buses are connected to all units (100, 200, 300 (1), 30).
0 (2) and 300 (3)), there is no restriction on the arrangement of each unit.

For example, the communication signal input / output unit 100,
Each of the ATM cell processing unit 200 and the upper header processing units 300 (1), 300 (2), 300 (3)) is connected to three sets of buses 301, 302,
When connecting to the unit 303, each unit may be connected to any connector, and the positions where a plurality of units are arranged may be interchanged.

If a bus that can be used in common between units is not used, the protocol processing device of FIG.
As shown in FIG. 7, the connection and arrangement between the units must be determined in consideration of the data processing procedure. Also in this embodiment, the communication signal input / output unit 100, the ATM cell processing unit 200, the upper header processing unit 300
(1), 300 (2), and 300 (3)) are implemented by mounting different programs on common hardware. Therefore, the connection and arrangement between the units can be freely changed.

[0123]

As described above, according to the protocol processing apparatus of the present invention, the communication signal input / output means, the ATM cell processing means, and the upper header processing means which operate independently of each other can perform the pipeline processing. Therefore, the processing can be sped up. According to the ATM cell storing method of the present invention,
When receiving a VC multiplexed stream, it is not necessary to allocate a memory area for each VC in advance, so that there is no useless area and a memory area can be used efficiently.

Further, when providing a plurality of sets of communication paths such as buses that can be used for data transfer between a plurality of units, data transfer can be performed more efficiently between the units and data can be processed efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a functional configuration of a protocol processing device according to a first embodiment.

FIG. 2 is a block diagram illustrating hardware of a protocol processing device according to the first embodiment.

FIG. 3 is a memory map showing a configuration of a storage area on an ATM cell storage memory.

FIG. 4 is a memory map showing a configuration of a storage area for reception.

FIG. 5 shows a communication signal input / output unit and an AT at the time of cell reception.
5 is a flowchart illustrating an operation of the M cell processing unit.

FIG. 6 is a flowchart showing the contents of a multi-cell DMA transfer.

FIG. 7 is a flowchart showing the operation of the upper header processing unit.

FIG. 8 is a flowchart showing a transmission process of the ATM cell processing unit.

FIG. 9 is a time chart showing the operation of the communication signal input / output unit when the VC of each cell is different.

FIG. 10 is a time chart showing the operation of the communication signal input / output unit when cells of the same VC are continuous.

FIG. 11 shows a configuration of a storage area on an ATM cell storage memory.

FIG. 12 shows a configuration of a storage area on an ATM cell storage memory.

FIG. 13 is a block diagram illustrating hardware of a protocol processing device according to the second embodiment.

FIG. 14 is a block diagram illustrating hardware of a protocol processing device according to a third embodiment;

FIG. 15 is a block diagram illustrating hardware of a protocol processing device according to a fourth embodiment;

FIG. 16 is a time chart showing an example of data transfer timing.

FIG. 17 is a block diagram illustrating a connection and arrangement example of each unit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 communication signal input / output unit 110 ATM framer 120 DMA control circuit 130 VC separation module 140 input CRC calculation circuit 180,290 bus selection circuit 190 local bus 200 ATM cell processing unit 201 ATM cell storage memory 202 ATM cell information extraction module 203 VCI management Memory 204 CRC recalculation module 205 Information input / output circuit 210 Data memory 220 DMA control circuit 230 Microprocessor 240 Program memory 250 FPGA 260 Ethernet interface 270 Local bus 280,285 C-PCI bus interface 300 Upper header processing unit 301 Upper header storage Memory 302 Upper header information extraction module 303 Information input / output circuit 310 For data Mori 320 DMA controller 330 microprocessor 340 program memory 350 FPGA 360 Ethernet interface 370 local bus 380,385 C-PCI bus interface 391, 392 C-PCI bus 501, 502, 503 bus

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Mitsuo Teramoto 2-3-1 Otemachi, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Ichira Matsuhiro Otemachi-2, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Co., Ltd. (72) Inventor Toshiaki Miyazaki 2-3-1, Otemachi, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Co., Ltd.

Claims (8)

[Claims] 1. An ATM framer connected to a transmission line capable of forming a plurality of virtual channels, for inputting and outputting ATM cells to and from the transmission line, and an ATM cell input by the ATM framer from the transmission line to a virtual channel. A VC separation module for separating ATM cells from each other, an ATM cell storage memory for storing ATM cells input from the transmission line by the ATM framer, and ATM cell information for extracting information from the ATM cells transferred to the ATM cell storage memory An extraction module; an upper header storage memory for storing at least payload information of the ATM cells input from the transmission line by the ATM framer; and an ATM cell information extraction module from the ATM cells transferred to the upper header storage memory. For protocols at a higher layer than the layer to be processed A communication signal input / output unit including the ATM framer and the VC separation module; and an ATM cell processing unit including the ATM cell storage memory and the ATM cell information extraction module. Means and an upper header processing means provided with the upper header storage memory and the upper header information extraction module are connected in series and connected to each other.
A protocol processing device comprising a cell processing unit and a control unit that operates independently of each other in a high-order header processing unit. 2. The protocol processing apparatus according to claim 1, wherein the ATM cell received by the ATM framer is transmitted to the ATM cell.
When transferring data to the TM cell storage memory, a predetermined number of ATM cells are stored in the ATM framer until a predetermined number of cells are stored in the ATM framer, unless the virtual channel of the input ATM cell changes. Multiple A
A protocol processing device comprising a transfer control means for continuously transferring TM cells. 3. The protocol processing apparatus according to claim 1, wherein said plurality of upper header processing means are independent of each other.
The ATM cell processing means is connected to the ATM cell processing means, and the high-order header processing means of the transfer destination of the ATM cell is switched according to the difference of the virtual channel to which each ATM cell belongs to the ATM cell processing means. A protocol processing device wherein cells are processed in parallel by a plurality of upper header processing means. 4. The protocol processing apparatus according to claim 1, wherein the same hardware includes at least a processor for executing a program, a program memory, a direct memory access control circuit, a programmable gate array, a bus interface, and an internal bus. A protocol processing apparatus comprising different software, and each hardware is configured as the ATM cell processing means and the upper header processing means. 5. The protocol processing device according to claim 1, wherein the ATM framer calculates CRC information of a packet for each virtual channel received from a transmission line by an AAL5 layer, and the upper header processing means. A second CRC calculating means for calculating the CRC information of the AAL5 layer for each packet for each virtual channel corrected by the processing of the above, and when at least the packet is corrected by the processing of the upper header processing means, the second CRC calculating means While correcting the ATM cell to be transmitted with the result calculated by the CRC calculating means,
CRC based on the calculation result of the first CRC calculation means
A protocol processing apparatus, further comprising: a CRC control unit that, when an error is detected, reflects the CRC error information in an ATM cell to be transmitted. 6. The protocol processing device according to claim 4, wherein said plurality of identical hardware are connected to each other using a plurality of buses. 7. An ATM cell storage method for separating ATM cells received from a transmission path capable of forming a plurality of virtual channels for each virtual channel and storing the separated ATM cells in a storage device, comprising: a header, a payload, and a next storage. Utilizing a free list formed by sequentially logically connecting unused storage areas of fixed size for holding link information to areas, storing at least ATM cells for each virtual channel of received ATM cells. Holding the reception management data including the information indicating the head position of the area, and sequentially securing each storage area from the free list for each received ATM cell, and storing each ATM cell in the secured storage area. ATM linking the secured storage area to the end of a reception buffer holding each ATM cell received so far. Le storage method. 8. The ATM cell storage method according to claim 6, wherein a first storage area for storing a plurality of ATM cells is secured from the free list, and the first storage area stores the processed ATM cells in the first storage area. A payload is stored, and a header of an ATM cell of the same virtual channel stored in the reception buffer is written to the first storage area, and the header of the ATM cell to be transmitted is stored at the end of the transmission buffer holding the ATM cell to be transmitted. And connecting the remaining data following the data held in the first storage area among the data of the same virtual channel stored in the reception buffer to the first storage area. Characteristic ATM cell storage method.