JP2001237261A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device which can deal with bump electrodes of fine pitch, and a method for manufacturing the same. SOLUTION: The semiconductor device 100 comprises a pad member 12 having an electrical connection region 12a, an insulation layer 13 formed on the pad member 12, an underlying metal layer 14 formed on the pad member 12, and a bump electrode 15 provided on the underlying metal layer 14. The angle θ defined by the side face 15b of the bump electrode 15 and the surface of the pad member 12 is θ>=80 deg..

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device which is excellent in reliability and can cope with a narrow pitch of bump electrodes and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the increase in the degree of integration of integrated circuits and the reduction in the size of semiconductor chips, there is a demand for a mounting technique capable of supporting terminal connection at a fine pitch. As a mounting technology that can easily respond to this request, there is TAB (Tape Automated Bonding) mounting used for TCP (Tape Carrier Package) and the like.
Other mounting techniques include anisotropic conductive films, ie, A
CO using CF (Anisotropic Conductive Film)
G (Chip On Glass), COF (Chip On Film or Fle)
xible) is known.

FIG. 6 is a cross-sectional view showing a configuration (bump electrode structure 650) of a bump electrode 65 provided on a pad member 62 in a general semiconductor device 610. In this bump electrode structure 650, a pad member 62 made of Al is formed on an insulating layer 61 formed on a semiconductor substrate (not shown). This pad member 62
It is electrically connected to an internal semiconductor element (not shown). The surface of the pad member 62 has an electrical connection region 62
is provided, and the electrical connection region 62a and the bump electrode 65 are electrically connected via the metal layer 64 for base.

A passivation layer 63 is formed on the insulating layer 61 and on the periphery of the pad member 62 as an insulating layer. That is, the passivation layer 63
Is formed so as to cover the insulating layer 61 and the periphery of the pad member 62, and the central part (electrical connection region 62a) of the pad member 62 is exposed. Pad member 62
A base metal layer 64 is formed thereon. The base metal layer 64 also serves as a plating metal layer, and has a laminated structure of a barrier metal layer 641 and a protective metal layer 651 for adhesion. A bump electrode 65 is formed on the base metal layer 64. The bump electrode 65 is formed by, for example, Au plating.

Next, a cross section showing an Au plating step in forming the bump electrode 65 shown in FIG. 6 is shown in FIG. The bump electrode 65 is formed by an Au electrolytic plating method. That is, the plating electrode needle 80 is brought into contact with the protective metal layer 651a for adhesion formed on the barrier metal layer 641a, and a current is applied. As a result, Au is deposited in the openings 71a provided in the positive resist layer 71. Subsequently, the resist layer 71 is removed to obtain a bump electrode 65. Using the bump electrode 65 as a mask, the barrier metal layer 641a and the protective metal layer 651a are etched, and the barrier metal layer 6 is removed.
Underlayer metal layer 64 including 41 and protective metal layer 651
Get. The bump electrode 65 obtained by the above steps is
The shape corresponds to the shape of the opening 71a of the resist layer 71.

It is generally known that a positive resist layer has a higher resolution than a negative resist. However, a positive resist layer is formed by forming a resist layer (not shown) and then forming a predetermined pattern using an exposure mask (not shown) when light is applied between the applied resist layer and the mask. Due to interference, the upper part of the resist layer (the side closer to the exposure mask) is lower (the side closer to the pad member 62).
More sensitive to light. Therefore, the opening 71a of the positive resist layer 71 obtained by the exposure is
The opening area becomes larger as approaching the surface of No. 1.

Further, the bump electrode 65 shown in FIG.
As shown in FIG.
It is formed by laminating an Au plating layer to a height substantially equal to the thickness of the resist layer 71 thereon. As described above, the bump electrode 6 obtained by the process shown in FIG.
Since the shape of the bump electrode 5 corresponds to the shape of the opening 71a, the shape of the obtained bump electrode 65 has a small cross-sectional area at the lower portion (the side close to the pad member 62) as shown in FIG. The cross-sectional area increases as the distance increases. Therefore, the cross-sectional area of the upper part of the bump electrode 65 is considerably larger than the cross-sectional area of the lower part. As the pitch of the bump electrodes 65 having such a shape is reduced, the risk that adjacent bump electrodes 65 contact each other and cause a short circuit increases.

A semiconductor device 62 in which a bump electrode structure 650 including a bump electrode 65 shown in FIG.
0 is shown in FIG. When manufacturing the semiconductor device 620 shown in FIG. 8, the leads 81 formed on a tape (not shown) are thermocompression-bonded on the bump electrodes 65. In FIG. 8, the lead 81 is made of a Cu thin film layer and an Sn plating layer (both not shown) covering the Cu thin film layer, and the bump electrode 65 is made of an Au plating layer as described above. Therefore, in the thermocompression bonding step, the bump electrode 65 made of Au and the Sn plating layer forming the lead 81 are pressed, and eutectic of Au and Sn is achieved. In this step, the upper portion of the bump electrode 65 is further deformed by the load applied to the bump electrode 65 when the lead 81 is pressed. As a result, the cross-sectional area of the upper part of the bump electrode 65 is further increased by the thermocompression bonding step, and the possibility that the adjacent bump electrodes 65 contact each other to cause a short circuit is further increased.

FIG. 9 shows a cross section of a semiconductor device 630 in which the bump electrode structure 650 including the bump electrode 65 shown in FIG. 6 is applied to COG mounting by ACF. In the semiconductor device 630 illustrated in FIG. 9, for example, an organic material such as glass epoxy,
Alternatively, the terminal electrodes 91 arranged on a mounting circuit board (not shown) made of a glass substrate on which signal input terminals of the liquid crystal display device are formed, and the bump electrodes 65 are joined. That is, the bump electrodes 65 are electrically connected to the opposing terminal electrodes 91 via the ACF 92, respectively.

In the ACF 92, conductive particles 93 having a diameter of about 5 μm are dispersed in a film-like epoxy resin 94. In the semiconductor device 630, the conductive particles 93 are interposed between the terminal electrode 91 and the bump electrode 65 through a pressurization / heating step using a crimping tool (not shown), and the bonding between the terminal electrode 91 and the bump electrode 65 is performed. When the gap of the portion 95 is equal to or smaller than the particle size of the conductive particles 93, a conductive state is obtained. There is no conduction between the adjacent terminal electrodes 91 and between the bump electrodes 65 because they are not in contact with the conductive particles 93.

However, through the above-described pressurizing / heating step, the upper portion of the bump electrode 65 is further deformed by the load applied to the bump electrode 65. As a result, the pressurizing / heating step further increases the cross-sectional area of the upper portion of the bump electrode 65, so that the possibility that the adjacent bump electrodes 65 come into contact with each other to cause a short circuit further increases. In this case, since the ACF 92 is interposed between the adjacent bumps 65 and the conductive particles 93 are present in the ACF 92, the adjacent bumps 65 may contact each other via the conductive particles 93 and cause a short circuit. There is. Further, in this case, the ACF 92 does not spread in the vicinity of the junction between the bump electrode 65 and the passivation layer 63, and the bubbles 96 remain in such portions, and cracks may occur in the bump electrodes 65 due to the stress of the vapor generated by the bubbles 96. There is. Such a situation can occur similarly when the bump electrode 65 shown in FIG. 6 is applied to COF (Chip On Film or Flexible).

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having high reliability and capable of coping with a narrow pitch of bump electrodes, and a method of manufacturing the same.

[0013]

(First Semiconductor Device) A semiconductor device according to the present invention comprises a pad member formed on a base and having an electrical connection region, and an insulating member formed around the pad member. A layer, a base metal layer formed on the pad member, and a bump electrode provided on the base metal layer, and an angle between a side surface of the bump electrode and an upper surface of the pad member. θ is θ ≧ 80 °.

In the present invention, the electrical connection region is a region of the pad member which is not covered with the insulating layer, and is connected to the bump electrode on the upper surface of the pad member via the metal layer for the base. Part to do. Further, the base means at least a substrate on which a semiconductor element is formed and a wiring layer formed on the substrate.

The upper surface of the pad member refers to the surface of the pad member including the electrical connection region. Further, the angle between the side surface of the bump electrode and the surface of the pad member is, in other words, the surface of the pad member,
The angle formed by the direction in which the bump electrode extends upward from the base metal layer.

If θ is less than 80 °, when the bump electrode is joined to a joining member (for example, a lead or terminal electrode), the bump electrode is deformed and the adjacent bump electrodes come into contact with each other to cause a short circuit. Is more likely to do so.

On the other hand, according to the semiconductor device of the present invention, since θ ≧ 80 °, when the bump electrodes are joined to the joining member, the bump electrodes are deformed and the adjacent bump electrodes are joined to each other. Are not in contact with each other, which can effectively cope with the narrow pitch of the bump electrodes.

In the semiconductor device, the angle θ is 8
More preferably, 0 ° ≦ θ ≦ 105 °. The angle θ
Is 80 ° ≦ θ ≦ 105 °, so that the cross-sectional shape and the size of the upper and lower portions of the bump electrode do not greatly differ, so that when the bump electrode and the bonding member are bonded, the bump electrode Can be prevented from being deformed and adjacent bump electrodes contacting each other to cause a short circuit. Thus, it is possible to effectively cope with the narrow pitch of the bump electrodes.

Further, in the semiconductor device, it is further preferable that the angle θ is approximately 90 °. When the angle θ is approximately 90 °, the cross-sectional shape and size of the upper and lower portions of the bump electrode are substantially equal, so that a short circuit occurs when the bump electrode and the bonding member are bonded. Can be more reliably prevented. Thereby, it is possible to more effectively cope with a narrow pitch of the bump electrodes.

The bump electrode is made of a material containing gold as a main component, and has a surface roughness Ra (μm) of the bump electrode.
Is more preferably 0.1 ≦ Ra ≦ 0.4.
Details will be described in the section of a second semiconductor device described later.

(Second Semiconductor Device) A semiconductor device according to the present invention includes a pad member formed on a base and having an electrical connection region, an insulating layer formed on the pad member, and a pad member formed on the pad member. The bump electrode includes a formed base metal layer and a bump electrode provided on the base metal layer, and the bump electrode is made of a material containing gold as a main component, and has a surface roughness Ra ( μm) is 0.1 ≦ Ra ≦ 0.4.

Here, the roughness Ra of the surface of the bump electrode refers to an arithmetic average roughness, and an arbitrary point on the surface of the bump electrode with respect to a predetermined center line set. A value obtained by measuring a height difference (absolute value) from a reference at a point (measurement point) and dividing the sum of the height differences by the number of measurement points.

The surface roughness Ra of the bump electrode is 0.1
When it is less than the above, when the bump electrode and the joining member are joined, alignment may be difficult due to reflected light from the surface of the bump electrode. Further, in this case, for example, when the bump electrode and the bonding member are bonded by applying ACF, it becomes difficult to capture conductive particles on the surface of the bump electrode, and sufficient conductivity cannot be obtained. is there.

On the other hand, if the surface roughness Ra of the bump electrode exceeds 0.4, the area which effectively contributes to the bonding between the bump electrode and the bonding member is reduced, so that sufficient bonding strength cannot be secured. There are cases.

On the other hand, when the surface roughness Ra of the bump electrode is in the range of 0.1 to 0.4 μm, a good bonding state is ensured at the bonding portion between the bump electrode and the bonding member. Therefore, a sufficient bonding area can be obtained, so that a sufficient bonding strength can be secured at the bonding portion. Further, when the surface roughness Ra is within the range of 0.1 to 0.4 μm, light is scattered to some extent on the surface of the bump electrode. And the alignment when joining the bump electrode and the joining member is facilitated. Furthermore, when the bump electrode and the joining member are joined using, for example, an ACF, a conductive state is ensured between the bump electrode and the joining member because conductive particles are captured on the surface of the bump electrode. can do.

(Method of Manufacturing Semiconductor Device) In a method of manufacturing a semiconductor device according to the present invention, a step of forming a pad member in a predetermined region on a substrate, a step of covering an insulating layer so as to cover the pad member, By lithography, leaving the insulating layer in the peripheral portion on the pad member to expose an electrical connection region in the pad member, and depositing a base metal layer on the pad member and the insulating layer, Forming a resist layer having an opening on the base metal layer, arranging the opening on the pad member, and forming a metal plating layer on the base metal layer in the opening. Forming, forming a bump electrode made of the metal plating layer by removing the resist layer, and etching the base metal layer using the bump electrode as a mask. Wherein the step of packaging, and in the step of forming the metal plating layer, characterized in that the height of the metal plating layer to 2/3 or less of the height of the resist layer.

According to the method of manufacturing a semiconductor device of the present invention,
By adjusting the height of the metal plating layer deposited for the formation of the bump electrode to 2/3 or less of the height of the resist layer, the shape and the size of the cross section are almost equal from the top to the bottom. Can be easily formed. Therefore, a semiconductor device that can cope with the narrow pitch of the bump electrodes can be obtained by a simple method.

In this case, the step of forming the metal plating layer is a step of forming a gold plating layer. In the step of forming the gold plating layer, the plating temperature T (° C.) and the plating current density CD (A / dm ² ) Preferably has the relationship of the following formula (1).

CD ≦ 0.05 × T−2.0 Formula (1) The plating temperature T (° C.) and the plating current density CD (A / dm ² ) are defined based on the relationship of Formula (1). By performing the gold plating step, the surface roughness Ra of the bump electrode obtained by the gold plating step is set to 0.1 to 0.4 μm.
m. As a result, alignment with the joining member is easy, and a bump electrode having a good conduction state with the joining member can be obtained.

[0030]

FIG. 1 is a sectional view showing a semiconductor device 110 according to an embodiment of the present invention. In the semiconductor device 110, an insulating layer 11 is formed on a semiconductor substrate (not shown).
The pad member 12 is formed on 1. In the present embodiment, a case is shown in which pad member 12 contains Al as a main component. The pad member 12 is electrically connected to an internal semiconductor element (not shown). The pad member 12 has an electrical connection region 12a on the surface thereof, and the bump electrode 1 is formed in the electrical connection region 12a via the metal layer 14 for the base.
5 is electrically connected.

Further, on the insulating layer 11 and the pad member 12
Is formed on the periphery of the passivation layer 13 as an insulating layer.
Are formed. That is, the passivation layer 13 is formed so as to cover the insulating layer 11 and the peripheral portion of the pad member 12, and the central portion (the electrical connection region 12a) of the pad member 12 is exposed. Here, the type of the passivation layer 13 is not particularly limited. As the passivation layer 13, any structure can be used as long as it can reduce the impact at the time of bump mounting and contribute to the prevention of cracks. For example, a SiO ₂ layer, a SiN layer, a PSG (phosphorus glass) layer, or the like can be used. For example, passivation layer 1
When a SiO ₂ layer is used as 3, the thickness of the passivation layer 13 is about 2 μm. Alternatively, the passivation layer 13 can have a multilayer structure. As a case where the passivation layer 13 has a multilayer structure, for example, a laminated structure of a SiO ₂ layer and a SiN layer can be considered.

On the pad member 12 and on the passivation layer 13 formed around the pad member 12, a base metal layer 14 is formed.
Are formed. The underlying metal layer 14 is also called a so-called under bump metal, and also serves as a plating metal layer. The underlying metal layer 14 has a laminated structure of a barrier metal layer 141 and a protective metal layer 151 for adhesion. In the base metal layer 14, for example, the barrier metal layer 141 is made of TiW, and the protective metal layer 151 is made of an Au layer.
On the underlayer metal layer 14, a bump electrode 15 formed by, for example, Au plating is formed.

The angle θ between the side surface 15a of the bump electrode 15 and the surface of the pad member 12 is θ ≧ 80 °, preferably 80 ° ≦ θ ≦ 105 °, and more preferably θ ≒.
90 °.

The angle θ formed between the side surface 15a of the bump electrode 15 and the surface of the pad member 12 is, in other words, the surface of the pad member 12 and the direction in which the bump electrode 15 extends upward from the base metal layer 14. The corner.

If θ is less than 80 °, the bump electrode 15
When joining with a joining member (for example, a lead or a terminal electrode), the bump electrode 15 is deformed, and the adjacent bump electrodes 15 come into contact with each other to increase the possibility of a short circuit. On the other hand, by setting θ to be within 105 °, it is possible to sufficiently secure an effective bonding area when bonding the bump electrode 15 and the bonding member, and to obtain a good bonding without lowering the reliability at the time of bonding. The state is obtained. In particular, when TAB or COF is applied to the connection of the bump electrode 15, if the effective bonding area is reduced, the allowable margin in the alignment with the bonding member is reduced, and the reliability is reduced. Also, when the ACF is applied to the connection of the bump electrode 15, if the effective bonding area is reduced, the number of conductive particles present on the bonding surface between the bump electrode 15 and the bonding member is reduced, and the reliability at the time of bonding is reduced. I do.

On the other hand, the side surface 15a of the bump electrode 15
And the angle θ between the pad member 12 and the surface thereof is 80 ° ≦ θ ≦
When the angle is 105 °, it is possible to effectively cope with a narrow pitch and to maintain the reliability at the time of joining. Note that the semiconductor device 110 shown in FIG. 1 shows a case where the angle θ is approximately 90 °, that is, a case where the bump electrode 15 extends substantially vertically. In the bump electrode 15 shown in FIG. 1, since the angle θ is approximately 90 °, the cross-sectional shape and size of the upper and lower portions of the bump electrode 15 are substantially equal. It is possible to more reliably prevent the bump electrodes 15 from being deformed at the time of joining and the adjacent bump electrodes 15 from contacting each other and causing a short circuit. Thereby, it is possible to more effectively cope with a narrow pitch of the bump electrodes.

It is desirable that the roughness Ra of the surface 15b of the bump electrode 15 is 0.1 to 0.4 μm. When the roughness Ra of the surface 15b of the bump electrode 15 is less than 0.1, when joining the bump electrode 15 and the joining member,
Alignment may be difficult due to light reflected from the surface 15b of the bump electrode 15. Also, in this case,
For example, when joining the bump electrode 15 and the joining member using ACF, the surface 15b of the bump electrode 15
In some cases, it becomes difficult to capture the conductive particles, and sufficient conductivity may not be obtained.

On the other hand, if the roughness Ra of the surface 15b of the bump electrode 15 exceeds 0.4, the area that effectively contributes to the bonding between the bump electrode 15 and the bonding member is reduced, so that sufficient bonding strength can be secured. May disappear.

On the other hand, the surface 15b of the bump electrode 15
Is within the range of 0.1 to 0.4 μm,
Since a sufficient bonding area is obtained at the bonding portion between the bump electrode 15 and the bonding member to ensure a good bonding state, sufficient bonding strength can be ensured at the bonding portion. Further, the roughness Ra of the surface 15b is 0.1 to 0.1.
When it is within the range of 4 μm, the surface 15 of the bump electrode 15
b, the light is scattered to some extent, so that the reflected light from the surface 15b can be suppressed to an extent that alignment is possible, so that the alignment at the time of joining the bump electrode 15 and the joining member becomes easy. Furthermore, when the bump electrode 15 and the joining member are joined using the ACF, the conductive particles are trapped on the surface 15b of the bump electrode 15, so that a good conduction state is secured between the bump electrode 15 and the joining member. can do. Also, in TAB mounting, if the roughness Ra is in the range of 0.1 to 0.4 μm, a sufficient bonding strength can be secured at the bonding portion between the lead member and the bump electrode. This means, for example, that the bump electrode
When formed by u plating, the roughness Ra is 0.1 to 0.1.
When the thickness is within the range of 4 μm, Au is appropriately absorbed into the lead member, and a sufficient side fillet can be formed at the joint between the lead member and the Au bump electrode.

The roughness Ra of the surface 15b of the bump electrode 15
Can be adjusted by an Au plating process (described later).

Next, a method of manufacturing the semiconductor device 110 shown in FIG. 1 will be described.

(Device Manufacturing Method) FIG. 2 is a sectional view showing a plating step in forming the bump electrode 15 shown in FIG. First, the barrier metal layer 141 made of TiW
A positive resist layer 21 having a predetermined pattern is formed on a base metal layer 14a having a stacked structure of a and a protective metal layer 151a made of Au. In order to form the bump electrode 15 on the pad member 12, such a resist layer 2
1 has an opening 21 a on the pad member 12. According to the pattern of the positive resist layer 21, Au is deposited in the openings 21a by electrolytic plating to form the bump electrodes 15.

As described above, the positive resist is used when forming a pattern using an exposure mask (not shown).
Due to light interference between the applied resist layer and the mask, the upper part (the side closer to the exposure mask) of the resist layer is more sensitive than the lower part. Therefore, the opening 21a of the positive resist layer 21 obtained by the exposure is
The opening area increases as approaching the surface.

In the present embodiment, the amount of Au deposited in the Au plating step when forming the bump electrode 15 is controlled by the plating time. By this step, the bump electrode 1
Au deposited by an Au plating process for forming 5
The height B of the plating layer is set to 2/3 of the height A of the resist layer 21.
Do the following. That is, in the Au plating step, the bump electrode 1 is stacked without laminating the Au plating layer until the opening area above the opening 21a of the resist 21 is increased.
5 is formed. Therefore, in this case, it is necessary to form the resist layer 21 having a height 1.5 times or more the desired height of the bump electrode 15. For example, height B
When forming the bump electrode 15 having a thickness of 20 μm, it is necessary to form the resist layer 21 having a height A of 30 μm or more.

As described above, the roughness Ra of the surface 15b of the bump electrode 15 is desirably 0.1 to 0.4 μm. The roughness Ra of the surface 15b of the bump electrode 15
Can be adjusted by the Au plating process described above.

In the case of manufacturing a bump electrode by Au plating, a method of performing an Au plating process under a high current density and a high temperature condition is generally selected in order to shorten a plating time, and a fine method based on a relationship between the current density and the temperature is selected. Coordination was not valued. However, an Au bump electrode manufactured under high current density and high temperature conditions is not necessarily a preferable surface state in order to obtain a good bonding state between the Au bump electrode and a bonding member (a lead, a terminal electrode, or the like). Could not be said to have. Therefore, in the present invention, the roughness Ra of the surface 15b of the bump electrode 15 is adjusted by the Au plating process. Thereby, the bump electrode 15
It is possible to improve the joining state between the member and the joining member.

FIG. 5 shows the plating temperature T (° C.) and the plating current density CD (A / dm) in the Au plating step shown in FIG.
FIG. ² is a characteristic diagram showing the relationship ² ). Here, Au100 and Au120 manufactured by EEJA (Japan Electroplating Engineers Co., Ltd.) were used as the plating solution.

In FIG. 5, the surface roughness Ra is 0.1 to
When the bump electrode surface is in the range of 0.4 μm, the surface roughness Ra is about 0.1 μm away from the range of 0.1 to 0.4 μm, and the surface roughness Ra is unfavorable as the bump electrode surface in terms of surface roughness. And those whose surface roughness Ra is more than 0.1 μm apart from the range of 0.1 to 0.4 μm are indicated by x.

Generally, the lower the current density, the higher the surface roughness of the layer formed by plating. In order to set the roughness Ra within the above-described range, as shown in FIG.
The plating process is performed while maintaining the relationship of 0.05 × T−2.0 (mainly the hatched portion).

Further, by lowering the current density, the growth in the lateral direction (in the direction parallel to the surface of the bump member 12) with respect to the resist layer 21 during plating is suppressed,
It is easy to form a bump electrode having substantially the same cross-sectional shape and size from the top to the bottom. Further, when the plating temperature is 70 ° C. or lower, the deformation of the resist layer 21 due to heat is small, and the deformation of the opening 21 a is also small.
A bump electrode 15 having a desired shape is obtained. When the plating temperature is 40 ° C. or lower, a cooling cooler needs to be used in addition to the heater, so that the temperature control of the plating solution is not easy and the plating solution may be non-uniform. For this reason, the temperature of the plating solution is more preferably 40 to 70 ° C.

Thereafter, after the resist 21 is removed, wet etching is performed on the barrier metal layer 141a and the protective metal layer 151a using the bump electrode 15 as a mask to obtain the base metal layer 14. Thus, the semiconductor device 110 having the bump electrode structure 150 shown in FIG. 1 can be obtained.

According to the above manufacturing method, the bump electrode 15
Has a shape extending in a direction substantially perpendicular to the bonding surface with the pad member 12. The bump electrodes 15 have a cross-sectional shape and a difference in size between the upper and lower portions of the bump electrodes 15 as small as possible.
The occurrence of short-circuit due to contact between adjacent bump electrodes can be reduced.

(Application Example of Device) Next, FIGS. 3 and 4 show an example of a semiconductor device including the bump electrode structure 150 including the bump electrode 15 shown in FIG.

First, FIG. 3 shows a cross section of a semiconductor device 120 in which the bump electrode structure 150 including the bump electrode 15 shown in FIG. 1 is applied to TAB mounting. Semiconductor device 1 shown in FIG.
In manufacturing the device 20, the leads 31 formed on a tape (not shown) are thermocompression-bonded onto the bump electrodes 15. In FIG. 3, the lead 31 includes a Cu thin film layer and an Sn plating layer (both not shown) covering the Cu thin film layer, and the bump electrode 15 includes an Au plating layer as described above.
Therefore, by the thermocompression bonding step, the bump electrode 15 made of Au and the Sn plating layer forming the lead 31 are pressed, and eutectic of Au and Sn is achieved. In this step, the bump electrode 15 is further deformed by the load applied to the bump electrode 15 when the lead 31 is pressed. However, since the cross-sectional shape and size of the bump electrode 15 before pressurization are substantially equal between the upper part and the lower part, adjacent bump electrodes 15 come into contact with each other due to deformation of the bump electrode 15 due to pressurization, and a short circuit occurs. Can be prevented.

Further, since the surface roughness Ra of the bump electrode 15 is 0.1 to 0.4 μm, even when TAB is used, the connection state between the bump electrode 15 and the lead 31 serving as a bonding member can be improved. Can be further improved.

Next, FIG. 4 shows a cross section of a semiconductor device 130 in which the bump electrode structure 150 including the bump electrode 15 shown in FIG. 1 is applied to COG mounting by ACF. In the semiconductor device 130 shown in FIG. 4, a mounting circuit board (not shown) made of an organic material such as glass epoxy or a glass substrate on which signal input terminals of a liquid crystal display device are formed.
The terminal electrodes 41 arranged above and the bump electrodes 15 are joined. That is, the bump electrodes 15 are electrically connected to the opposing terminal electrodes 91 via the ACF 42, respectively.

In the ACF 42, conductive particles 43 having a diameter of about 5 μm are dispersed in a film-like epoxy resin 44. In the semiconductor device 130, the conductive particles 43 are interposed between the terminal electrode 41 and the bump electrode 15 through a pressing / heating process using a crimping tool (not shown), and the bonding between the terminal electrode 41 and the bump electrode 15 is performed. When the gap between the portions 45 is equal to or smaller than the particle size of the conductive particles 43, a conductive state is obtained. There is no conduction between the adjacent terminal electrodes 41 and between the bump electrodes 15 because they are not in contact with the conductive particles 43.

In the semiconductor device 130 shown in FIG.
Since the cross-sectional area of the bump electrode 15 is substantially equal between the upper part and the lower part of the bump electrode 15, even if a load is applied to the bump electrode 15 in the pressing / heating step, only the upper part of the bump electrode 15 is formed. There is no significant deformation.
As a result, it is possible to prevent the adjacent bump electrodes 65 from contacting each other and causing a short circuit. In addition, the adjacent bump electrodes 65 do not come into contact with each other with the conductive particles 43 interposed therebetween, and no short circuit occurs.

On the other hand, if the ACF 42 does not reach the vicinity of the junction between the bump electrode 15 and the passivation layer 13, bubbles may remain in such a portion, and cracks may occur in the bump electrode 15 due to the vapor stress generated by the bubbles. is there. On the other hand, according to the semiconductor device 130 shown in FIG. 4, since the difference in cross-sectional shape and size between the upper and lower portions of the bump electrode 15 is small, the ACF 42 extends to the vicinity of the junction between the bump electrode 15 and the passivation layer 13. Cracks are less likely to occur. Such an effect is similarly exhibited when the bump electrode structure 150 according to the present embodiment is applied to COF.

Further, since the surface roughness Ra of the bump electrode 15 is 0.1 to 0.4 μm, even when the ACF is used, the connection between the bump electrode 15 and the terminal electrode 41 as a joining member can be achieved. The condition can be further improved.

As described above, since the bump electrode 15 according to the present embodiment has substantially the same cross-sectional shape and size at the upper portion and the lower portion, it can effectively cope with a narrow pitch of the bump electrodes.

Further, according to the method of manufacturing a semiconductor device according to the present embodiment, the height A of the resist layer 21 and the height B of the metal plating layer deposited for forming the bump electrode 15 are adjusted. Thereby, it is possible to obtain the bump electrode 15 whose cross-sectional shape and size are substantially equal from the upper part to the lower part. Thus, a semiconductor device that can cope with the narrow pitch of the bump electrodes 15 can be obtained.

Further, by setting the roughness Ra of the surface 15b of the bump electrode 15 in the range of 0.1 to 0.4 μm,
Even when TAB mounting or ACF (anisotropic conductive film) is applied, the connection state between the bump electrode 15 and the bonding member can be improved, which effectively contributes to mounting at a fine pitch. As a result, it is possible to prevent the occurrence of a short circuit due to the contact between the adjacent bump electrodes, and it is possible to obtain a highly reliable device that can cope with the narrow pitch of the bump electrodes.

In the present embodiment, the case where the pad member 12 is made of Al has been described. However, the material of the pad member 12 is not limited to this. It can also be used.
The relationship between the height of the resist layer 21 and the height of the bump electrode 15 can be applied even when the bump electrode 15 is made of a metal other than Au.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a plating step for forming a bump electrode shown in FIG. 1;

3 is a cross-sectional view showing an example in which the bump electrode structure including the bump electrode shown in FIG. 1 is applied to TAB (Tape Automated Bonding) mounting.

FIG. 4 is a view showing a structure in which a bump electrode structure including the bump electrode shown in FIG. 1 is formed by an ACF (Anisotropic Conductive Film).
It is sectional drawing which shows an example applied to OG (Chip On Glass) mounting.

FIG. 5 is a characteristic diagram showing a relationship between a plating temperature T (° C.) and a plating current density CD (A / dm ² ) at the time of Au plating as shown in FIG.

FIG. 6 is a cross-sectional view illustrating a configuration of a bump electrode provided on a pad member of a general semiconductor device.

FIG. 7 is a sectional view illustrating a plating step for forming a bump electrode illustrated in FIG. 6;

8 is a cross-sectional view showing an example in which the bump electrode structure including the bump electrode shown in FIG. 6 is applied to TAB (Tape Automated Bonding) mounting.

FIG. 9 shows a bump electrode structure including the bump electrode shown in FIG. 6 formed by an ACF (Anisotropic Conductive Film).
It is sectional drawing which shows an example applied to OG (Chip On Glass) mounting.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Insulating layer 12 Pad member 12a Electrical connection area 13 Passivation layer 14, 14a Base metal layer 15 Bump electrode 15a Side surface of bump electrode 15 15b Surface of bump electrode 15 21 Resist layer 21a Opening 31 Lead 41 Terminal electrode 42 ACF 43 Conductive particles 44 Resin 45 Joint 80 Plated electrode needle 110, 120, 130 Semiconductor device 141, 141a Base metal layer 150 Bump electrode structure 151, 151a Protective metal layer

Claims (7)

[Claims] A pad member formed on a base and having an electrical connection region; an insulating layer formed on a periphery of the pad member; a base metal layer formed on the pad member; A semiconductor device, comprising: a bump electrode provided on a base metal layer; and an angle θ between a side surface of the bump electrode and a surface of the pad member is θ ≧ 80 °. 2. The semiconductor device according to claim 1, wherein the angle θ satisfies 80 ° ≦ θ ≦ 105 °. 3. The semiconductor device according to claim 1, wherein the angle θ is approximately 90 °. 4. The bump electrode according to claim 1, wherein the bump electrode is made of a material containing gold as a main component, and a surface roughness Ra (μm) of the bump electrode is 0.1 ≦ Ra ≦
0.4, which is 0.4. 5. A pad member formed on a base and having an electrical connection region, an insulating layer formed on the pad member, a base metal layer formed on the pad member, and A bump electrode provided on a metal layer, wherein the bump electrode is made of a material containing gold as a main component, and the surface roughness Ra (μm) of the bump electrode is 0.1 ≦ Ra ≦
0.4, which is 0.4. 6. A step of forming a pad member in a predetermined region on a substrate, a step of coating an insulating layer so as to cover the pad member, and a step of forming the insulating layer on a peripheral portion of the pad member by photolithography. Exposing an electrical connection region in the pad member, leaving a base metal layer on the pad member and the insulating layer, and forming a resist layer having an opening on the base metal layer. Disposing the opening on the pad member; forming a metal plating layer on the base metal layer in the opening; removing the resist layer to form the metal. Forming a bump electrode made of a plating layer; and etching the base metal layer using the bump electrode as a mask, forming the metal plating layer. In step, the height of the metal plating layer to 2/3 or less of the height of the resist layer, a method of manufacturing a semiconductor device. 7. The method according to claim 6, wherein the step of forming the metal plating layer is a step of forming a gold plating layer, and the plating temperature T (° C.) and the plating current density CD (A / dm ² ) has a relationship represented by the following equation (1). CD ≦ 0.05 × T−2.0 Formula (1)