JP2001237312A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a deep recessed part is formed on the surface of first-layer wiring 48 that becomes the bottom surface of a through hole 30 when a deep recessed part is formed on a lower-side W plug 45 for burying a contact hole 23, and that the connection between the first-layer wiring and an upper-side W plug 49 for burying the through hole 30 is inferior for increasing resistance when the through hole 30 for connecting second-layer wiring 53 to the first wiring 48, in the structure that the contact hole 23 for connecting the first-layer wiring 48 to the active region of a semiconductor substrate 1 are provided at the same position. SOLUTION: A side wall 40 where an etchback is formed on the side of a contact hole 23 is provided for preventing cavities from being easily formed when the lower-side W plug is formed by the blanket method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a structure of a semiconductor device having a through hole for connecting an upper wiring and a middle wiring and a through hole for connecting the middle wiring and a lower wiring at the same position. And, it relates to a manufacturing method for obtaining such a structure.

[0002]

2. Description of the Related Art As a wiring structure of a semiconductor device, a through hole (or a contact hole) for connecting a lower wiring (including an active region of a semiconductor substrate) and a middle wiring above the lower wiring.
It is often practiced to reduce the size of the semiconductor device as much as possible by setting the middle wiring and the through hole connecting the upper wiring above it to the same position. A conventional example of such a wiring structure will be described with a brief description of a manufacturing method.
FIG. 3 is a sectional view of the main part. A first interlayer insulating film 2 is formed on a surface of a semiconductor substrate 1 on which a predetermined active region (not shown) is formed, and a contact hole 3 is formed at a predetermined position by anisotropic dry etching. Then, the first interlayer insulating film 2
A barrier layer 4 such as a titanium / titanium nitride laminated film (hereinafter referred to as a Ti / TiN laminated film) is formed by a sputtering method so as to cover the surface of the contact hole 3 and the side and bottom surfaces of the contact hole 3 (the surface of the semiconductor substrate 1). . Next, the entire surface is CVD
A tungsten film (hereinafter referred to as a W film) is formed to a thickness that fills the contact hole 3 by a method, and the entire surface is etched back until the surface of the first interlayer insulating film 2 is exposed. (Hereinafter, W plug) 5 is formed. At this time, the barrier layer on the first interlayer insulating film is also removed by etching. Then, since the W film formed by CVD has a concave portion so as to reflect the portion of the underlying contact hole 3, the center is slightly reflected on the surface of the lower W plug 5 after the etch back. A concave portion (plug loss) 5a that becomes lower occurs. Next, for example, Ti /
A barrier layer 6 such as a TiN laminated film and an alloy film 7 mainly composed of Al are formed by a sputtering method, and are patterned to form a first layer wiring 8 extending in the front and back direction of the drawing by a lower W plug 5 to a semiconductor substrate. One active region (not shown) is formed. Next, an insulating film is formed so as to cover the first interlayer insulating film 2 and the first layer wiring 8, and a planarization process is performed to form a second interlayer insulating film 9. Next, a through hole 10 is formed directly above the contact hole 3 by anisotropic dry etching. Then, a barrier layer 11 such as a Ti / TiN laminated film is formed by a sputtering method so as to cover the surface of the second interlayer insulating film 9 and the side and bottom surfaces of the through hole 10 (the surface of the first layer wiring 8). I do. Next, a W film is formed on the entire surface to fill the through hole 10 by the CVD method, and the entire surface is etched back until the surface of the second interlayer insulating film 9 is exposed. 12 is formed. At this time, the barrier layer on the second interlayer insulating film 9 is also removed by etching. Then, since the W film formed by CVD has a concave portion so as to reflect the portion of the underlying through hole 10, the center of the surface of the upper W plug 12 is slightly lowered after the etch back to reflect the concave portion. A concave portion (plug loss) 12a occurs. Next, for example, Ti / TiN
Barrier layer 13 such as a laminated film and alloy film 1 mainly composed of Al
4 is formed by sputtering and patterned to form a second layer wiring 15 extending in the left-right direction in FIG.
To form a connection with the first layer wiring.

As described above, since the contact holes and the through holes are filled with the W plug by the blanket method, the upper and lower wirings can be connected even in the contact holes and the through holes having a large aspect ratio.

[0004]

However, when the contact holes and the through holes are further miniaturized, the following problems arise. FIG. 4 is a cross-sectional view of a main part in the order of the manufacturing process when the contact holes and the through holes are miniaturized. In such a case, a first interlayer insulating film 2 is formed on the surface of the semiconductor substrate 1 and a fine contact hole is formed at a predetermined position, as shown in the sectional view of the main part after the formation of the W film shown in FIG. If the barrier layer 4 is formed by sputtering, and the barrier layer 4 is formed by sputtering, the barrier layer 4 deposited on the side surface of the contact hole 23 tends to be thicker at the mouth and thinner at the bottom. Therefore, if the W film 5b is formed on the entire surface by the CVD method so as to fill the contact hole 23, the opening is closed before the contact hole 23 is completely filled, and the cavity 5c tends to be formed. Therefore, the first
When the entire surface is etched back until the surface of the interlayer insulating film 2 is exposed, there is a recess 5d so that the CVD-formed W film 5b reflects the underlying contact hole 23, and as shown in FIG. After the etch-back, a concave portion (plug loss) 5a having a slightly lower center is formed on the surface of the lower W plug 25 reflecting that. The recess 5a is connected to the cavity 5c to form an apparently deep recess 25a.
Therefore, next, as shown in FIG.
A barrier layer 6 such as an i / TiN laminated film and an alloy film 7 mainly composed of Al are formed by a sputtering method, and are patterned to form a first layer wiring 28 extending in the front and back direction of the drawing by a lower W plug 25. When formed to be connected to an active region (not shown) of the semiconductor substrate 1, a deep recess 25 a of the lower W plug 25 is formed.
In the first layer wiring 28, a relatively deep concave portion 28a is formed at the contact hole 23. The through hole 30 penetrating the second interlayer insulating film 9 is provided at the deep concave portion 28a in this way, and as described with reference to FIG. 3, the upper W plug 32 and the barrier layer 13 such as the Ti / TiN laminated film are formed. When the second-layer wiring 35 made of Al and the alloy film 14 mainly composed of Al is formed, there is a problem that the connection resistance between the first-layer wiring 28 and the second-layer wiring 35 increases. The reason is that, for example, in the step of forming the barrier layer 11 prior to the CVD for the upper W plug 32, the underlying first layer wiring 28 has a concave portion, so that the coverage is poor and the contact area is insufficient. It is possible that W and Al react to form a substance with high resistance, but it is not yet clear. Therefore, the present invention provides a connection structure in which the bottom of the upper through hole is made flatter to suppress the occurrence of abnormal connection resistance, and a manufacturing method for manufacturing the same.

[0005]

In order to solve the above-mentioned problems, the present invention is directed to a lower wiring, a first interlayer insulating film covering the lower wiring, a middle wiring formed thereon, and a first wiring. A lower through hole provided at a place where the lower wiring and the middle wiring of the interlayer insulating film are connected, and the lower wiring and the middle wiring formed by a blanket method and filling the lower through hole. A lower W plug to be connected, a second interlayer insulating film covering the first interlayer insulating film and the intermediate wiring, and an upper side provided just above the lower through hole in the second interlayer insulating film A through hole, an upper W plug formed by a blanket method to fill the upper through hole and connect to the middle wiring, and an upper wiring arranged on the second interlayer insulating film and connected to the upper M plug. Semiconductor device provided with In the lower through-hole, a sidewall formed by an etch-back method is provided on a side surface thereof, and a barrier layer that covers the sidewall and a bottom surface of the lower through-hole is provided. A semiconductor device is provided, wherein the lower W plug is filled. According to the above configuration, a sidewall formed by an etch-back method is provided on the side surface in the lower through hole, the sidewall has a taper, the upper opening side of the lower through hole is widened, and the bottom side is formed. It is narrow. Therefore, in order to form the lower W plug, CV
When the W film is formed by the method D, the inside of the through hole is closed from the narrow bottom side, so that it is difficult to form a cavity. that way,
When W is etched back to leave W only in the through hole to form a lower W plug, a deep recess is not formed, and the surface of the intermediate wiring formed thereon is prevented from having a deep recess. Then, as a method of manufacturing the semiconductor device, a first interlayer insulating film having a lower through hole exposing a predetermined position of the lower wiring is formed on the surface of the semiconductor substrate on which the lower wiring is formed. A surface of the first interlayer insulating film;
A thin film is formed so as to cover the side surface and the bottom surface of the through hole, and it is etched back by anisotropic etching to form a sidewall on the side surface of the lower through hole,
A barrier layer is formed on the entire surface including the side wall surface and the bottom surface of the lower through hole by a sputtering method, and a W film is formed on the surface of the barrier layer by a CVD method so as to fill the contact hole 3. A lower W plug is formed leaving only the inside of the lower contact hole, and a middle wiring connected to the lower W plug and extending on the first interlayer insulating film is formed. Forming a second interlayer insulating film having an upper through hole directly above the lower through hole, forming an upper W plug in the upper through hole, and further forming an upper wiring connected to the upper W plug; There is provided a method for manufacturing a semiconductor device, characterized by being formed.

[0006] The "lower wiring" in this specification may be an active region such as an impurity diffusion region formed in a semiconductor substrate. In this case, the lower through hole in this specification is usually called a contact hole.

[0007]

An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of the main part, and FIG. 2 is a cross-sectional view of the main part in the order of the manufacturing process. The detailed configuration will be described while explaining the manufacturing method. First, a semiconductor substrate 1 on which a predetermined active region (not shown) is formed is prepared. In this active region, a portion connected to a wiring above it corresponds to a lower wiring in the present invention. Then, an insulating film mainly composed of, for example, PSG is formed on the surface by a CVD method,
If necessary, the first interlayer insulating film 2 is formed by flattening. Then, a contact hole 23 is formed at a predetermined position for performing wiring connection by anisotropic dry etching. The contact hole 23 corresponds to a lower through hole in the present invention (see FIG. 2A). Next, a thin film of, for example, silicon nitride is formed by a suitable method such as a CDV method or a sputtering method so as to cover the surface of the first interlayer insulating film 2 and the side and bottom surfaces of the contact hole 23 (the surface of the semiconductor substrate 1). Etchback is performed by anisotropic etching to remove the silicon nitride film on the surface of the first interlayer insulating film 2 and the bottom surface of the contact hole 23, and leave the sidewall only on the side surface of the contact hole 23 to form a sidewall 40. In this embodiment, the sidewalls 40 are made of silicon nitride, but may be made of a conductive material such as a metal such as tungsten or a compound such as titanium nitride. However, a sufficient etching selectivity must be obtained in relation to the first interlayer insulating film 2. When the first interlayer insulating film is made of a material mainly composed of silicon oxide such as PSG, each of the above materials can be suitably used. Next, a barrier layer 4 such as a Ti / TiN laminated film is formed so as to cover the surface of the first interlayer insulating film 2, the bottom of the contact hole 23 and the surface of the sidewall 40.
Is formed by a sputtering method. Next, a W film 41 is formed on the entire surface by a CVD method so as to fill the contact holes 23. Then, since the sidewalls 40 are formed in a tapered shape, the W film 41 fills the contact hole 23 from the bottom and deposits so as to close the opening at the end, so that the occurrence of a large cavity is greatly reduced. (Figure 2
(B)). Next, the W film 41 and the barrier layer 4 are etched back over the entire surface until the surface of the first interlayer insulating film 2 is exposed, leaving the lower W plug 4 in the contact hole 23.
5 is formed. Next, a barrier layer 6 such as a Ti / TiN laminated film and an alloy film 7 mainly composed of Al are formed on the entire surface by a sputtering method, and are patterned to form a first layer wiring 48 extending in the front and back directions in the drawing. It is formed by connecting to an active region (not shown) of the semiconductor substrate 1 by the side W plug 45. Here, the first layer wiring 48 corresponds to the middle layer wiring in the present invention. Since the W film formed by CVD has the concave portion 41a so as to reflect the portion of the underlying contact hole 23 (see FIG. 2B), the surface of the lower W plug 45 is reflected after the etch back to reflect that. Has a recess (plug loss) 45a whose center is slightly lower, but is not deep.
Therefore, no deep recess is formed on the surface of the first layer wiring 48 formed thereon (see FIG. 2C). Next, an insulating film such as a PSG film is formed by a CVD method so as to cover the first interlayer insulating film 2 and the first layer wiring 48, and a planarization process is performed. I do. Next, a through hole 30 is formed directly above the contact hole 23 by anisotropic dry etching. Here, the through hole 30 corresponds to the upper through hole in the present invention. And
A barrier layer 11 such as a Ti / TiN laminated film is formed by a sputtering method so as to cover the surface of the second interlayer insulating film 9 and the side and bottom surfaces of the through hole 30 (the surface of the first layer wiring 48). Next, a W film 43 is formed on the entire surface by a CVD method so as to fill the through holes 30. Then,
Since no sidewall is formed in the through hole 30, there is a high possibility that a cavity 43a will be formed inside (see FIG. 2).
(D)). Next, the W film 43 and the barrier layer 11 are entirely etched back until the surface of the second interlayer insulating film 9 is exposed, and an upper W plug 49 is formed while remaining in the through hole 30. Then, after the etch back, the cavity 43 may be connected to a plug loss generated on the surface, and a deep concave portion 50 may be generated. However, since there is no deep recess on the surface of the first layer wiring 48 forming the bottom surface of the through hole 30, the upper W plug 49 is connected to the first layer wiring 48 via the barrier layer 11.
With low resistance. Next, for example, Ti / TiN
Barrier layer 51 such as a laminated film and Al-based alloy film 5
2 is formed by a sputtering method, and is patterned to form a second layer wiring 53 extending in the left-right direction in FIG.
(See FIG. 1). The second layer wiring 53 corresponds to the upper layer wiring in the present invention.

The semiconductor device of the present invention manufactured by the above-described manufacturing method and shown in FIG. 1 has an active region (not shown) provided on a semiconductor substrate 1 as a lower wiring, and a first interlayer insulating film covering the active region. 2 and the first as an intermediate wiring formed thereon.
A layer wiring 48, a contact hole 23 as a lower through hole provided at a place where an active region (not shown) as a lower layer wiring of the first interlayer insulating film and the first layer wiring 48 are connected, A lower W plug 45 which is formed by a blanket method and fills the contact hole 23 to connect an active region (not shown) as a lower layer wiring to a first layer wiring; a first interlayer insulating film 2 and a first layer A second interlayer insulating film 9 covering the wiring 48, a through hole 30 (upper through hole of the present invention) provided immediately above the contact hole 23 in the second interlayer insulating film 9, and a blanket method. Upper W plug 49 for filling through hole and connecting to first layer wiring 48
And a semiconductor device provided on the second interlayer insulating film 9 and having a second layer wiring as an upper layer wiring connected to the upper W plug, the contact hole 23 is formed on the side surface by an etch-back method. Since the sidewalls 40 are provided and the through holes 23 are tapered so as to become thinner toward the bottom, the barrier layer 4 that covers the sidewalls 40 and the bottom surfaces of the contact holes 23 is provided. When filling the side W plug 45,
It is difficult to form a cavity, so that a deep concave portion is not formed on the surface of the first layer wiring 48 disposed thereon, and the connection between the first layer wiring 48 and the upper W plug 49 is improved.

The above embodiment is directed to a lower wiring according to the present invention,
The case where the middle layer wiring and the upper layer wiring correspond to the active region of the semiconductor substrate, the first layer wiring, and the second layer wiring, respectively, has been described. For example, the lower layer wiring is the first layer wiring, and the middle layer wiring is the second layer wiring. The same can be applied to the case where the upper wiring is a connection between three wiring layers provided in the upper layer of the semiconductor substrate like the third wiring.

In the above embodiment, no sidewall is provided in the upper through hole. However, the upper through hole is provided in the same manner as in the lower side to prevent the occurrence of a deep recess 50 formed on the surface of the upper W plug, thereby preventing the upper wiring from being connected to the upper wiring. The connection with the plug can be made more reliable.

It is needless to say that the first interlayer insulating film and the second interlayer insulating film of the present invention may include another wiring irrelevant to the connection structure of the present invention.

[0011]

As described above, according to the semiconductor device of the present invention, the connection between the middle wiring and the upper W plug is ensured, and the connection between the middle wiring and the upper wiring is connected stably with low resistance. I do. Further, according to the manufacturing method of the present invention, the semiconductor device of the present invention can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an essential part cross sectional view showing the order of steps for describing the manufacturing method of the present invention;

FIG. 3 is a cross-sectional view of a main part showing a conventional semiconductor device.

FIG. 4 is an essential part cross sectional view shown in order of process for describing a problem of the conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate (lower layer wiring) 2 first interlayer insulating film 4 barrier layer 9 second interlayer insulating film 23 contact hole (lower through hole) 30 through hole (upper through hole) 40 side wall 41 W film 45 lower side W plug 49 Upper W plug 53 Second layer wiring (upper layer wiring)

Claims (4)

[Claims] A lower wiring, a first interlayer insulating film covering the lower wiring, a middle wiring formed thereon, and a place connecting the lower wiring and the middle wiring of the first interlayer insulating film. A lower tungsten plug formed by a blanket method to fill the lower through hole and connect the lower wiring and the middle wiring, the first interlayer insulating film, A second interlayer insulating film covering the middle wiring, an upper through-hole provided immediately above the lower through-hole of the second interlayer insulating film, and a blanket method formed to fill the upper through-hole. An upper tungsten plug connected to the middle wiring,
And an upper layer wiring connected to the upper tongue plug and disposed on the interlayer insulating film, wherein a sidewall formed by an etch-back method is provided on a side surface in the lower through hole, A semiconductor device, comprising: a barrier layer that covers the side wall and a bottom surface of the lower through hole; and the lower tungsten plug is filled therein. 2. A first interlayer insulating film having a lower through hole exposing a predetermined position of the lower wiring is formed on a surface of a semiconductor substrate on which a lower wiring is formed, and wherein the first interlayer insulating film is provided. A thin film is formed so as to cover the surface of the film and the side and bottom surfaces of the through hole, and the thin film is etched back by anisotropic etching to form a sidewall on the side surface of the lower through hole; A barrier layer is formed on the entire surface including the bottom surface of the lower through hole by sputtering, and a tungsten film is formed on the surface of the barrier layer to fill the contact hole 3 by CVD, and the lower contact is etched back. A lower tungsten plug is formed leaving only the inside of the hole, and connected to the lower tungsten plug,
A second interlayer insulating film having an upper through hole immediately above the lower through hole is formed on the entire surface including on the intermediate wiring, and then the upper through hole is formed. A method of manufacturing a semiconductor device, comprising: forming an upper tungsten plug therein; and forming an upper wiring connected to the upper tungsten plug. 3. The semiconductor device according to claim 1, wherein a material of said first interlayer insulating film is mainly silicon oxide, and said sidewall is silicon nitride. 4. The semiconductor device according to claim 1, wherein said sidewall is made of a conductive material.