JP2001237378A - Integrated circuit and method of verifying internal signal thereof - Google Patents

Abstract

(57) [Summary] [PROBLEMS] The present invention does not greatly increase the number of pins.
An object of the present invention is to provide a configuration of an integrated circuit capable of accurately observing an internal signal. An internal signal observation circuit for outputting an internal signal as a serial signal is provided in an integrated circuit. When performing observation, the test apparatus 20 inputs a command from the serial input SIN together with the clock signal CLK, and instructs sampling of an internal signal. The internal signal observing circuit 1 samples the internal signal specified by this command and outputs it as a serial output SOUT. Also, according to an instruction from the internal signal observation circuit 1, an arbitrary value can be written to the internal register 3 during normal operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an integrated circuit having a means for externally observing an internal signal and a method for verifying the internal operation of the integrated circuit.

[0002]

2. Description of the Related Art An integrated circuit is provided with a means for observing an internal signal in the integrated circuit from outside the device for an evaluation test in a production factory or for debugging or failure analysis. There is something.

[0003] There are the following two methods for observing signals inside a conventional integrated circuit. 1) A method of providing pins for outputting internal signals of the number of signals to be observed within the limit of the number of input / output pins of the semiconductor device. 2) A method in which a pin for observing an internal signal is shared with other normal input / output pins, and a device is provided with a mode for performing a normal operation and a mode for observing an internal signal.

FIG. 12 shows the principle of construction of an integrated circuit according to the method 1). In this method, an output pin directly connected to each signal line which needs to be observed is provided, and a measuring instrument is connected to these pins, thereby externally observing a signal state inside the integrated circuit. In the case of the integrated circuit 100 of FIG. 12, the internal circuit block 101-1 and the internal circuit block 1
Output pins are provided for internal signal lines between 01-2 and 101-3, respectively. In the method 1), it is necessary to provide extra output pins for the number of signals that need to be observed, in addition to the pins for the original operation purpose of the integrated circuit.

FIG. 13 shows the principle of construction of an integrated circuit according to the method 2). In the method 2), a pin for observing an internal signal and an input / output pin used during normal operation are shared in order to prevent an increase in the number of pins.

In this case, the integrated circuit is provided with a test mode selection signal pin for switching between a normal specification mode and a test mode for observing an internal state. L "
Is input, and when an internal signal is observed, "H" is input to switch from a mode in which a normal operation is performed to a test mode. In the test mode, the output of the signal pin shared by the internal multiplex is switched to the signal indicating the internal state. In the integrated circuit 200 of FIG. 13, the output pin 203 is shared, and the output of the selector 202 is output by the test mode selection signal 204 to the internal signal between the internal circuit blocks 201-1 and 201-2 and the internal circuit block 201. -3.

The internal register provided inside the integrated circuit is configured to be rewritten as one of the operation processes in a normal operation process.

[0008]

The methods 1) and 2) have the following problems. In the case of the method 1), an extra output pin is required for the internal signal necessary for observation. Therefore, the number of output pins increases by the number of internal signals to be observed. Therefore, it is necessary to change the package of the semiconductor device used to one with a large number of pins, but the number of pins of the semiconductor device is limited by the cost, the type of package that can be used, the mounting area, etc. Often, there is not enough room to assign an output pin to a device.

In the case of the method 2), when observing the internal signal, the internal signal is operated in a special mode different from that in the normal operation. In such a special mode different from the normally used state, it is difficult to reproduce the same state as in the normal operation, and the internal signal during the normal operation cannot be accurately observed. This problem can be solved by creating a device dedicated for testing, but changing semiconductor devices usually leads to an increase in cost, and is not usually performed. For this reason, observation of the internal signal in the normal operation was substantially impossible.

In the conventional device, the set value of the internal register is changed in a normal operation. In order to enable the internal register to be changed to an arbitrary value during the normal operation, a means for that is set in advance in a design stage. I have to prepare it.

An object of the present invention is to provide an integrated circuit and a method of verifying an internal signal of the integrated circuit in consideration of the above problems.

[0012]

In order to solve the above-mentioned problems, an integrated circuit according to the present invention comprises input means, sampling means, parallel-serial conversion means, and output means.

The input means receives a command from outside the integrated circuit as a serial signal. The sampling means samples the internal signal based on the command. The parallel-serial converter converts the sampling result into serial data.

The output means outputs the serial data to the outside of the integrated circuit. With this configuration, the integrated circuit according to the present invention receives an instruction as serial data and outputs the sampling result as serial data. The signal can be observed from outside.

Further, the integrated circuit according to the present invention may be configured to further include an internal register value setting means for setting an internal register value of the integrated circuit based on the command. In the case of this configuration, the integrated circuit can set an internal register in the integrated circuit to an arbitrary value irrespective of the setting by the internal operation in response to an external command.

[0016]

FIG. 1 shows an outline of the present embodiment.
The integrated circuit 10 of FIG. 1 is an integrated circuit of a digital synchronous circuit that operates using the synchronous signal BCLK as a reference synchronous signal.

In the present embodiment, an internal signal observing circuit 1 is configured inside the integrated circuit 10 for observing an internal signal, and sampling is performed on each signal line in the integrated circuit 10 using the internal signal observing circuit 1. And outputs the result to the outside of the device as a serial signal.

The internal signal observation circuit 1 includes input pins CLK and SIN and an output pin SO as external pins of the integrated circuit 10.
It has three pins on the UT. When observing the internal signal of the integrated circuit 10, the integrated circuit 10 is mounted on a circuit board and operated in a normally used state. Sending a command to the signal observation circuit 1,
Observe the sampling result of the output internal signal. As described above, the integrated circuit 10 of the present embodiment can reproduce the operation state of the circuit to be observed in a perfect form as it is in a normal use state, and observe the state of the internal signal at that time by the test apparatus 20. I can do it.

The input signal CLK input from the input pin CLK of the integrated circuit 10 is a synchronization signal for controlling the internal signal observation circuit 1 and has a frequency several times to several hundred times higher than the reference synchronization signal BCLK of the integrated circuit 10. have. Also, this signal CL
K is used not only as an operation clock of the internal signal observation circuit 1 but also as a synchronization signal for serial transmission and reception between the integrated circuit 10 and the test apparatus 20 and a sampling signal of an internal signal to be measured.

The serial input signal SIN input from the input pin SIN is serial data for the test apparatus 20 to give an instruction to the internal signal observing circuit 1 such as operation setting and selection of an internal signal group to be measured. . The test apparatus 20 serially inputs an instruction to the internal signal observation circuit 1 from the SIN pin. The internal signal observation circuit 1 decodes the input data on this signal, sets the operation, and selects / selects an internal signal group. Release, start / stop, reset of the internal signal observation circuit 1, rewriting of an internal register of the integrated circuit 10, and the like are performed.

FIG. 2A shows the structure of the serial input signal SIN. The serial signal SIN includes a header portion and a data portion, and the header portion has information indicating the type of the serial data. The data portion has a structure in which the data body is stored. The test apparatus 20 instructs the integrated circuit 10 to operate by inputting a start bit, a header section storing an instruction for the integrated circuit 10, a data section, and finally, serial data in the form of a stop bit from the input pin SIN.

The serial output signal SOUT output from the output pin SOUT is serial data indicating the state of an internal signal of the integrated circuit 10 output from the internal signal observation circuit 1. The internal signal observation circuit 1 receives the serial input signal SI
N, the internal signal of the integrated circuit 10 is sampled based on an instruction from the test apparatus 20 by N.
An output is output from the output pin SOUT to the outside of the integrated circuit 10 as a serial output signal SOUT as shown in FIG.

The integrated circuit 10 according to the present invention can be applied to an integrated circuit using an asynchronous circuit in addition to the synchronous circuit shown in FIG. If the integrated circuit 10 is a synchronous circuit,
The internal operation clock BCLK of the integrated circuit 10 is input to the internal signal observation circuit 1, and sampling of the internal signal can be performed in synchronization with the internal operation clock BCLK. In this case, sampling is performed by setting the number of signals selected as the observation target and the number of samplings in one cycle of BCLK depending on the signals CLK and BCLK. When sampling is performed asynchronously, the sampling period is set at a period that depends on the number of signals selected as the observation target and the sampling signal CLK.

FIG. 3 is a diagram showing a configuration example of the internal signal observation circuit 1. In the configuration shown in FIG.
Are serial / parallel conversion block 11, parallel / serial conversion block 12, setting register block 13,
It comprises a data decoder 14, a sampling block 15, a register rewrite control block 16, and a selector 17. The serial / parallel conversion block 11 converts the serial signal input from the SIN pin by the test device 20 into parallel in synchronization with the clock signal CLK, and outputs the parallel signal to the data decoder 14. The data decoder 14 decodes data input from the test device 20. As a result, if the instruction stored in the data part is, for example, an instruction instructing the setting of the internal signal observing circuit 1, the corresponding data in the following data part is set in the designated setting register in the setting register block 13. If the instruction is a selection instruction of an internal signal to be sampled, the selector 17 is instructed to select a signal specified by data in the data section. When the result of decoding is a command to rewrite the internal register of the integrated circuit 10, the register rewriting control block 16
B, D, and DSEL are controlled to rewrite corresponding internal registers. The integrated circuit 10 is connected to the port of the selector 17.
The internal signal lines to be measured are connected to each other, and a signal instructed by the data recorder 14 is selected from the internal signals input from these and output to the sampling block 15. Sampling block 15
Samples the signal input from the selector 17 using the signal CLK as a sampling signal, and outputs the result to the parallel / serial conversion block 12. The parallel / serial conversion block 12 converts the sampling result output from the sampling block 15 into serial data synchronized with the signal CLK and outputs the serial data from the SOUT pin to the outside of the integrated circuit 10.

In the internal signal observing circuit 1, the command newly input from the test apparatus 20 by the serial input signal SIN becomes valid sequentially, but after the output of the sampling result by the previous setting is completed, the new operation setting is performed. Is started.

FIG. 4 is a diagram showing an operation setting procedure by the internal signal observation circuit 1. FIG. 3 shows a case where the setting commands a, b, and c for the operation of designating an internal signal group and an internal signal group (the internal signal group will be described later) are successively input as serial inputs SIN from the test apparatus 20. It is shown. These instructions are decoded by the data decoder 14 and the contents of the instructions are sequentially set in the internal signal observing circuit 1. However, the setting is not immediately reflected in the processing, but the processing that has not been completed at the time of setting is completed. Later, it is reflected in the next processing. For example, if a new setting instruction is decoded while the sampling result is being output, this instruction becomes valid after outputting all the data being processed before decoding as the serial output signal SOUT, and becomes new in the next sampling processing. Sampling is performed according to various settings, and the sampling result is output as a serial output signal SOUT. At this time, when a plurality of internal signal groups are selected and set as sampling targets, these internal signal groups are sampled simultaneously. Then, after converting the result into serial data, a start bit and a stop bit are added and the serial output signal S
Output to OUT as OUT. In the case of the figure, the internal signal group and the three internal signal groups are designated as sampling targets, and sampling is performed on these internal signal groups simultaneously, and the result is output to the serial output SO.
Output as UT.

FIG. 5 shows an application example of the internal signal observation circuit 1 to an integrated circuit whose internal signal is to be observed. In the integrated circuit 10a of FIG. 5, the internal signal lines to be observed are directly connected to the ports of the internal signal observation circuit 1a, respectively, and whether or not the internal signal observation circuit 1a performs sampling for each of the internal signal lines is determined. Is specified individually. The internal signal observation circuit 1a is supplied with an operation clock BCLK of the integrated circuit 10a, and can output sampling data in synchronization with the internal operation clock BCLK.

The integrated circuit 10a shown in FIG. 5 has an internal circuit configuration divided into two internal circuit blocks 2a-1 and 2a-2, and an internal signal on a signal line between the internal circuit blocks 2a-1 and 2a-2. The internal signal observing circuit 1a is incorporated for observing and for changing the setting of the internal register 3a in the internal circuit block 2a-2. The internal signal lines to be observed are connected to the ports of the internal signal observation circuit 1a.

FIG. 6 shows an example of a command used as an instruction for the internal signal observation circuit 1. In the example shown in the figure, one command is composed of a 2-byte header and 2 bytes.
It consists of a byte data part. The header indicates the type of command, and in the example of FIG.
A synchronous / asynchronous switching command (0x) for switching between sampling and asynchronous in synchronization with K
aa: Here, 0x represents hexadecimal notation), a selection / cancellation command (0xb) for an internal signal group to be sampled
b), reset (0xcc), and command (0xee) for setting the internal register 3a.

The data part following the header part stores data used in each command. For example, when the header portion is a synchronous / asynchronous switching command, whether to set synchronously or asynchronously is designated by the following data portion. When the internal signal group is specified, the internal signal group to be selected and the selection / cancellation are specified by the data section. In the case of the command for rewriting the internal register 3a, the data section writes the command to the internal register 3a. Specify the data.

The test apparatus 20 converts these commands into serial data from the serial input SIN as serial data.
0a to give a control instruction to the internal signal observation circuit 1a.

FIG. 7 is an image diagram showing the sampling timing of the internal signal and the output timing of the sampling result. Each of the internal signals selected by the instruction from the test apparatus 20 is sampled using the signal CLK supplied from the CLK pin as a sampling signal. As the sampling signal CLK, a signal having a period of a fraction of a cycle to a hundredth of the cycle of the operation clock BCLK of the integrated circuit 10 is used.
The internal signal is a signal B based on the sampling signal CLK.
It is sampled and buffered a plurality of times during one LK cycle. For example, if the cycle of the operation clock BCLK is 5
In the case of 00 ns, the number of selected internal signal lines is 20, and the cycle of the sampling signal CLK is 10 ns, one signal can be sampled twice in one operation clock cycle. it can.

In the case of FIG. 7, the number of signals to be sampled is 2
This shows the timing of sampling when synchronous output is performed with four samplings. The sampling starts the first sampling after three cycles of a sampling CLK signal (not shown) counted from the rising edge of the operation clock BCLK. The sampling result is the internal signal observation circuit 1
a, the data is sequentially buffered, converted into serial data, and output from the SOUT pin to the outside. In the case of the figure, the first sampling result a of the internal signal a and the internal signal b
1, b1, the second sampling results a2, b2. . And are sequentially output as serial data SOUT. After all four sampling results have been output, the specific C
After waiting for an LK cycle and leaving an interval, the next sampling starts from the rising edge of the next operation clock BCLK.

Next, rewriting of the internal register 3a of the integrated circuit 10a will be described. FIG. 8 is an explanatory diagram of the rewriting of the internal register in the present embodiment. In the integrated circuit 10a of this embodiment, when it is necessary to temporarily change the set value of the internal register 3a, the internal signal observation circuit 1a operates the internal signals D, CKB, and DSEL to change the value of the internal register 3a. Can be rewritten.

The internal register 3a is a register which is read / written by the internal operation of the integrated circuit 10a. In FIG. 8, only one flip-flop FF is shown for one bit for the sake of simplicity. Further, the integrated circuit 10a may have a configuration having a plurality of internal registers. However, in order to avoid complicating the description, FIG. 8 shows a configuration having only one register as an example.

The data input D of the flip-flop FF constituting the internal register 3a is provided with the output DATA of the multiplex MUX which receives the two signals of the internal signal AAA of the integrated circuit 10a and the signal D from the internal signal observation circuit 1a. The value of the internal register 3a is rewritten by this data DATA. Multiplex MU
The output DATA of X is output to the integrated circuit 10 by the internal signal observation circuit 1a switching the level of the selection signal DSEL.
The internal signal AAA of a and the signal D from the internal signal observation circuit 1a are switched. The OR value of the internal operation clock BCLK and the signal CKB from the internal signal observation circuit 1a is input to the clock input CK of the flip-flop FF. During normal operation, the signal CKB is in the “L” state, and the internal operation clock BCLK is input to the clock input CK of the flip-flop FF.

During normal operation, the multiplex MUX
Output signal DATA outputs an internal signal AAA. When the internal register 3a is rewritten by an external command, the internal signal observation circuit 1a outputs data to be written to the internal register 3a from the signal D, and outputs the selection signal DS.
Operate EL output to output multiplex MUX D
ATA is switched to the signal D side. Then, when the internal operation clock BCLK is “L”, a one-shot pulse signal having an appropriate width is output as the signal CKB, and the data of the signal D is written to the flip-flop FF.

FIG. 9 is a timing chart of each signal in FIG. 8 when the internal register 3a is rewritten. Integrated circuit 10
a is a normal operation, the internal signal observation circuit 1a outputs the selection signal DS
EL and CKB are set to “L” and multiplex MU
X to the internal signal AAA side, and the internal operation clock B as the clock input CLKB of the flip-flop FF.
CLK is input as it is so that the internal register 3a is rewritten by the internal signal AAA in synchronization with the internal operation clock BCLK.

At the time of testing the integrated circuit 10a, it is necessary to set the value of the internal register 3a to a specific value. When a test instruction for changing the internal register is input from the test apparatus 20 as the serial input signal SIN, the internal signal observation circuit 1a Sets the DSEL signal to the corresponding internal register 3a to "H".
To Then multiplex MUX output DATA
Switches from the data from the internal signal AAA side to the signal D side from the internal signal observation circuit 1.

Next, after a specific CLK period from the falling edge of the internal operation clock BCLK, the internal signal observation circuit 1a
Outputs a pulse signal of a specific width as the signal CKB. When this is input to the flip-flop FF as the clock input CLKB, the flip-flop FF rewrites data at the rising edge of CLKB, and the output YYY, which is the value of the internal register 3a, is the data whose internal signal observation circuit 1a is rewritten by the signal D. (D data). The value of this output YYY is held at the value D data rewritten until the next rising edge of the internal operation clock BCLK, and after the rising edge of BCLK, the internal signal AAA is output.
(AAA dat)
Return to a).

FIG. 10 is a diagram showing a second application example of the internal signal observation circuit 1 to an integrated circuit to be observed. FIG.
The internal signal observing circuit 1b has an internal circuit configuration divided into three internal circuit blocks 2b-1, 2b-2, and 2b-3. As in the case of FIG. An internal signal observation circuit 1b is incorporated for observation.

In the second application example, the signals (lines) in the integrated circuit 10b are divided into a plurality of groups, and each group is made into one internal signal group. A method of selecting whether or not to perform sampling is adopted. This grouping is performed so that one group is formed for each of a plurality of related internal signals such as address lines and data lines.

In the integrated circuit 10b of FIG. 10, a plurality of internal signal lines between the internal circuit blocks 2 are divided into four internal signal groups, and the parallel-serial conversion circuit 5 is provided for each internal signal group.
Is provided. By inputting the output of the parallel-serial conversion circuit 5 to the port of the internal signal observation circuit 1b, the internal signal to be observed is changed to the internal signal observation circuit 1b.
It is connected to the. A plurality of internal signals are converted into serial data through the parallel-serial conversion circuit 5 and input to the port of the internal signal observation circuit 1b. Therefore, when selecting an internal signal group to be sampled based on an instruction from the test apparatus 20, the internal signal observation circuit 1b selects one or a plurality of ports from its own port, so that the internal signal observation circuit 1b transmits the signal through the parallel-serial conversion circuit 5. To select a group of internal signals connected to that port to enable sampling.

FIG. 11 is a diagram showing the sampling timing in the case of the second application example shown in FIG. When receiving the signal selection command from the serial input SIN, the internal signal observation circuit 1b selects a port corresponding to the internal signal group specified by the signal selection command and performs sampling. Then, the parallel data of the sampling result is converted into a serial signal in the order determined at the design stage for each port, and is output from the output pin SOUT to the outside as serial data. At this time, a start bit is added at the head of each output data, and a stop bit is added at the end. The length of the output data (the number of data) depends on the number of signals sampled, in other words, the number of selected ports and the number of internal signals input to each port.

After outputting all the sampled data as serial data from the output pin SOUT, after waiting for a specific CLK period and leaving an interval, the next sampling process is performed, and the signal from the selected port is sampled, and a series of data is sampled. Repeat the operation.

[0046]

According to the present invention, it is possible to realize an integrated circuit capable of observing the internal signal of the integrated circuit without providing a large number of external pins for observing the internal signal.

In the integrated circuit according to the present invention, the internal signals can be observed while other semiconductor circuits and electronic components are mounted on the printed circuit board on which they are mounted. The internal signal can be observed from the outside while reproducing. Therefore, normal operation is performed in a state of being mounted on a device, which has been difficult so far, and the internal signal at that time can be observed from the outside, so that accurately reproduced data can be obtained.

Further, since the internal signal can be observed with the peripheral device connected, it is possible to observe the influence of other devices. In the integrated circuit according to the present invention,
During the normal operation, the set value of the internal register of the integrated circuit can be changed to a value irrelevant to the value set by the normal operation.

With the above effects, in the integrated circuit according to the present invention, the efficiency of debugging and failure analysis can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing an outline of an embodiment.

2A is a diagram illustrating a configuration of a serial input signal SIN, and FIG. 2B is a diagram illustrating a configuration of a serial output signal SOUT.

FIG. 3 is a diagram illustrating a configuration example of an internal signal observation circuit.

FIG. 4 is a diagram showing an operation setting procedure by an internal signal observation circuit.

FIG. 5 is a diagram showing a first application example of an internal signal observation circuit to an integrated circuit to be observed.

FIG. 6 is a diagram illustrating an example of a command.

FIG. 7 is an image diagram showing sampling timing of an internal signal.

FIG. 8 is an explanatory diagram of rewriting of an internal register in the embodiment.

9 is a timing chart of each signal in FIG. 8 when the internal register 3a is rewritten.

FIG. 10 is a diagram showing a second application example of an internal signal observation circuit to an integrated circuit to be observed.

FIG. 11 is a diagram illustrating sampling timing in the case of a second application example.

FIG. 12 is a diagram showing an integrated circuit having a configuration in which the number of external pins is equal to the number of internal signals to be observed.

FIG. 13 is a diagram showing an integrated circuit having a configuration in which a pin for observing an internal signal is shared with other input / output pins.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Internal signal observation circuit 2, 101, 201 Internal circuit block 3 Internal register 4 Internal signal group 5 Parallel-serial conversion circuit 10, 100, 200 Integrated circuit 11 Serial / parallel conversion block 12 Parallel / serial conversion block 13 Setting register block 14 Data Decoder 15 Sampling Block 16 Register Rewrite Control Block 17 Selector 20 Test Device 202 Selector 203 Shared Output Pin 204 Test Mode Select Signal FF Flip-flop MUX Multiplex

Claims (6)

[Claims] An input unit for receiving an instruction as a serial signal from outside the integrated circuit; a sampling unit for sampling an internal signal based on the instruction; a parallel-serial conversion unit for converting a sampling result into serial data; Output means for outputting data to the outside of the integrated circuit. 2. The integrated circuit according to claim 1, further comprising an internal register value setting unit that sets an internal register value of the integrated circuit based on the instruction. 3. A method according to claim 1, wherein an instruction from outside the integrated circuit is received as a serial signal, an internal signal is sampled based on the instruction, a sampling result is converted into serial data, and the serial data is output to outside the integrated circuit. Internal signal verification method for an integrated circuit. 4. The method according to claim 3, wherein the internal signals to be sampled are individually designated. 5. The internal signal verification method for an integrated circuit according to claim 3, wherein a plurality of the internal signals are set as a signal group, and the internal signal to be sampled is specified for each signal group. 6. The method according to claim 3, wherein an internal register value of the integrated circuit is set based on the instruction.