JP2002247143A - Bit error insertion circuit of PN pattern generator - Google Patents

Abstract

(57) [Summary] A PN that enables a bit error insertion position to be set at an arbitrary position of a bit string constituting a PN pattern signal.
It is an object to provide a bit error insertion circuit of a pattern generator. A PN pattern generation unit for generating a PN pattern signal, an error insertion timing generation unit for generating a bit error insertion timing to be inserted into the PN pattern signal, and a bit error insertion signal to be inserted into the PN pattern signal , An error insertion position determination unit 14 that determines the bit position of a bit error to be inserted into the PN pattern signal, and an arbitrary bit string that forms the PN pattern signal while inserting the PN pattern signal into the input data. And a PN pattern / PN error insertion unit 3 for inserting a 1-bit bit error at the position of.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit error insertion circuit of a PN pattern generator, and more particularly, to a test signal at the time of an opening test of a transmission apparatus or at the time of checking the line quality at the time of maintenance work or the like. The present invention relates to a bit error insertion circuit of a PN pattern generator used for detecting a bit error of a PN pattern signal.

[0002]

2. Description of the Related Art In a TDM transmission apparatus or the like, at the time of an opening test or at the time of maintenance work, for each time slot (hereinafter referred to as TS) corresponding to each user of a frame signal,
A PN pattern signal serving as a test signal is inserted at one node, and the other node counts bit errors of the received PN pattern signal, thereby confirming the line quality. At this time, as a preprocessing, in order to recognize that the means for confirming the bit error of the received PN pattern signal is operating normally, when transmitting the PN pattern signal, the PN pattern signal is forcibly set to 1 in advance. A process for making a bit erroneous is performed, and the reception side detects that a 1-bit error has occurred in the PN pattern signal. This operation is appropriately performed manually by a maintenance person while checking the bit error occurrence state of the received PN pattern signal. Therefore, the insertion interval of a 1-bit bit error usually has an interval of several seconds or more. General. So, TDM
In a transmission device or the like, a circuit for inserting a 1-bit bit error at a required interval is added to a PN pattern generator.

FIG. 5 shows a configuration example of a bit error insertion circuit of a conventionally used PN pattern generator. The figure shows a case of a transmission device having a transmission rate of 8.192 Mbit / sec, in which one cycle of a clock of 8 kHz is defined as one frame. An 8-bit PN pattern is inserted into a specific TS, and a 1-bit PN pattern signal is inserted into a PN pattern signal. Insert a bit error. Therefore, the bit error insertion circuit of the PN pattern generator includes a PN pattern generation unit 1 for generating a PN pattern signal, an error generation unit 2 for generating a timing for generating a bit error, and a PN pattern signal inserted into input data. The PN pattern / PN error insertion unit 3 inserts a 1-bit bit error into a bit sequence forming a PN pattern signal.

The PN pattern generator 1 includes a PN TIM output circuit 4 for generating a PN pattern signal output timing signal, and a PN pattern generator 5 for generating a PN pattern signal. ERR ADD), a latch circuit 7 for holding the detected edge signal, and an AND circuit 8.
The N error insertion unit 3 includes an EXOR circuit 9 for making one bit of the bit string constituting the PN pattern signal erroneous, an AND circuit 10 for generating a timing for inserting the PN pattern signal into the input data, and a PN pattern signal for the input data. And a select circuit 11 to be inserted.

Referring to FIG. 5, a signal input / output to / from the bit error insertion circuit will be described. PNINS indicates a signal for generating a PN pattern signal, and TIM INS
Is a timing signal indicating the insertion position of the PN pattern signal, and DAT IN indicates a data input composed of a main signal. ERR ADD indicates an error insertion signal that operates asynchronously according to a software instruction, and 8MCLK indicates
8.192 Mbit / sec clock signal;
AT OUT indicates the data output of the main signal after the insertion of the PN pattern and the insertion of the bit error.

The operation of FIG. 5 will be described. In the PN pattern generation section 1, the PN INS signal is inverted in phase and TI
The PN TIM output circuit 4 outputs an output timing signal (PN TIM signal) of a PN pattern signal obtained by being input to the OR circuit together with the M INS signal, and controls the PN pattern generator 5 to generate an 8-bit P at a predetermined timing.
An N pattern signal is output. The error generator 2 detects the rising edge of the ERR ADD signal by the edge detection circuit 6 and holds the detection signal by the latch circuit 7. By inputting the held output and the PN TIM signal to the AND circuit 8, a timing signal for inserting a bit error into the PN pattern signal is generated and input to the EXOR circuit 9 of the PN pattern / PN error insertion unit 3.
The PN pattern / PN error insertion unit 3 determines the timing for inserting the PN pattern signal into the data input.
Under the control of the circuit 10, a PN pattern is inserted into the data input in the select circuit 11, and a bit error is inserted into the PN pattern signal at a predetermined timing in the EXOR circuit 9. The PN pattern signal is 1
PN pattern signal consisting of 8 bits for TS, PN pattern signal consisting of 16 bits for 2TS, 2 / 3TS
The bit length can be set, such as a 4-bit PN pattern signal.

[0007]

However, when a bit error insertion circuit using a conventional PN pattern generator inserts a 1-bit bit error into a PN pattern signal, the insertion timing forms one frame. Whenever it does not match the bit string range of the PN pattern signal inserted at an arbitrary position in the input data, a bit error is always inserted into the first bit of the PN pattern signal having a predetermined bit length.

FIG. 6 shows an operation image diagram of a bit error insertion circuit using a conventional PN pattern generator. Referring to the figure, (1) shows an 8 kHz clock signal, which transmits 1024 bits during one frame. (2) shows a position where an 8-bit PN pattern signal is inserted in a bit string constituting one frame, and (3) shows an attempt to insert a one-bit error in 1024 bits of one frame. This shows the timing position that was set. According to the display example of FIG. 6, the bit for which the bit error is instructed is the fourth bit B4 in the 1024 bits of one frame, but the PN of 8 bits is used.
Since the pattern signal is out of the range of the inserted bit string, the bit error cannot be directly inserted into the fourth bit. Therefore, in the above-described error generation unit that generates the bit error insertion timing, if the bit position where the bit error is inserted is out of the range of the bit string in which the 8-bit PN pattern signal is inserted, the bit error insertion is performed. Operation is performed using an 8-bit PN
When the bit string of the pattern signal is inserted into the PN pattern signal, the code is retained until the insertion position is reached. Was.

Since the bit error insertion instruction is arbitrarily specified within a range of 1024 bits, it is unlikely that the bit error insertion instruction is included in the bit string range of the 8-bit PN pattern signal. It is expected that the position will often be concentrated on the first bit of the 8-bit PN pattern signal. for that reason,
Since it is impossible to insert a bit error into an arbitrary bit of the 8-bit PN pattern signal, and the bit error is inserted into the first bit of the 8-bit PN pattern signal, the bit error is inserted into the PN pattern signal. There has been inconvenience in recognizing that the means for checking the bit error is operating normally. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem of the bit error insertion circuit of the PN pattern generator which has been conventionally used. It is an object of the present invention to provide a bit error insertion circuit of a PN pattern generator which can be set at an arbitrary position.

[0010]

To achieve the above object, a bit error insertion circuit of a PN pattern generator according to the present invention has the following configuration. P according to claim 1
The bit error insertion circuit of the N pattern generator is a bit error insertion circuit which is inserted into the main signal when checking the line quality between the transmission devices and is inserted into the PN pattern signal used as a test signal, and which is output at a predetermined timing. A PN pattern generating unit for generating a PN pattern signal and a PN pattern signal output timing signal;
An error insertion timing generator for generating a bit error insertion timing signal to be inserted into the pattern signal; an error generator for generating a bit error insertion signal to be inserted into the PN pattern signal; and a bit error bit to be inserted into the PN pattern signal An error insertion position determining unit for determining a position; a PN pattern signal inserted into input data;
A PN pattern / PN error insertion unit that inserts a 1-bit bit error at an arbitrary position in a bit string forming the N pattern signal.

According to a second aspect of the present invention, in the bit error insertion circuit of the PN pattern generator, the PN pattern generation section inputs a PN pattern generation signal and a PN pattern insertion position timing signal to a logic circuit and outputs a PN pattern signal output timing signal. A PN TIM output circuit for outputting,
A PN pattern generator that outputs a PN pattern signal having a predetermined bit length at a predetermined timing.

According to a third aspect of the present invention, there is provided a bit error insertion circuit of the PN pattern generator, wherein the error insertion timing generation section detects a rising edge of a frame period of input data constituted by a plurality of time slots; A first latch circuit that holds the edge signal in synchronization with a clock signal for a predetermined time, a PN pattern signal that receives the holding signal output by the first latch circuit and the PN pattern signal output timing signal, A first AND circuit that generates an insertion start timing signal, and a first counter circuit that counts the number of bits of the PN pattern signal by counting a clock signal after loading a counter with the PN pattern signal insertion start timing signal. , The output of the first counter circuit and a second By comparing the count value of the printer circuit output constituted by the comparator circuit the count value and outputs the generated bit error insertion timing signal matching timing.

According to a fourth aspect of the present invention, in the bit error insertion circuit of the PN pattern generator, the error generation section detects an edge detection circuit for detecting a rising edge of the error insertion signal, and synchronizes the detected edge signal with a clock signal. A second latch circuit and a DFF circuit for holding for a predetermined time, a PN pattern signal which receives a holding signal output from the DFF circuit, the PN pattern signal output timing signal, and a bit error insertion timing signal output from the comparison circuit; And a second AND circuit that generates a bit error insertion signal for inserting a bit error into the data.

6. The bit error insertion circuit of a PN pattern generator according to claim 5, wherein said error insertion position determination section receives said PN pattern signal insertion start timing signal and said bit error insertion timing signal and outputs a second counter circuit. And a third AND circuit for loading the PN
A second counter circuit which receives a pattern signal insertion start timing signal, counts a clock signal, and determines a bit error insertion position to be inserted into the PN pattern signal.

According to a sixth aspect of the present invention, in the bit error insertion circuit of the PN pattern generator, the PN pattern / PN error insertion section inputs the PN pattern signal and the bit error insertion signal and converts predetermined bits of the PN pattern signal. An EXOR circuit for making one bit wrong; a fourth AND circuit for receiving the PN pattern generation signal and the PN pattern insertion position timing signal and generating a timing for inserting the PN pattern signal into the main signal;
And a select circuit for selecting and outputting input data or a PN pattern signal including a bit error by controlling the output signal of the circuit.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on illustrated embodiments. FIG. 1 is a configuration diagram showing one embodiment of a bit error insertion circuit of a PN pattern generator according to the present invention. The figure shows a transmission rate of 8.192 Mbit / s, where one cycle of a clock of 8 kHz is one frame.
ec shows a case of a transmission device, in which an 8-bit PN pattern is inserted into a specific TS and a 1-bit error is inserted at an arbitrary position of the PN pattern signal. Therefore, the bit error insertion circuit of the PN pattern generator includes a PN pattern generation unit 1 for generating a PN pattern signal and an error insertion timing generation unit 12 for generating a bit error insertion timing to be inserted into the PN pattern signal.
An error generation unit 13 that generates a bit error insertion signal to be inserted into the PN pattern signal; an error insertion position determination unit 14 that determines the bit position of the bit error to be inserted into the PN pattern signal; And a PN pattern / PN error insertion unit 3 that inserts a 1-bit bit error at an arbitrary position in a bit string forming the PN pattern signal.

The PN pattern generating section 1 has a PN TIM output circuit 4 for generating the output timing of the PN pattern signal and a P / N circuit for generating an 8-bit PN pattern signal.
An error insertion timing generator 12 includes an N pattern generator 5, an edge detection circuit 15 for detecting a rising edge of an 8k clock signal (8kCLK), and a first latch circuit for holding the detected edge signal for a predetermined time. 16, a first AND circuit 17 constituting a predetermined logic circuit, a first counter circuit 18 for counting the number of bits of the PN pattern signal, and a comparison for generating a bit error insertion timing to be inserted into the PN pattern signal. Circuit 1
9 and the error generation unit 13 outputs the error insertion signal (E
An edge detection circuit 20 for detecting a rising edge of the RR ADD), a second latch circuit 21 and a DFF circuit 22 for holding the detected edge signal for a predetermined time,
A second AND circuit 23 that generates a bit error insertion signal that is output when a bit error is inserted into the pattern signal.

The error insertion position determining unit 14 includes a third AND circuit 24 constituting a predetermined logic circuit, and a second counter circuit 25 for determining a bit position of a bit error to be inserted into the PN pattern signal. The PN pattern / PN error insertion section 3 includes an EXOR circuit 9 for erroneously changing one bit constituting the PN pattern signal and a fourth AND circuit 1 for generating a timing for inserting the PN pattern signal.
0 and a select circuit 11 for inserting a PN pattern signal into input data.

In FIG. 1, signals input to and output from the bit error insertion circuit will be described. PNINS indicates a signal for generating a PN pattern signal, and TIM INS indicates
This is a timing signal indicating the insertion position of the PN pattern signal, and DAT IN indicates a data input composed of a main signal. ERR ADD indicates an error insertion signal that operates asynchronously under the instruction of software, and 8kCLK indicates 8
kHz clock signal, 8MCLK is 8.19
A clock signal of 2 Mbit / sec.
The UT indicates the data output of the main signal after the insertion of the PN pattern signal and the insertion of the bit error.

Next, the operation of FIG. 1 will be described with reference to the operation image diagram of the bit error insertion circuit of the PN pattern generator according to the present invention shown in FIG. FIG. 2 (1)-
(3) shows a bit arrangement diagram in one frame configuration,
(4) is an explanatory diagram of a counter provided for determining a bit error insertion position. First, according to an external instruction, a TS position where a PN pattern signal is to be inserted is set,
The PN pattern signal is inserted at the position shown in (2).
The counter shown in (4) is a counter that advances by one for each frame. When the PN pattern signal to be inserted is 8 bits, it is an 8 count counter. Therefore, the value that can be taken by the counter is set to 0 to 7 and corresponds to the bit error insertion position shown in (3). Therefore, when a bit error insertion of 1 bit is instructed from the outside, the value of the counter indicated by the insertion instruction decision point becomes the bit position where the bit error is inserted, and in FIG. Therefore, the logic of the fourth bit of the PN pattern signal shown in (3) is inverted, and a bit error is inserted into the PN pattern signal. Therefore, the selection of the insertion position of the bit error depends on the number of bits constituting the PN pattern signal.
This is performed within a bit, and a bit error is inserted at a predetermined position with respect to the PN pattern signal after the bit error insertion instruction timing. Naturally, when the insertion of the PN pattern signal is 16 bits, the range that the counter can take is 0 to 15, and if the range that the counter can take is varied according to the number of bits of the PN pattern signal to be inserted, Good.

Next, the operation of FIG. 1 will be described with reference to the timing charts of FIGS. FIG. 3 is a timing chart showing an operation of inserting a PN pattern signal in the bit error insertion circuit of the PN pattern generator according to the present invention. FIG. 6 is a timing chart illustrating an operation of inserting a bit error. Displayed in the signal name of the timing chart ()
The alphabets enclosed by are the Ps according to the present invention shown in FIG.
In the configuration diagram showing an embodiment of the bit error insertion circuit of the N pattern generator, input / output signals and signals identical to the alphabets enclosed in parentheses () displayed on the input / output section of each component are shown.

An operation for inserting an 8-bit PN pattern signal into input data composed of a main signal will be described with reference to FIGS. The PN pattern generation unit 1
(A) PN INS signal is inverted, (b) TIM
The PN TIM signal, which is the output timing signal of the PN pattern signal obtained by inputting the PN signal to the OR circuit together with the INS signal, is output from the PN TIM output circuit 4, and the PN pattern generator 5 is controlled at a predetermined timing ( d)
Outputs PN OUT signal. The PN pattern / PN error insertion unit 3 normally selects the input data (e) DAT IN signal composed of the main signal and outputs it as (f) DAT OUT in the select circuit 11, but the fourth AND (A) PN INS which is an input signal of the circuit 10
And (b) operate the select circuit 11 at the timing when both TIM INS are logic “1”, and
A PN pattern signal is inserted through the R circuit 9 and (f) D
Output as ATOUT.

Next, the operation of inserting a 1-bit error into the 8-bit PN pattern signal inserted into the input data will be described with reference to FIGS. In the error insertion timing generator 12, (g) the rising edge of the 8 kCLK signal is detected by the edge detection circuit 15, and (i) the 8 kCLK edge detection signal is input to the first latch circuit 16. The first latch circuit 16 has (h) 8
In synchronization with the MCLK signal, it is set by inputting (i) the logic "1" of the 8kCLK edge detection signal, and (c) the logic "1" of the PN TIM signal.
At the timing of (1), and becomes the (j) latch 1Q signal. Further, (j) latch 1Q signal and (c) PN
A timing signal for inputting the TIM signal to the first AND circuit 17 and starting insertion of the PN pattern signal (k)
The latch 1Q outputs a PN TIM signal.

On the other hand, the error generator 13 detects (l) the rising edge of the error insertion signal (ERR ADD) by the edge detection circuit 20 and obtains (m) the obtained ERR AD.
The D edge detection signal is input to the second latch circuit 21.
The second latch circuit 21 is set by inputting the logic "1" of the (m) ERR ADD edge detection signal in synchronization with the (h) 8MCLK signal, and the (k) latch 1Q. Reset with the PN TIM signal (n) Output the latch 2Q signal. When the logic of the (k) latch 1Q · PN TIM signal is “1”, the DFF circuit 22 outputs the (n) latch 2Q signal and outputs a “1” (p) DFF output signal, and outputs a bit. This is one of conditions for generating an error insertion signal.

Next, the first counter circuit 18 provided in the error insertion timing generator 12 is provided with the (k) latch 1
After the count “0” is loaded by the Q · PN TIM signal, when the (c) PN TIM signal is logic “1”, (h) counts the 8MCLK signal and (q) outputs the counter 1Q signal. Therefore, in this embodiment,
It counts from "0" to "7" and stops. Also, a second counter 25 provided in the error insertion position determination unit 14
(H) When the logic of the (1) latch 1Q PN TIM signal is "1", (h) count the 8MCLK signal for one clock and (r) output the counter 2Q signal and stop.
The time chart shown in FIG. 4 shows, as an example, a case where the counter value becomes “2” after counting for one clock,
This counter advances one count for each frame, and "7"
Is counted and loaded to "0".

Therefore, the error insertion timing generator 12
In the comparison circuit 19 provided in (1), the (q) counter 1
At the timing when the Q signal and the (r) counter 2Q signal are input and the counter value output from the second counter circuit 25 matches the counter value output from the first counter circuit 18, (s ) Output a comparison signal. FIG.
In the timing chart, the fourth bit of the 8-bit PN pattern signal corresponds to the timing. Further, in the second AND circuit 23 provided in the error generating unit 13, the (c) PN TIM signal and the (p) D
The timing at which the FF output signal and the (s) comparison signal are input and the logic of the three input signals are both "1" is a timing signal for inserting a 1-bit bit error into an 8-bit PN pattern signal. , PN pattern / PN
The data is input to an EXOR circuit 9 provided in the error insertion unit 3.

Therefore, (d) EXO receiving the PN OUT signal and the output signal of the second AND circuit 23
The R circuit 9 sets the output logic of the second AND circuit 23 to “1” at the timing of inserting the bit error,
(D) 4 of the PN OUT signal located at that timing
After inverting the logic of the bit and inserting a bit error, the select circuit 11 outputs it as a (f) DAT OUT signal. In this embodiment, the case where the PN pattern signal is 8 bits for 1TS has been described. However, in the same embodiment, a PN pattern signal consisting of 16 bits for 2TS and a PN pattern consisting of 24 bits for 3TS. It is possible to insert a 1-bit bit error into a (8-bit × N) -bit bit string such as a pattern signal.

[0028]

The conventional bit error insertion circuit has a high probability of inserting a bit error into the first bit of the PN pattern signal, and tends to be a biased test. P, 1, 2, 3, 4, 5, 6
Bit errors can be inserted with the same probability in all bit positions of the N pattern signal, and the additional circuit is only a counter and a peripheral circuit.
It is possible to exert a great effect in operating a DM transmission device or the like.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a bit error insertion circuit of a PN pattern generator according to the present invention.

FIG. 2 is a diagram showing an operation image of a bit error insertion circuit of the PN pattern generator according to the present invention.

FIG. 3 is a timing chart showing an operation of inserting a PN pattern signal in the bit error insertion circuit of the PN pattern generator according to the present invention.

FIG. 4 is a timing chart showing an operation of inserting a bit error in the bit error insertion circuit of the PN pattern generator according to the present invention.

FIG. 5 is a configuration example of a bit error insertion circuit of a conventionally used PN pattern generator.

FIG. 6 shows an operation image diagram of a conventional bit error insertion circuit using a PN pattern generator.

[Explanation of symbols]

1. PN pattern generation unit, 2. Error generation unit, 3. PN pattern / PN error insertion unit, 4. P
N TIM output circuit, 5 PN pattern generator, 6 edge detection circuit, 7 latch circuit, 8 AND circuit, 9 ......
EXOR circuit, 10-AND circuit (fourth AND circuit), 11-select circuit, 12-error insertion timing generator, 13-error generator,
14. Error insertion position determining unit, 15 Edge detection circuit, 16 first latch circuit,
17 ··· first AND circuit, 18 ··· first counter circuit, 19 ·· comparison circuit, 20
..Edge detection circuits, 21. · Second latch circuits,
22 ··· DFF circuit, 23 ··· second AND circuit,
24..third AND circuit, 25..second counter circuit

Claims (6)

[Claims] A bit error insertion circuit for inserting a PN pattern signal into a PN pattern signal to be used as a test signal when checking the line quality between transmission apparatuses, wherein the PN pattern signal having a predetermined bit length and output at a predetermined timing. A PN pattern generation unit for generating a PN pattern signal output timing signal; an error insertion timing generation unit for generating a bit error insertion timing signal to be inserted into the PN pattern signal; and a bit error insertion signal to be inserted into the PN pattern signal An error generation unit that performs the operation, an error insertion position determination unit that determines the bit position of a bit error to be inserted into the PN pattern signal, and a PN pattern signal that is inserted into the input data and 1 is placed at an arbitrary position in the bit string that constitutes the PN pattern signal. PN pattern / PN error insertion to insert bit error of bit And a bit error insertion circuit of the PN pattern generator. 2. A PN TIM output circuit for inputting a PN pattern generation signal and a PN pattern insertion position timing signal to a logic circuit and outputting a PN pattern signal output timing signal; PN that outputs PN pattern signal of bit length
2. The bit error insertion circuit of the PN pattern generator according to claim 1, wherein the bit error insertion circuit is constituted by a pattern generator. 3. The error insertion timing generator includes an edge detection circuit for detecting a rising edge of a frame period of input data constituted by a plurality of time slots,
A first latch circuit for holding the detected edge signal in synchronization with a clock signal for a predetermined time; and a holding signal output by the first latch circuit and the PN pattern signal output timing signal to input a PN pattern signal. A first AND circuit for generating a signal insertion start timing signal; and a PN by counting a clock signal after loading a counter with the PN pattern signal insertion start timing signal.
A first counter circuit that counts the number of bits of the pattern signal, and compares the count value of the output of the first counter circuit with the count value of the output of a second counter circuit, which will be described later, to generate timing at which the count values match, and to insert a bit error. 3. A bit error insertion circuit for a PN pattern generator according to claim 1, wherein said bit error insertion circuit comprises a comparison circuit for outputting a timing signal. 4. An error detecting section comprising: an edge detecting circuit for detecting a rising edge of an error insertion signal; a second latch circuit and a DFF circuit for holding the detected edge signal for a predetermined time in synchronization with a clock signal And a holding signal output by the DFF circuit, the PN pattern signal output timing signal, and a bit error insertion timing signal output by the comparison circuit, and a bit error insertion signal for inserting a bit error into the PN pattern signal. 4. A bit error insertion circuit for a PN pattern generator according to claim 1, wherein said bit error insertion circuit comprises a second AND circuit for generating. 5. An error insertion position determination unit, comprising: a third AND circuit that inputs the PN pattern signal insertion start timing signal and the bit error insertion timing signal and loads a second counter circuit; 5. A second counter circuit which receives a signal insertion start timing signal, counts a clock signal, and determines a bit error insertion position to be inserted into a PN pattern signal. Bit error insertion circuit of PN pattern generator. 6. The PN pattern / PN error insertion section,
An EXOR circuit that inputs the PN pattern signal and the bit error insertion signal and erroneously corrects a predetermined bit of the PN pattern signal by one bit, and receives the PN pattern generation signal and the PN pattern insertion position timing signal and outputs
A fourth AND circuit for generating a timing for inserting the N pattern signal into the main signal, and a PN including input data or bit error controlled by an output signal of the fourth AND circuit.
6. A bit error insertion circuit for a PN pattern generator according to claim 1, further comprising a selection circuit for selecting and outputting a pattern signal.