JP2002261237A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-precision resistance value, have heat resistance and oxidation resistance, make a good connection with a wiring layer, and to easily manufacture at relatively low manufacturing cost. Provided is a semiconductor device having a high-resistance thin-film resistance element having a possible structure, and a method for manufacturing the same. The resistive film is made of a silicon cermet material.
3 and a thin-film resistance element 10 formed by laminating at least an insulating protective film 4 on the resistance film 3, and the silicon cermet material is
An insulating layer made of a composition containing silicon and at least one element selected from oxygen, nitrogen, and carbon in one or more metal elements, wherein a wiring 11 electrically connected to the thin-film resistance element 10 covers the thin-film resistance element 10 Through the opening formed in 5,
A semiconductor device directly connected to the resistance film 3 is formed.
A step of forming the resistive film 3; a step of continuously forming the insulating protective film 4 on the resistive film 3 in the same apparatus as the step of forming the resistive film 3; The semiconductor device is manufactured by including a step of forming the thin-film resistance element 10 by patterning the insulating protective film 4 collectively and a step of forming the insulating layer 5 covering the thin-film resistance element 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a thin film resistance element. In particular, high resistance (> 0.5
(kΩ / □) is required to be mounted on a semiconductor device having an analog circuit function including bipolar elements or a so-called BiCMOS semiconductor device having an analog / digital circuit function including bipolar transistors and MOS transistors. The present invention relates to a semiconductor device suitable for application.

[0002]

2. Description of the Related Art When forming a resistive element in a semiconductor device having an integrated circuit, the types of resistive elements used include (1) a diffused resistive element, (2) a field effect resistive element, and (3) a thin film multi-layer. Crystal silicon resistance element (4) Thin film metal resistance element.

(1) A diffusion resistance element is formed by doping a semiconductor substrate with an impurity of N-type or P-type conductivity and performing a heat treatment. The resistance value of the diffusion resistance element depends on the diffusion length of the impurity, the diffusion width, the diffusion depth, and the resistivity of the diffusion material. The resistivity of the diffusion material is characterized by depending on the junction profile between the dopant and the dopant species after the high-temperature heat treatment. (2) The field-effect resistance element is a resistance element using a transistor used in a depletion mode, and is characterized in that the resistance value is adjusted by ion implantation for controlling the threshold voltage of the transistor. (3) The thin-film polycrystalline silicon resistance element is formed by doping a polycrystalline silicon film with an impurity having a conductivity type of N-type or P-type and performing heat treatment. (4) The thin film metal resistance element is formed of a resistive metal material film formed on an insulating material. The thin-film metal resistance element has been particularly useful in an LSI that requires a high sheet resistance in a circuit.

In a conventional digital circuit, a polycrystalline silicon film doped with an impurity has been used as a resistor material. However, especially in analog circuits,
A lower temperature coefficient of resistance is required as compared to digital circuits. Therefore, thin-film metal resistance elements having high accuracy and high reliability have been adopted. As a material of such a highly accurate and highly reliable thin film metal resistance element, nickel chromium (NiCr), tantalum nitride (TaN), chromium silicide (CrS
i ₂ ), chromium silicon oxy (CrSiO) and the like are known.

In recent years, with the increase in the degree of integration of semiconductor devices, miniaturization of resistance elements has been required.
CrSiO and CrSi _{2 from} which a high specific resistance of about Ωcm can be easily obtained are often used. As a result, a required high resistance value is ensured. Incidentally, the specific resistance of the above materials is as follows: CrSiO is 1000 to 4000 μΩ.
cm, 500-2000 μΩcm of CrSi ₂ , TaN
Is about 100 μΩcm, and NiCr is about 50 μΩcm.

A conventional miniaturized thin-film resistance element is formed by forming a resistance element such as C on an insulating film on a semiconductor substrate.
The thin film pattern made of the rSi ₂ film is provided to extend, and the structure has a structure in which aluminum wiring made of aluminum or its alloy is directly in contact with both ends of the thin film pattern made of the CrSi ₂ film.

Further, when a particularly low resistance temperature coefficient is required for a thin-film metal resistance element formed on a silicon semiconductor substrate, CrSiN is preferably used as the material.
Membranes are often used. This CrSiN film has high resistance and is easy to form by sputtering or etching, and the doped polycrystalline silicon film has a resistance temperature coefficient of 1000 ppm.
/ ° C or higher, whereas the CrSiN film is 100 ppm
It has been used frequently because of its low temperature coefficient of resistance of / ° C.

However, the above four types of resistance elements have the following problems.

The diffusion resistance element and the field effect resistance element are
While each has the advantage of being easily integrated into the semiconductor integrated circuit manufacturing process, it has many disadvantages. In particular, since these resistance elements have the same parameters that control the resistance as those that must be optimized for the device performance of the semiconductor integrated circuit, the resistance is restricted, and it is difficult to freely design the resistance. Has become. Therefore, when a diffused resistance element or a field-effect resistance element is formed in an actual semiconductor integrated circuit, the device performance is prioritized. As a result, only a low resistance value can be obtained with these resistance elements due to the above-mentioned parameter restrictions. further,
The diffusion resistance element requires a relatively large space, and thus has a disadvantage that it hinders integration and miniaturization of the semiconductor integrated circuit.

On the other hand, polycrystalline silicon resistance elements are currently most widely employed as resistance elements for semiconductor integrated circuits. However, there are many factors that compose the carrier conduction mechanism in polycrystalline silicon, and it is complicated, and is subject to a large variation due to the influence of the heat treatment in other processes, and tends to be remarkable particularly on the high resistance side. Is not enough and the temperature coefficient of resistance (~ 2000ppm / ℃)
Has become an issue.

[0011] In addition, the CrSi-based material most widely used in the thin film metal resistance element is very liable to be oxidized. In a manufacturing process of a CrSi-based resistance element, a patterned resistance film (CrSi
In many cases, the base material film is directly exposed to an oxygen atmosphere or oxygen plasma. For this reason, oxidation or alteration occurs on the surface of the resistance film. If the aluminum film wiring is formed directly on the surface of the oxidized or deteriorated resistance film, the contact resistance becomes large and the conduction becomes unstable. Therefore, in order to remove the altered layer on the surface of the resistive film, the surface of the resistive film and the surface of the semiconductor wafer are also washed with a diluted hydrofluoric acid aqueous solution. However, even if the surface of the resistive film is cleaned as described above, it is difficult to make the contact resistance sufficiently low and stable. For example, since the CrSiN film is very easily oxidized, even after the surface is cleaned, a thin chromium oxide or the like is formed as a natural oxide film between the wiring film material laminated on the CrSiN film,
The conduction between the wiring material and the resistive film often becomes unstable.

Further, C is used as a material for the thin film metal resistance element.
In a conventional thin film resistor using an rSi ₂ film, CrSi
₂ has a problem that the resistance value greatly changes at a temperature near 360 ° C., and the resistance value largely fluctuates due to a heat treatment process performed after the thin film resistance element is formed until the semiconductor device is completed.

On the other hand, a CrSiO film is desirable as a material of the resistive film itself because it has high thermal stability and a small change in resistance due to a heat treatment step after forming the resistive element. However, this CrSiO film has a problem that it is difficult to make a good electrical connection with a wiring layer formed by laminating an aluminum alloy, and there is a problem that the initial resistance value varies greatly due to the contact resistance of the connection portion. Since a complicated element structure and complicated manufacturing steps are required, an increase in manufacturing cost is a major issue.

Further, many of the conventional thin film resistance elements use a nichrome alloy or tantalum nitride. However, since these materials have low specific resistance, the resistance film must be thinned to obtain a high specific resistance. Therefore, there is a problem that thermal stability is deteriorated when the thickness is reduced. Therefore, as a material having a high specific resistance, a thin film resistance element made of an alloy of chromium and silicon has been proposed. However, this alloy material also has a problem that the resistance value changes when heat is applied.

In order to solve the above-mentioned problems of the conventional resistance elements, various configurations and manufacturing methods of the resistance elements have been proposed (for example, Japanese Patent Application Laid-Open Nos. 6-5787 and 5-19).
0547, JP-A-7-245303, JP-A-7-2
02124), all of which have disadvantages such as a significant increase in manufacturing cost and deterioration in resistance accuracy, and are not practically sufficient.

[0016]

SUMMARY OF THE INVENTION To avoid the above problems,
In addition, the characteristics required especially for a high-resistance resistance element, that is, high resistance (> 2.0 kΩ / □), low temperature coefficient of resistance (<
± 200 ppm / ° C), high-precision resistance, heat resistance (45
It is required to satisfy all the requirements such as about 0 ° C.), oxidation resistance (up to about 450 ° C.), and stability with time.

Therefore, as materials meeting these requirements, (M + SiO ₂ ), (M + SiN), (M + SiN)
It is conceivable to form a high-resistance thin-film resistance element using a silicon cermet material (a composite material of an insulating material and a metal material) having a composition such as C) (M is a metal element).

Of these silicon cermet materials,
For example, Ta-SiO ₂ cermet, the sheet resistance to 10
kΩ / □, temperature coefficient of resistance <± 100 ppm / ° C., heat resistance up to 600 ° C., oxidation resistance up to 600 ° C., and insulating film SiO ₂ widely used in semiconductor manufacturing equipment It has the feature that the adhesion is very good with both the system and SiN-based materials.

However, when the above-mentioned silicon cermet material is used for a thin-film resistance element, there is a problem that the configuration of the other conventional resistance element described above cannot be applied as it is. The biggest problem is a problem in the manufacturing process with a silicon-based insulating film widely used at present in general semiconductor devices. In particular, when an attempt is made to form a silicon cermet material thin film (thickness: 10 nm to 100 nm) as a resistive film, the silicon cermet material, the composition and the constituent elements are used as an underlayer of the resistive film or an interlayer insulating layer covering the resistive film. Since a structure sandwiched between silicon-based insulating layers (SiO ₂ -based and SiN-based materials) that are very similar cannot be avoided, it is difficult to ensure etching selectivity between these silicon-based insulating layers and a resistive film made of a silicon cermet material. It has become.

As a result, the difficulty in the step of forming a contact region connecting the wiring layer and the resistance element increases, and this is the greatest problem to be realized.

Here, a problem that occurs when a silicon cermet material is applied to a thin-film resistance element will be described with reference to a specific configuration. As a structure when a silicon cermet material is applied to a thin-film resistance element, first, as shown in FIG. 22, a thin-film resistance element 70 is formed by a resistance film 73 made of a silicon cermet material, and a silicon-based insulating material covering the thin-film resistance element 70 is formed. The contact portion 77 of the wiring 77 (the base film 75 and the wiring layer 76) is formed through the connection hole formed in the layer 74.
A structure in which C is connected is conceivable. Such a structure is, for example, a structure that is often used in the above-described thin-film polycrystalline silicon resistance element. When this structure is adopted, since the etching selectivity between the silicon-based insulating layer 74 and the resistive film 73 made of the silicon cermet material cannot be obtained, over-etching is performed when the insulating layer 74 is etched to form a connection hole. Contact part 77 of wiring 77
The resistive film 73 under C is partially cut away and becomes thin.
As a result, the contact resistance increases, and the fluctuation of the resistance value of the thin-film resistance element 70 due to the contact resistance increases.

On the other hand, instead of forming a connection hole in the insulating layer 74 on the resistance film 73, a method of forming a wiring layer on the resistance film 73 and patterning the wiring layer to form a wiring 77 can be considered. In this case, patterning of the wiring layer is performed by a wet process using an etching solution or a dry process such as plasma etching.

First, when patterning the wiring layer by wet processing, as shown in FIG.
A wiring layer 78 is formed directly on the substrate 3 and is selectively etched by a wet process using an etching solution to pattern the wiring layer 78 to form a wiring. In this case, the wiring layer 78 is limited to a material that can be wet-processed, and it becomes impossible to employ a Ti-based barrier metal layer. Further, the surface of the resistance film 73 is damaged by the etching solution, which causes a change in the resistance value of the thin-film resistance element 70. Further, the resistance value is defined by the distance L between the wirings connected to both sides of the resistance film 73. In the wet processing, the position of the end face 78A of the wiring layer 78 is controlled to control the distance L between the wirings with high precision. Is difficult, and there is a problem in accuracy of the resistance value.

In the case where the wiring layer is patterned by dry processing, as shown in FIG.
The wiring 77 can be formed by directly forming a laminated film of the base film 75 and the wiring layer 76 on the upper surface and then performing patterning by plasma etching. in this case,
It is possible to use a Ti-based barrier metal layer as the base film 75. In this case, the surface of the resistive film 73 is damaged (eg, becomes thin as shown in FIG. 23B) by the damage of active radicals or incident ions in the plasma, which causes a change in the resistance value of the thin-film resistive element 70. Especially R
The effect of ion damage due to IE (reactive ion etching) on the surface of the resistive film 73 cannot be ignored.

Therefore, in the configuration in which the wiring 77 is formed on the resistance film 73, as shown in FIG. 24, a protection film 79 made of an insulating material is laminated on the resistance film 73, and
A configuration is conceivable in which the resistance film 73 and the wiring 77 are connected via the wiring 9. By laminating the protective film 79, it is possible to prevent the surface of the resistive film 73 from being damaged by plasma, a chemical, or the like. In the case of manufacturing the configuration shown in FIG. 24, after a protective film 79 is laminated on the resistance film 73, a base film 75 and a wiring layer 76 are formed so as to cover the protection film 79, and the base film 75 and the wiring layer 76 are patterned. Then, the wiring 77 is formed.
In this patterning, the resistive film 73 is formed by the protective film 79.
Surface damage can be avoided. Further, since it is necessary to separate the connection portions with the wirings 77 on the left and right in order to form the thin film resistance element 70, the protective film 79 between them (at the center) is removed. At this time, when the protective film 79 is an insulating material that can easily secure an etching selectivity with the resistive film 73, the resistive film 73 can function as an etching stopper when removing the protective film 79. As a result, the contact resistance with the wiring 77 is significantly increased. On the other hand, if a conductive material is used for the protective film 79,
Since the protective film 79 can secure etching selectivity with respect to the wiring 77 and the resistive film 73, the protective film 79 is simultaneously etched when patterning the wiring 77, or resisting when removing the central protective film 79. The film 73 may be damaged.

Next, the configuration shown in FIG. 25 uses two processing masks for etching to ensure the accuracy of the resistance value and to prevent the protective film 79 from damaging and damaging the resistance film 73. Is made possible. When the structure shown in FIG. 25 is manufactured, the protective film 79 is formed on the resistance film 73.
Are stacked, and the base film 75 and the wiring layer 76 are
Is formed, and the wiring layer 76 is patterned to form the wiring 77. A wet process is used for patterning the wiring layer 76, and the end face 76A of the wiring layer 76 is curved. At this time, the resistive film 73 is protected by the protective film 79 from the wet etching chemical. Subsequently, the mask used for patterning the wiring layer 76 is removed, and a mask having a smaller opening is formed again. Using the mask having a small opening, the base film 75 and the protective film 79 at the center are used.
Is removed. Since the interval L between the wirings 77 is defined by a mask having a small opening instead of a wet process, high accuracy of the resistance value of the thin-film resistance element 70 can be secured. However, in this case, a complicated manufacturing process such as reattachment of the mask is required, and there is a problem that the manufacturing cost is increased.

The structure shown in FIG. 26 is an improvement of the structure shown in FIG. 22. A conductive etching stopper layer 80 is formed under a resistive film 73 in a contact portion between a wiring 77 and a thin-film resistance element 70. In addition, it has a partially laminated structure with the resistance film 73. When a connection hole is formed in the insulating layer 74 by the etching stopper layer 80, the connection hole stops at the etching stopper layer 80. Then, the wiring 78
And the etching stopper layer 80 and the resistance film 73 are electrically connected. Since the etching stopper layer 80 is conductive, the contact resistance with the wiring is small. However,
In this case, the resistance film 73 has a step, and the coverage of the step becomes a cause of a change in the resistance value. In addition, since the number of etching stopper layers 80 increases, a complicated manufacturing process is required also in this case, resulting in an increase in manufacturing cost.

In order to solve the above-mentioned problems, in the present invention, the resistance value is high, the heat resistance and the oxidation resistance are good, the connection with the wiring layer can be made well, and the manufacturing cost is relatively low. An object of the present invention is to provide a semiconductor device having a high-resistance thin-film resistance element having a structure that can be easily manufactured at low cost, and a method of manufacturing the same.

[0029]

According to the present invention, there is provided a semiconductor device comprising:
It has a thin film resistance element formed by stacking at least a resistive film made of a silicon cermet material and an insulating protective film on the resistive film. The silicon cermet material contains oxygen, nitrogen, Wiring electrically connected to the thin-film resistance element, which is composed of a composition containing at least one element selected from carbon, and which is directly connected to the resistance film through an opening formed in an insulating layer covering the thin-film resistance element It is.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming a resistive film made of a silicon cermet material, and a step of forming an insulating protective film on the resistive film continuously in the same apparatus as the step of forming the resistive film. A step of forming a film, a step of collectively patterning the resistive film and the insulating protective film to form a thin-film resistive element comprising a laminated film of the resistive film and the insulating protective film, and a step of covering the thin-film resistive element. Forming a semiconductor device having a thin film resistance element including a step of forming an insulating layer, wherein the silicon cermet material is selected from oxygen, nitrogen, and carbon as silicon and at least one metal element. It has a composition containing at least one element.

According to the configuration of the semiconductor device of the present invention described above, a thin film resistance element is formed by laminating at least a resistance film made of a silicon cermet material and an insulating protective film on the resistance film. A high-resistance thin-film resistance element having a low temperature coefficient of resistance, heat resistance, and oxidation resistance can be formed by the characteristics of the silicon cermet material, and an insulating protective film can be formed when manufacturing the thin-film resistance element having this configuration. This protects the resistive film and prevents damage to the resistive film surface. Further, since the wiring electrically connected to the thin-film resistance element is directly connected to the resistance film through an opening formed in the insulating layer covering the thin-film resistance element, the contact resistance between the wiring and the resistance film is reduced. be able to. As a result, a change in the resistance value of the thin-film resistance element due to a variation in the contact resistance value or the contact resistance value is avoided.

According to the above-described method of manufacturing a semiconductor device of the present invention, after forming a resistive film made of a silicon cermet material, the insulating film is continuously formed on the resistive film in the same apparatus as in the step of forming the resistive film. Since a resistive film is formed and a resistive film and an insulating protective film are collectively patterned to form a thin-film resistive element, the resistive film is formed of an insulating protective film without forming a natural oxide film on the surface of the resistive film. Can be covered. Further, as described above, the resistive film is protected by the insulating protective film, and damage to the resistive film surface in a later step can be prevented. Thus, a high-resistance thin-film resistance element having the above-described low temperature coefficient of resistance, heat resistance, and oxidation resistance can be manufactured.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention has a thin-film resistance element formed by laminating at least a resistive film made of a silicon cermet material and an insulating protective film on the resistive film. An opening formed in an insulating layer covering the thin-film resistance element, the wiring being made of a composition containing at least one element selected from oxygen, nitrogen, and carbon in one or more metal elements; Through the semiconductor device directly connected to the resistance film.

The present invention also relates to the above semiconductor device,
The metal elements of the silicon cermet material are Ta, Nb,
One or more types are selected from W, Ti, Mo, Ni, V, and Zr.

According to the present invention, in the above semiconductor device,
The structure is such that the insulating protective film has selectivity to etching with respect to the insulating layer covering the thin-film resistance element.

According to the present invention, in the above semiconductor device,
The insulating protective film is made of an oxide or oxynitride of a metal element of a silicon cermet material.

The present invention relates to a method for manufacturing a semiconductor device having a thin-film resistance element, wherein a step of forming a resistance film made of a silicon cermet material and an apparatus identical to the step of forming this resistance film are provided. A step of forming an insulating protective film on the resistive film continuously within the resistive film, and patterning the resistive film and the insulating protective film collectively to form a thin film resistive element comprising a laminated film of the resistive film and the insulating protective film And a step of forming an insulating layer over the thin-film resistance element, wherein the silicon cermet material is silicon and one or more metal elements,
This is a method for manufacturing a semiconductor device having a composition containing at least one element selected from oxygen, nitrogen, and carbon.

Further, according to the present invention, in the method for manufacturing a semiconductor device, the insulating protective film has selectivity to etching with respect to the resistance film and the insulating layer.

FIG. 1 is a schematic configuration diagram (cross-sectional view) of a semiconductor device having a thin film resistance element as one embodiment of the present invention. In this semiconductor device, for example, an insulating layer 2 is formed on a semiconductor substrate or a base 1 formed by forming an epitaxial layer on the semiconductor substrate, and a resistive film 3 and a protective film 4 thereon are laminated on the insulating layer 2. The thin film resistance element 10 made of a film is formed. The insulating layer 5 covers the surface of the thin-film resistance element 10, and the wiring 11 is connected to the resistance film 3 through an opening formed in the insulating layer 5 and the protective film 4 of the thin-film resistance element 10. The wiring 11 is composed of a wiring layer 7 and a base film 6 thereunder. A contact portion 11C is formed so as to fill an opening formed in the insulating layer 5 and the protective film 4 and to be electrically connected to the resistance film 3. Have.

In the present embodiment, in particular, a Si (silicon) cermet material (a composite material of an insulating material and a metal material) is used as the material of the resistance film 3 and the protective film 4 is used.
Is an insulating film.

The Si (silicon) cermet material is Si
(Silicon), a metal element M, and another element (for example, oxygen). As the metal element M, preferably, at least one kind is selected from metals of Ta, Nb, W, Ti, Mo, Ni, V, and Zr. As the other elements, at least one element is selected from reactive elements of oxygen, nitrogen, and carbon.

The silicon, the metal element M, and the source of the reactive species
A cermet having a composition of three or more components is composed of elemental materials. example
M_xSi_yO_z, M_xSi_yN_z, M_xSi_yC_z,
M_xSi_yO_zN _w(X, y, z, w are positive numbers)
Cermets having different compositions can be used.

Resistive film 3 made of silicon cermet material
Is preferably 0.1 KΩ / □ or more. The thickness of the resistance film 3 is preferably 10 nm to 3 nm.
Within the range of 00 nm. The composition ratio of the metal element M and silicon Si of the silicon cermet material is M / (M
+ Si) = 25 to 55 (mol%).

Such a silicon-based cermet material is
For example, it is used for a heating element (heater) such as a thermal printer head or an ink jet head.

As the insulating protective film 4, an insulating metal oxide or an insulating metal oxynitride can be used. Preferably, an oxide or an oxynitride (M _x O _y , M _x O _y N _z, etc.) of the metal element M constituting the cermet of the resistance film 3 is used.
y and z are positive numbers) so as to have good compatibility with the resistance film 3. Further, as the insulating protective film 4, it is also possible to use fine crystalline polycrystalline silicon, amorphous (amorphous) silicon, or a film in which they are mixed.

The sheet resistance of the insulating protective film 4 is preferably set to 100 kΩ / □ or more. The thickness of the protective film 4 is preferably in the range of 5 to 50 nm.

Further, the insulating protective film 4 has a high etching selectivity (selectivity) with respect to the insulating layers 2 and 5 sandwiching the thin-film resistance element 10 above and below, especially the insulation layer 5 covering the thin-film resistance element 10. Is preferred. Usually, in a semiconductor device, a silicon compound (silicon oxide or silicon nitride) is used as a material of the insulating layers 2 and 5. The insulating layer 5 is made of a material such as the above-described insulating metal oxide, insulating metal nitride, microcrystalline polycrystalline silicon, amorphous silicon, or the like.
A material having high etching selectivity to the silicon compound is used for the insulating protective film 4. As a result, the contact portion 11 of the wiring 11 is formed on the insulating layer 5 covering the thin-film resistance element 10.
In the step of performing the etching for forming the opening for C, the insulating protective film 4 can act as an etching stopper.

If the protective film 4 is made of a material having a high etching selectivity with respect to the insulating layer 5 made of a silicon compound as described above, the protective film 4 is made of a material having a high etching selectivity with respect to the resistance film 3 made of a silicon-based cermet material. Etching selectivity is increased. Thereby, the contact portion 11 of the wiring 11 is formed on the protective film.
In a step of performing an etching for forming an opening for C, only the insulating protective film 4 is etched to form the resistive film 3.
Can be prevented from being etched.

The wiring 11 includes Al, Ti, W, Ta, M
One or more elements selected from o and Cu or a material selected from compounds having these as main components can be used. Further, a stacked structure of a plurality of films using these materials may be used. The base film 6 of the wiring 11 can function as a barrier metal particularly by using Ti or the like.

In the semiconductor device of the present embodiment, for example, the material and thickness of the thin-film resistance element 10 and the layers around it may be as follows. (A) Silicon substrate as substrate 1 and Si as insulating layer 2
The O ₂ film is 800 nm in thickness, and the resistive film 3 is Ta-SiO
₂ cermet (Ta: SiO ₂ = 45: 55 in molar ratio)
Film thickness 80 nm (sheet resistance 3 k [Omega / □), as a protective film 4 of insulating thickness 25nm and Ta _x O _y, the insulating layer 5
A SiO ₂ film having a thickness of 400 nm as the wiring 11
In order from the lower layer, Ti / TiON / Ti are each formed with a film thickness of 30.
A laminated structure of nm / 70 nm / 30 nm (corresponding to the base film 6), an Al-Si film having a thickness of 800 nm, and a TiON film having a thickness of 25 nm are formed. (B) GaAs substrate as base 1, Si as insulating layer 2
₃ N ₄ film is 300 nm in thickness, and Ta-Si is used as the resistance film 3.
O ₂ cermet (Ta: SiO ₂ = 45: 5 in molar ratio)
5) film thickness 80 nm (sheet resistance 3 k [Omega / □), as a protective film 4 of insulating, film thickness Ta _x O _y 25 nm, the the Si ₃ N ₄ film thickness 300 nm, as a wiring 11 as an insulating layer 5, In order from the lower layer, a Ti film is 50 nm thick (corresponding to the underlayer 6), a Pt film is 50 nm thick, and an Au film is 500 nm thick.
m, respectively.

Further, the semiconductor device of the present embodiment has the above-described features in its structure and also has features in its manufacturing process as described below.

First, in order to suppress the fluctuation of the resistance value of the thin film resistance element 10, not only the resistance film 3 and the protection film 4 are laminated, but also preferably, the resistance film 3 is formed continuously in the same sputtering apparatus. The film and the protective film 4 are formed. This allows
The surface of the resistive film 3 is covered with the protective film 4 without being oxidized or damaged.

Further, since the protective film 4 is formed on the resistive film 3, the resistive film 3 is not exposed to an oxygen atmosphere or oxygen plasma, and the resistive film 3 is formed by an alkaline chemical such as a stripping chemical. Corrosion can also be avoided. In other words, in the subsequent steps, for example, in the film formation and patterning steps of the wiring layer 7 and the like, the surface of the resistive film 3 is prevented from being chemically changed by an oxygen atmosphere or an etching chemical and damaged by oxygen plasma. This suppresses a change in the resistance value of the thin-film resistance element 10, so that the resistance value of the thin-film resistance element 10 can be further improved in accuracy.

When patterning the thin-film resistance element 10 composed of the resistance film 3 and the protective film 4, after forming a pattern with a photoresist, the processing is performed by either reactive ion etching RIE or ion milling. . At this time, it is desirable to process the resistive film 3 and the protective film 4 collectively using the same photoresist as a mask.

The thin film resistor 10 and the thin film resistor 10
In forming the contact portion 11C with the wiring 11 connected to the substrate, the insulating layer 5 covering the thin-film resistance element 10 is processed by reactive ion etching (RIE) or processing by an etching chemical, or An opening (connection hole) for the contact portion 11C is formed by a combination of the above processes. Further, the insulating protective film 4 is processed to form an opening (connection hole) for the contact portion 11C. The process of processing the insulating layer 5 made of a silicon compound and the process of processing the insulating protective film 4 can be performed by switching the etching process conditions using the same equipment and the same mask.

Then, as described above, the insulating protective film 4
Is made of a material having a high etching selectivity with respect to the insulating layer 5 made of a silicon compound, thereby performing a high selectivity etching by a reactive ion etching (RIE) method to form a connection hole in the insulating layer 5. In the etching to be performed, the protective film 4 can be used as an etching stopper. At this time, the thickness of the insulating protective film 4 is set to a thickness that can sufficiently withstand the etching stopper. Conditions for performing this high selectivity etching include, for example, CF ₄ , CHF ₃ , C ₂ F ₆ , C ₄ F ₈ ,
Adopting at least one gas species of Ar and CO,
Reactive ion etching (RIE) may be performed by generating the plasma.

Similarly, the material of the insulating protective film 4 is made of a material having a high etching selectivity with respect to the resistive film 3 made of a silicon cermet material, so that a material having a high selectivity is obtained by the reactive ion etching (RIE) method. The resistive film 3 can be used as an etching stopper in etching for forming an opening for forming the contact portion 11C of the wiring 11 in the protective film 4 by performing etching. Conditions for performing this etching with a high selectivity include, for example, Cl ₂ , BCl ₃ , SF ₆ , and CH ₂ F in an etching gas.
₂ , at least one gas species, or CF ₄ , CH
At least one of F ₃ , C ₂ F ₆ , C ₄ F ₈ , Ar and CO
More specifically, reactive ion etching (RIE) may be performed by employing a plurality of types of gases and generating plasma thereof.

By performing the manufacturing as described above, the resistance film 3 of the thin film resistance element 10 and the wiring 11
Can be stably electrically connected to each other, and furthermore, the contact resistance value between the resistance film 3 and the wiring 11 can be constantly stabilized. It is possible to suppress.

The semiconductor device having the thin film resistance element 10 shown in FIG. 1 can be specifically manufactured, for example, as follows. Note that the material and the thickness of each layer are described as the above-described configuration (A). First, FIG. 2A
As shown in FIG. 1, an insulating layer 2 made of, for example, SiO ₂ is formed on a substrate 1 to a thickness of, for example, 800 nm.

Next, as shown in FIG. 2B, a resistive film 3 made of, for example, a Ta—SiO ₂ cermet material is formed on the insulating layer 2 to a thickness of, for example, 80 nm by sputtering.
Further, the protective film 4 made of, for example, Ta ₂ O ₅ is continuously formed in the same sputtering apparatus by sputtering, for example, by ₂₅ n.
m to form a film. Here, when the composition of the cermet material is Ta / (Ta + SiO ₂ ) = 45% (molar ratio), the sheet resistance of the resistive film 3 is 3 kΩ / □.
On the other hand, the protective film 4 made of Ta ₂ O ₅ has a sheet resistance of 3M.
Ω / □ or more.

Next, a heat treatment is performed at 450 ° C. for 15 minutes in a hydrogen atmosphere to reduce the stress of the thin-film resistance element 10.
Stabilizes thermal fluctuations. Although the sheet resistance of the resistive film 3 fluctuates by about 8% due to this heat treatment step, the fluctuation of the resistance value when the same heat treatment is performed in the subsequent manufacturing steps is avoided. Note that this heat treatment step may be performed after the wiring 11 is formed.

Next, as shown in FIG. 2C, a photoresist 21 for forming a pattern of the thin-film resistance element 10 is formed on the protective film 4. Subsequently, as shown in FIG. 2D,
The resistive film 3 and the protective film 4 are collectively processed by etching using the photoresist 21 to pattern the resistive film 3 and the protective film 4. The etching at this time is performed, for example, by RI using a plasma generator.
Using E (reactive ion etching), the etching is performed, for example, in a mixed gas (BCl ₃ + Cl ₂ ) atmosphere at a pressure of 10 mTorr.

After patterning the resistive film 3 and the protective film 4, resist ashing is performed by a plasma generating apparatus. That is, as shown in FIG. 2E, the photoresist 21X remaining on the protective film 4 is removed by the oxygen plasma 22.
Ashing is performed under a pressure of 1.6 Torr, for example, using a gas containing oxygen as a main component. At this time,
The insulating protective film 4 made of Ta ₂ O ₅ is made of Ta-SiO
_It plays a role of protecting the resistance film 3 made of _two cermets from damage caused by irradiation of the oxygen plasma 22.

Further, residual organic matter after ashing,
A cleaning step for removing the polymer, the etching residue, the deteriorated resist layer, and the like is performed. As shown in FIG. 3F, the surface is subjected to a chemical treatment with, for example, an alkaline organic stripping solution 23. At this time, the insulating protective film 4 made of Ta ₂ O ₅ protects the resistive film 3 made of Ta—SiO ₂ cermet from the alkaline corrosive chemical solution 23 and prevents corrosion and etching damage of the resistive film 3. Fulfill.

After the ashing and the chemical treatment described above, the thin film resistance element 10 composed of the laminated film of the resistance film 3 and the protection film 4 is completed as shown in FIG. 3G. Next, as shown in FIG. 3H, the laminated film of the thin-film resistance element 10 is covered, and an insulating layer 5 made of, for example, SiO _{2 is} formed to a thickness of, for example, 400 nm by a plasma CVD method. The plasma CVD temperature is a low temperature of 400 ° C. or less. If necessary, a surface smoothing step is performed thereafter. In this smoothing step, S
Although a coating film such as OG (Spin on glass) is used, the thin film resistance element 10 is not affected because the insulating layer 5 covers the coating film.

Subsequently, the insulating layer 5 covering the thin-film resistance element 10
A connection hole is formed in the substrate. As shown in FIG. 3I, a photoresist 24 is formed on the insulating layer 5 and the photoresist 2
4, an opening 25 for forming a connection hole is formed.

Next, as shown in FIG. 4J, using the photoresist 24 in which the opening 25 is formed as a mask, the insulating layer 5 is processed by, for example, RIE (reactive ion etching) using a plasma device. An opening is formed in 5. At this time, the insulating protective film 4 made of Ta ₂ O _{5 is used.}
Is used as an etching stopper for etching the insulating layer 5 made of SiO ₂ , the conditions of the plasma etching are, for example, a mixed gas (CF ₄ + CHF ₃₎ as an etching gas.
+ Ar), and the processing pressure is 500 mTorr. By adopting this condition, the etching selectivity is 10 or more (S
iO ₂ etch rate / Ta ₂ O ₅ etch rate).

Subsequently, as shown in FIG. 4K, the protective film 4 is processed by RIE using the photoresist 24 as a mask to form an opening in the protective film 4.
At this time, in order to use the resistive film 3 made of a Ta—SiO ₂ cermet material as an etching stopper for the insulating protective film 4 made of Ta ₂ O ₅ , the conditions of the plasma etching are, for example, a mixed gas (SF ₆₎ as an etching gas. + C
l ₂ ), and the processing pressure is 16 mTorr. By adopting this condition, an etching selectivity of 8 or more (Ta ₂ O
₅ etch rate / Ta-SiO ₂ etch rate).

Thereafter, as shown in FIG. 4L, the photoresist 24 on the insulating layer 5 is removed. Subsequently, a base film 6 and a wiring layer 7 are sequentially formed using a sputtering apparatus,
The underlying film 6 and the wiring layer 7 are patterned into a predetermined pattern to form the wiring 11 as shown in FIG. 4M.
As the base film 6, for example, a stacked structure of, for example, Ti / TiON / Ti is formed so as to have a total film thickness of 130 nm, for example, to be a barrier metal. As the wiring layer 7, for example, Al-
An Si alloy is formed to a thickness of, for example, 800 nm. Thus, the thin film resistance element 1 of the present embodiment shown in FIG.
A semiconductor device having 0 can be manufactured.

According to the above-described embodiment, since the silicon cermet material is used for the resistance film 3 of the thin-film resistance element 10, the sheet resistance, which is a characteristic of the silicon cermet material, is 10 kΩ / □ and the temperature coefficient of resistance is less than ±±. 100 ppm /
From the characteristic of ° C., a relatively high sheet resistance and a low temperature coefficient of resistance can be obtained in the thin-film resistance element 10, and the thin-film resistance element 10 having high resistance and less affected by heat treatment (having heat resistance) can be configured. . Further, the thin-film resistance element 10 having acid resistance and oxidation resistance can be constituted from the characteristic that the acid resistance and oxidation resistance, which are the characteristics of the silicon cermet material, can be ensured up to 600 ° C.

Further, by forming the thin-film resistance element 10 by laminating the insulating protection film 4 on the resistance film 3, the surface of the resistance film 3 is protected by the protection film 4. In the resist ashing step, the stripping liquid step, and the like after the patterning, it is possible to prevent the resistive film 3 made of the silicon cermet material from being damaged or chemically changed. Thereby, the fluctuation of the resistance value of the thin-film resistance element 10 due to the damage of the resistance film 3 or the like is suppressed, and the thin-film resistance element 1
It is possible to increase the precision of 0.

Further, the wiring 11 is connected to the thin-film resistance element 10 by using the insulating protective film 4 as a material having etching selectivity with respect to the insulating layer 5 made of a silicon compound covering the resistance film 3. In the step of forming an opening in the insulating layer 5 by etching to form the contact portion 11C, the insulating protective film 4 acts as an etching stopper, so that etching damage to the resistive film 3 can be avoided. Further, since the insulating protective film 4 has etching selectivity with respect to the resistance film 3 made of a silicon cermet material, a step of forming an opening in the insulating protective film 4 by etching to form the contact portion 11C. In this case, the wiring 11 can be reliably connected to the resistive film 3 so that the etching residue of the insulating protective film 4 does not remain or the resistive film 3 is not etched. Therefore, the contact resistance component, which is the parasitic resistance of the thin-film resistance element 10, can be reduced, and the variation in the contact resistance can be suppressed. As a result, the precision of the resistance value of the thin-film resistance element 10 can be further improved. Can be planned.

That is, according to the semiconductor device of the present embodiment,
Particularly, in the high-resistance thin-film resistance element 10, it is possible to realize a high-precision resistance value and high reliability.

Although it has conventionally been impossible to mount a silicon-based cermet material on a semiconductor integrated circuit device composed of a silicon-based insulating film having a similar composition, the semiconductor cermet material is manufactured using the semiconductor device of the present embodiment. The present invention can be realized without causing a significant increase in cost and without requiring a complicated element structure and complicated manufacturing steps.

Further, since the resistance element is constituted by the thin film resistance element 10, the space occupied by the resistance element can be reduced as compared with the resistance element using the diffusion resistance, and the semiconductor device can be miniaturized and miniaturized. Can be achieved.

The structure of the thin-film resistance element 10 is such that a silicon cermet material is used for the resistance film 3, an insulating protective film 4 is laminated on the resistance film 3, and a connection hole for connecting the wiring 11 is protected. Other than the fact that it is also formed on the film 4, it is the same as a conventional resistance element using a polycrystalline silicon film, and has a relatively simple configuration. For this reason, the manufacturing process of the thin-film resistance element 10 is the same as the manufacturing process of the conventional resistance element using a polycrystalline silicon film except that the step of forming the insulating protective film 4 is increased. The manufacturing process of the thin-film resistance element 10 can be incorporated in the manufacturing process. Further, since the formation of the insulating protective film 4 is performed continuously in the same sputtering apparatus as the process of forming the resistive film 3, the increase in the manufacturing cost due to the additional process of forming the protective film 4 does not increase. small.

As described above, according to the present embodiment, a complicated device configuration and a complicated manufacturing process are not required. Therefore,
According to the present embodiment, it is possible to manufacture a semiconductor device having the high-resistance thin-film resistance element 10 at a relatively low cost without increasing the manufacturing cost, and to reduce the resistance element 1
Resistance element 10 having good characteristics by suppressing the fluctuation of the resistance value of 0
Can be manufactured stably.

Subsequently, as another embodiment of the present invention,
Bi incorporating the structure of the thin film resistance element 10 shown in FIG.
FIG. 5 shows a schematic configuration diagram (cross-sectional view) of the CMOS semiconductor device. This BiCMOS semiconductor device has an N-type epitaxial layer 42 on a silicon substrate 41 as shown in FIG.
Are formed to form a base. On this base, a CMOS transistor section 31 composed of a PMOS transistor 31P and an NMOS transistor 31N, a bipolar transistor section 32 composed of a vertical NPN bipolar transistor (hereinafter referred to as an NPN transistor), and a thin film resistor And a resistance element section 33 having the element 30. An element isolation layer 4 formed by LOCOS is formed on the surface of the substrate.
4 are formed, and each transistor 31P, 31N, 32
Are separated.

[0079] PMOS transistor 31P of the CMOS transistor 31, N on the surface of the substrate ^- the semiconductor well region 45 is formed, the N ^- semiconductor well region 45 of the
A P-type source / drain region 47 is formed therein. Channels are formed inside these source / drain regions 47. A gate electrode G having a laminated structure of a polycrystalline silicon film 55 and a silicide film 56 is formed on the channel via a gate oxide film. On the side wall of the gate electrode G, a side wall made of an insulating film is formed. In the P-type source / drain region 47,
A wiring 64 having a three-layer structure of a base film 61, a wiring layer 62, and a conductive antireflection film 63 is connected.

The NMOS transistor 31N of the CMOS transistor section 31 has a base (semiconductor epitaxial layer 4).
A semiconductor well region 46 of P ⁻ is formed on the surface of 2),
An N-type source / drain region 48 is formed in the P ⁻ semiconductor well region 46. Channels are formed inside the source / drain regions 48. These source / drain regions 48 have N-type low concentration regions (so-called LDD regions) inside (on the channel side). A gate electrode G having a laminated structure of a polycrystalline silicon film 55 and a silicide film 56 is formed on the channel via a gate oxide film. On the side wall of the gate electrode G, a side wall made of an insulating film is formed. The N-type source / drain region 48 has a base film 6
1, a wiring 64 having a three-layer structure of a wiring layer 62 and a conductive antireflection film 63 is connected.

Vertical NP of bipolar transistor section 32
The N bipolar transistor has an N-type buried diffusion region 43 formed inside a semiconductor substrate.
Then, a base region 49 is formed in the N-type epitaxial layer 42, and an emitter region 50 is formed near a central surface of the base region 49. In the collector take-out portion, a collector take-out region 51 is formed so as to be connected to the N-type buried diffusion region 43. A base electrode having a three-layer structure in which a silicide film 58 is interposed between polycrystalline silicon films 57 is connected to the base region 49. An emitter electrode having a three-layer structure in which a silicide film 60 is sandwiched by a polycrystalline silicon film 59 is connected to the emitter region 50. And the base electrode is CM
A base wiring 64B having a three-layer structure similar to the wiring 64 of the OS transistor portion 31 is connected, an emitter electrode 64E having a three-layer structure is connected to the emitter electrode, and a collector wiring having a three-layer structure is connected to the collector extraction region 51. 64C is connected.

The resistive element portion 33 is formed with a resistive film 3 made of a silicon cermet material having the same configuration as the thin film resistive element 10 shown in FIG. Consisting of This thin film resistance element 30
Are formed on the insulating layers 52 and 53 formed on the element isolation layer 44, and the surface is covered with a thin insulating film 54. Through the openings formed in the insulating film 54 and the protective film 4, the CM
A wiring 64R having a three-layer structure similar to the wiring 64 of the OS transistor section 31 is directly connected to the resistance film 3 of the thin-film resistance element 30.

Although not shown in FIG. 5, each wiring 6
4, 64B, 64E, 64C and 64R are covered with an insulating layer, and an upper layer wiring or the like is further formed on the insulating layer to form a BiC.
A MOS semiconductor device is configured.

In this embodiment, since the thin-film resistance element 30 of the resistance element section 33 has the same configuration as the thin-film resistance element 10 shown in FIG. 1, similar to the above-described embodiment,
A high-resistance thin-film resistance element having a high-precision resistance value can be configured.

In this embodiment, the thin film resistance element 3
The wiring 64R connected to the zero resistance film has the same three-layer structure 6 as the wiring 64 of the CMOS transistor part 31 and the wirings 64B, 64E, and 64C of the bipolar transistor part 32.
1, 62 and 63, and can be formed simultaneously in the same process. Further, an insulating film covering the gate electrode G of the CMOS transistor unit 31 and the resistance element unit 3
The insulating film covering the third thin-film resistance element 30 is the same insulating film 54.

Since the resistance element is constituted by the thin film resistance element 30, the resistance value of the resistance element is not affected by the parameters of the characteristics of the CMOS transistor section 31 and the bipolar transistor section 32. Therefore, the element design of the resistance element section 33 and the CMOS transistor section 31
And the design of the bipolar transistor section 32 can be performed more freely with less restrictions.

Next, the BiC of this embodiment shown in FIG.
The manufacturing process of the MOS semiconductor device will be described with reference to FIGS. It should be noted that an element isolation layer 44 is provided inside a base comprising a silicon substrate 41 and an N-type semiconductor epitaxial layer 42.
The description of the steps of forming each semiconductor region is omitted. Forming a gate electrode G on a base via a gate insulating film;
After a sidewall made of an insulating film is formed on the side wall of the gate electrode G, the insulating film 52 is entirely covered over the gate electrode G.
To form Further, in the bipolar transistor section 32, the opening is formed by removing the insulating film 52 on the base region 49. Next, a polycrystalline silicon film 57, a silicide film 58, and a polycrystalline silicon film 57 are formed on the insulating film 52.
A layer is formed and patterned to form a base electrode having a three-layer structure. This base electrode is made of an insulating film 52
Is connected to the base region 49 through the opening. Next, a relatively thick insulating layer 53 is formed to cover the base electrode.
Further, in the bipolar transistor section 32, an opening is formed in the base region and the insulating layer 53 on the emitter region 50 and the base region 49 in the vicinity thereof. A sidewall is further formed on the side wall of the opening by an insulating film. Thereafter, a polycrystalline silicon film 59
Three layers of a silicide film 60 and a polycrystalline silicon film 59 are formed, and are patterned to form an emitter electrode having a three-layer structure. This emitter electrode is connected to the emitter region 50 through an opening in the base electrode and the insulating layer 53. The emitter electrode and the base electrode are separated by the sidewall formed on the side wall of the opening of the base electrode.
Next, a resistive film 3 made of a silicon cermet material and a protective film 4 are sequentially formed so as to cover the insulating layer 53 and the emitter electrode. Then, in the resistive element portion 33, a photoresist 81 for forming a resistive element pattern is formed on the protective film 4. FIG. 6 shows this state.

Next, as shown in FIG. 7, the protective film 4 and the resistive film 3 are collectively patterned using the photoresist 81 as a mask. Subsequently, the photoresist 81 is removed, and the surface is covered with the insulating film 54 as shown in FIG. Thus, the thin-film resistance element 30 including the resistance film 3 and the protection film 4 is covered with the insulating film 54.

Next, as shown in FIG.
A photoresist 82 having an opening for forming a contact portion to 0 is formed, and etching is performed using the photoresist 82 as a mask to form an opening (connection hole) in the insulating film 54. Subsequently, as shown in FIG.
Using the same photoresist 82 as a mask, etching is performed under different conditions to form openings (connection holes) in the protective film 4.

Next, the photoresist 82 is removed, and as shown in FIG.
A photoresist 83 having an opening for forming a connection hole of the bipolar transistor portion 32 is formed, and the insulating film 54, the insulating layer 53, and the insulating film 52 are etched using the photoresist 83 as a mask. Then, openings (connection holes) reaching the source / drain regions 57 and 58, the base electrode, and the collector extraction region 51, respectively, are formed.

Next, as shown in FIG. 12, the photoresist 83 is removed. Further, a base film 61, a wiring layer 62,
By sequentially forming three layers of the conductive anti-reflection film 63 and patterning the three layers, as shown in FIG.
The wiring 64 of the OS transistor section 31, the wirings 64B, 64E, 64C of the bipolar transistor section 32, and the wiring 64R of the resistance element section 33 are formed. In this way,
The BiCMOS semiconductor device having the configuration shown in FIG. 5 can be manufactured. Thereafter, an interlayer insulating layer and an upper layer wiring are formed as necessary.

Next, as still another embodiment of the present invention, FIG. 14 shows a schematic configuration diagram (cross-sectional view) of a BiCMOS semiconductor device incorporating the structure of the thin-film resistance element 10 shown in FIG. This BiCMOS semiconductor device has a schematic configuration similar to that of FIG. 5, but differs in the vicinity of an emitter wiring 64E of a bipolar transistor portion 32 composed of a vertical NPN bipolar transistor (hereinafter referred to as an NPN transistor). That is, the resistance film 3 and the protection film 4 of the thin-film resistance element 30 exist on the left and right sides of the emitter wiring 64E and the emitter electrode as layers between the emitter wiring 64E and the emitter electrode. The resistive film 3 in this portion is in contact with the base film 61 of the emitter wiring 64 and the side walls of the polycrystalline silicon film 59 and the silicide film 60 of the emitter electrode.
It is a conductor integrated with the emitter wiring 64 and the emitter electrode. Other configurations are the same as those in FIG.
A duplicate description is omitted.

Further, the Bi of this embodiment shown in FIG.
The manufacturing process of the CMOS semiconductor device is shown in FIGS. First, up to the state shown in FIG. 6 of the above embodiment,
Manufacturing is performed in the same manner as in the previous embodiment. Next, before patterning the thin film resistance element 30 with the photoresist 81, a photoresist 84 is formed so as to cover the emitter electrode portion of the bipolar transistor section 32. Then, as shown in FIG. 15, the protective film 4 and the resistive film 3 are etched using the two photoresists 81 and 84 as a mask. As a result, a pattern of the thin-film resistance element 30 is formed by the resistive film 3 and the protective film 4, and the resistive film 3 and the protective film 4 remain over the emitter electrode.

Subsequently, the photoresists 81 and 84 are removed, and an insulating film 54 is formed on the surface as shown in FIG. At this time, the resistive film 3 and the protective film 4 covering the emitter electrode are covered with the insulating film 54.

Next, as shown in FIG. 17, an opening (connection hole) is formed in the insulating film 54 on the thin-film resistance element 30 by performing etching using the photoresist 82 as a mask. Further, as shown in FIG. 18, etching is performed using the same photoresist 82 as a mask under different conditions to form openings (connection holes) in the protective film 4 of the thin-film resistance element 30.

Next, the photoresist 82 is removed, and as shown in FIG.
And a photoresist 83 having an opening for forming a connection hole of the bipolar transistor portion 32 is formed. Using the photoresist 83 as a mask, the insulating film 54, the insulating layer 53, the insulating film 52, and the protective film on the emitter electrode are formed. 4
And the resistive film 3 are etched,
Openings (connection holes) reaching the source / drain regions 57 and 58, the base electrode, and the collector extraction region 51 are formed.

Next, as shown in FIG. 20, the photoresist 83 is removed. Further, a base film 61, a wiring layer 62,
By sequentially forming three layers of the conductive anti-reflection film 63 and patterning the three layers, as shown in FIG.
The wiring 64 of the OS transistor section 31, the wirings 64B, 64E, 64C of the bipolar transistor section 32, and the wiring 64R of the resistance element section 33 are formed. In this way,
A BiCMOS semiconductor device having the configuration shown in FIG. 14 can be manufactured. Thereafter, an interlayer insulating layer and an upper layer wiring are formed as necessary.

In each of the above embodiments, the present invention is applied to the BiCMOS semiconductor device having the CMOS transistor section 31 and the bipolar transistor section 32, and the resistance element section 33 having the thin film resistance element 30 is formed. However, the present invention can be applied to a semiconductor device having another configuration. For example, a capacitor (capacitor), a PNP bipolar transistor, or the like may be provided in addition to the configuration of each of the above embodiments.

The present invention is not limited to the above-described embodiment, and may take various other configurations without departing from the gist of the present invention.

[0100]

According to the present invention described above, by forming a thin-film resistance element by laminating at least a resistive film made of a silicon cermet material and an insulating protective film, a low temperature coefficient of resistance can be obtained due to the characteristics of the silicon cermet material. A high-resistance thin-film resistance element having heat resistance and oxidation resistance can be formed, and when the thin-film resistance element having this configuration is manufactured, the resistance film is protected by an insulating protective film, and the surface of the resistance film is protected. To prevent damage. Accordingly, it is possible to suppress a change in the resistance value of the thin-film resistance element due to damage to the surface of the resistance film.

In the manufacture of a semiconductor device having a thin-film resistance element, after forming a resistance film made of a silicon cermet material, an insulating protective film is continuously formed on the resistance film in the same device. By patterning the resistive film and the insulating protective film collectively, the resistive film can be covered with the insulating protective film without forming a natural oxide film on the surface of the resistive film. As a result, it is possible to avoid a change in resistance value due to a natural oxide film on the surface of the resistive film and an increase in contact resistance with the wiring.

Further, by directly connecting a wiring electrically connected to the thin-film resistance element to the resistance film through an opening formed in the insulating layer covering the thin-film resistance element, the contact resistance between the wiring and the resistance film is reduced. Therefore, the fluctuation of the resistance value of the thin film resistance element due to the magnitude of the contact resistance and the variation of the contact resistance value is avoided.

Therefore, according to the present invention, it is possible to realize a highly reliable semiconductor device having high accuracy of the resistance value of the thin film resistance element while suppressing the fluctuation of the resistance value of the thin film resistance element. In addition, since a large increase in manufacturing cost does not occur and a complicated element structure and complicated manufacturing steps are not required, it becomes easy to mount a thin-film resistance element made of a silicon cermet material on a semiconductor device.

Further, when the insulating protective film is made of a material having etching selectivity with respect to the insulating layer made of a silicon compound covering the resistive film, in the step of forming a contact portion for connecting a wiring to the resistive element, An etching damage to the resistance film can be avoided, and the wiring can be securely connected to the resistance film. As a result, it is possible to suppress the contact resistance component of the resistance element to be low, and also to suppress the variation fluctuation of the contact resistance component.
It is possible to further improve the accuracy of the resistance value of the thin-film resistance element.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram (cross-sectional view) of a semiconductor device having a thin-film resistance element according to an embodiment of the present invention.

2A to 2E are process diagrams showing a manufacturing process of the semiconductor device of FIG. 1;

FIGS. 3A to 3F are process diagrams showing a manufacturing process of the semiconductor device of FIG. 1;

4A to 4M are process diagrams showing a manufacturing process of the semiconductor device of FIG. 1;

FIG. 5 is a schematic configuration diagram (cross-sectional view) of a BiCMOS semiconductor device according to another embodiment of the present invention.

FIG. 6 is a process chart showing a manufacturing process of the BiCMOS semiconductor device of FIG. 5;

7 is a process chart showing a manufacturing process of the BiCMOS semiconductor device of FIG. 5;

FIG. 8 is a process chart showing a manufacturing process of the BiCMOS semiconductor device of FIG. 5;

FIG. 9 is a process chart showing a manufacturing process of the BiCMOS semiconductor device of FIG. 5;

FIG. 10 is a process chart showing a manufacturing process of the BiCMOS semiconductor device of FIG. 5;

FIG. 11 is a process chart showing a manufacturing process of the BiCMOS semiconductor device of FIG. 5;

FIG. 12 is a process chart showing a manufacturing process of the BiCMOS semiconductor device of FIG. 5;

FIG. 13 is a process chart showing a manufacturing process of the BiCMOS semiconductor device of FIG. 5;

FIG. 14 shows a BiCMO according to still another embodiment of the present invention.
1 is a schematic configuration diagram (cross-sectional view) of an S semiconductor device.

FIG. 15 is a process chart showing a manufacturing process of the BiCMOS semiconductor device of FIG. 14;

FIG. 16 is a process chart showing a manufacturing process of the BiCMOS semiconductor device of FIG. 14;

FIG. 17 is a process chart showing a manufacturing process of the BiCMOS semiconductor device of FIG. 14;

FIG. 18 is a process chart showing a manufacturing process of the BiCMOS semiconductor device of FIG. 14;

FIG. 19 is a process chart showing a manufacturing process of the BiCMOS semiconductor device of FIG. 14;

FIG. 20 is a process chart showing a manufacturing process of the BiCMOS semiconductor device of FIG. 14;

FIG. 21 is a process chart showing a manufacturing process of the BiCMOS semiconductor device of FIG. 14;

FIG. 22 is a schematic configuration diagram (cross-sectional view) of a thin-film resistance element using a silicon cermet material.

23A and 23B are schematic configuration diagrams (cross-sectional views) of thin-film resistance elements using a silicon cermet material.

FIG. 24 is a schematic configuration diagram (cross-sectional view) of a thin-film resistance element using a silicon cermet material.

FIG. 25 is a schematic configuration diagram (cross-sectional view) of a thin-film resistance element using a silicon cermet material.

FIG. 26 is a schematic configuration diagram (cross-sectional view) of a thin-film resistance element using a silicon cermet material.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Substrate, 2, 5, 53 insulating layer, 3 resistance film, 4 insulating protective film, 6 base film, 7 wiring layer, 10, 30
Thin film resistance element, 11, 64, 64B, 64E, 64C,
64R wiring, 21, 24, 81, 82, 83, 84
Photoresist, 31 CMOS transistor part, 32
Bipolar transistor part, 33 resistance element part, 5
2,54 insulating film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 21/8249 F-term (Reference) 5F038 AR07 AR15 AR25 AV05 AV06 EZ15 EZ20 5F048 AA09 AC05 AC10 BA02 BA12 BB05 BB08 BB12 BC06 BE03 BF12 BG12 CA07 CA13 DA23 5F082 AA21 AA38 BA04 BC09 BC18 DA09 DA10 EA13 EA15 EA27

Claims (6)

[Claims] 1. A thin-film resistance element comprising at least a resistive film made of a silicon cermet material and an insulating protective film on the resistive film. The element includes a composition including at least one element selected from oxygen, nitrogen, and carbon, and a wiring electrically connected to the thin-film resistance element passes through an opening formed in an insulating layer covering the thin-film resistance element. And a semiconductor device directly connected to the resistance film. 2. The semiconductor device according to claim 1, wherein the metal element of the silicon cermet material is at least one selected from the group consisting of Ta, Nb, W, Ti, Mo, Ni, V, and Zr. 3. The semiconductor device according to claim 1, wherein the insulating protective film has etching selectivity with respect to an insulating layer covering the thin-film resistance element. 4. The semiconductor device according to claim 1, wherein said insulating protective film is made of an oxide or oxynitride of a metal element of said silicon cermet material. 5. A method for manufacturing a semiconductor device having a thin-film resistance element, comprising: forming a resistive film made of a silicon cermet material; and forming the resistive film in the same apparatus. A step of continuously forming an insulating protective film on the resistive film, and patterning the resistive film and the insulating protective film collectively, from the laminated film of the resistive film and the insulating protective film. Forming a thin-film resistance element, and forming an insulating layer covering the thin-film resistance element, wherein the silicon cermet material includes silicon, one or more metal elements, oxygen, nitrogen, and carbon. A method of manufacturing a semiconductor device, comprising a composition containing at least one element selected from the group consisting of: 6. The method according to claim 5, wherein the insulating protective film has etching selectivity with respect to the resistance film and the insulating layer.